CN107040208A - Circuit arrangement, oscillator, electronic equipment and moving body - Google Patents
Circuit arrangement, oscillator, electronic equipment and moving body Download PDFInfo
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- CN107040208A CN107040208A CN201611167174.2A CN201611167174A CN107040208A CN 107040208 A CN107040208 A CN 107040208A CN 201611167174 A CN201611167174 A CN 201611167174A CN 107040208 A CN107040208 A CN 107040208A
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/02—Details
- H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
- H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
- H03B5/36—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
Abstract
Circuit arrangement, oscillator, electronic equipment and moving body.Circuit arrangement is included：Digital interface portion；Processing unit；Oscillator signal generative circuit, it generates oscillator signal；Clock signal generating circuit, it is generated the clock signal of the frequency after the frequency frequency multiplication of oscillator signal；And digital interface portion, the 1st of the connection of clock signal generating circuit the, the 3rd terminal group.1st terminal group is configured at the 1st region along the 1st side of circuit arrangement, the 3rd terminal group is configured at the 2nd, the 3rd, any one terminal area in the 4th terminal area.
Description
Technical field
The present invention relates to circuit arrangement, oscillator, electronic equipment and moving body etc..
Background technology
All the time, it is known to OCXO (oven controlled crystal oscillator：Constant temperature crystal vibrates
Device), TCXO (temperature compensated crystal oscillator：Temperature compensated crystal oscillator) etc.
Oscillator.Reference signal source in such as OCXO is as base station, network router, measuring apparatus and used.Such
In the oscillators such as OCXO, TCXO, the high precision int presence to frequency of oscillation is required.
As the prior art of such oscillator, for example, there is the skill disclosed in Japanese Unexamined Patent Publication 2015-82815 publications
Art.In the prior art, for the high precision int of frequency of oscillation, the age correction of frequency of oscillation has been carried out.Specifically, if
Storage part and elapsed time measurement portion are put, the storage part is to the corrected value of the control voltage of frequency of oscillation and pair in elapsed time
Relation information is answered to be stored.Moreover, according to the corrected value and the correspondence relationship information in elapsed time stored in storage part and
The elapsed time measured by elapsed time measurement portion performs age correction.
So, in the oscillators such as OCXO, TCXO, it is desirable to the high precision int of the frequency of oscillation of oscillator signal.In addition, sometimes
The clock signal of outside system requirements and frequency of oscillation different frequency.
On the other hand, in order to tackle the ring using the frequency control data generating unit formation PLL circuit outside circuit arrangement
The purposes such as road, it is also considered that digital interface portion is set in the circuit arrangement.
But, it is known that when setting such digital interface portion, it may be caused due to the communication noise in digital interface portion
Phase noise etc. cause clock signal, the precise decreasing of oscillator signal.
The content of the invention
According to several modes of the present invention, it is possible to provide a kind of circuit arrangement that can generate the few clock signal of noise etc.,
Oscillator, electronic equipment and moving body etc..
The mode of the present invention is related to circuit arrangement, and the circuit arrangement is included：Digital interface portion；Processing unit, its via
The digital interface portion input has the data from external device (ED), carries out signal transacting；Oscillator signal generative circuit, it is using shaking
Son and the frequency control data from the processing unit, generate the vibration for setting frequency of oscillation by the frequency control data and believe
Number；Clock signal generating circuit, it at least has phase comparing section, generates after the frequency of oscillation frequency multiplication of the oscillator signal
The clock signal of frequency；1st terminal group of the connection in the digital interface portion；The vibration electricity of the oscillator signal generative circuit
2nd terminal group of the connection on road；And the 3rd terminal group of the connection of the clock signal generating circuit, setting circuit dress
Put with the 1st while intersect while be the 2nd while, with the described 1st while it is relative while for the 3rd while, with the described 2nd when relative be
In the case of 4 sides, the 1st terminal group is configured at the 1st terminal area along the 1st side, and the 3rd terminal group is configured at
Along the described 2nd while the 2nd terminal area, along the described 3rd while the 3rd terminal area, the 4th terminal along the 4th side
Any one terminal area in region.
In the mode of the present invention, processing unit is entered data into from external device (ED) via digital interface portion, and hold
Row signal transacting.And by oscillator signal generative circuit, shaken using oscillator with the generation of the frequency control data from processing unit
Signal is swung, and is generated by clock signal generating circuit by the clock letter of the frequency after the frequency of oscillation frequency multiplication of oscillator signal
Number.Moreover, in the mode of the present invention, the 1st terminal group of the connection in digital interface portion is configured at the edge of circuit arrangement
The 1st terminal area on the 1st side.On the other hand, the 3rd terminal group of the connection of clock signal generating circuit is configured at the 2nd,
3rd, any one terminal area in the 4th terminal area.In such manner, it is possible to make the 1st terminal group of the connection in digital interface portion with
The distance of 3rd terminal group of the connection of clock signal generating circuit is separated.Thereby, it is possible to reduce by logical in digital interface portion
Caused by noise sound etc., the phase noise that is produced in clock signal etc., can be achieved that few clock signal of noise etc. can be generated
Circuit arrangement.
In addition, the present invention a mode in, Ke Yishi, the 2nd terminal group be configured at the 2nd terminal area with
A terminal area in 3rd terminal area, the 3rd terminal group is configured at the 2nd terminal area and the 3rd end
Another terminal area in subregion.
In such manner, it is possible to make the 2nd terminal group of the 1st terminal group of the connection in digital interface portion and the connection of oscillating circuit
Distance and digital interface portion connection the 1st terminal group and clock signal generating circuit connection the 3rd terminal group
Distance separate.Thereby, it is possible to reduce caused by communication noise in digital interface portion etc., in clock signal or oscillator signal
Phase noise of middle generation etc..
In addition, in the mode of the present invention, Ke Yishi, the 1st side is the short side of circuit arrangement, the 1st end
Subgroup is configured at the 1st terminal area along the 1st side as short side.
In such manner, it is possible to make the 1st terminal group for example separate corresponding with the length on the long side of circuit arrangement with other terminal groups
Distance, can reduce phase noise etc. caused by communication noise in digital interface portion etc..
In addition, in the mode of the present invention, Ke Yishi is being set between the 1st terminal group and the 2nd terminal group
Distance be that the distance between L12, the 1st terminal group and described 3rd terminal group are L13, the 2nd terminal group and described the
In the case that the distance between 3 terminal groups are L23, at least one in L12 and L13 is longer than L23.
In such manner, it is possible to make the 1st terminal group with the 2nd terminal group apart from L12, the distance of the 1st terminal group and the 3rd terminal group
L13 is elongated, it is achieved thereby that reduction of phase noise etc..
In addition, in the mode of the present invention, Ke Yishi, to input signal and base based on the oscillator signal
The frequency control data for the foreign frequency control data generating unit that calibration signal is compared is via the 1st terminal group, the number
Word interface portion is input into the processing unit, and the oscillator signal generative circuit is generated according to from the foreign frequency control data
The frequency control data that portion is inputted via the processing unit, generates the oscillator signal.
In such manner, it is possible to which foreign frequency control data generating unit of the efficient, flexible with the outside for being arranged at circuit arrangement, raw
Into the oscillator signal that frequency of oscillation is set by the frequency control data from the foreign frequency control data generating unit.
In addition, in the mode of the present invention, Ke Yishi, the circuit arrangement is included to based on the defeated of the oscillator signal
Enter the phase comparing section that the phase of signal and the reference signal is compared, the oscillator signal generative circuit is in the 1st pattern
Under, generated according to the frequency control data inputted from the foreign frequency control data generating unit via the processing unit
The oscillator signal, under the 2nd pattern, according to the frequency control inputted from the phase comparing section via the processing unit
Data processed generate the oscillator signal.
In such manner, it is possible to which tackling the system of outside has a case that foreign frequency control data generating unit and without outside
The situation both of these case of frequency control data generating unit, realizes raising of convenience etc..
In addition, in the mode of the present invention, Ke Yishi, the digital interface portion is to include serial data line and serial
The serial interface circuit of 2 lines of clock line, 3 lines or 4 lines.
So, can be outer with this in the case of the serial interface circuit in external device (ED) with 2 lines, 3 lines or 4 lines
Between part device, the serial line interface processing of 2 lines, 3 lines or 4 lines is carried out, by the data input from external device (ED) to processing unit.
In addition, the present invention a mode in, Ke Yishi, set from the described 1st direction while towards the described 3rd as
In the case of 1st direction, the processing unit is configured at the 1st direction side of the 1st terminal group.
In such manner, it is possible to by the data from external device (ED) inputted using the terminal of the 1st terminal group via digital interface
Portion is input to processing unit with the signal path of short path.Thereby, it is possible to reduce the communication noise by being produced in digital interface portion
Caused harmful effect.
In addition, in the mode of the present invention, Ke Yishi, the 2nd terminal group is configured at the 2nd terminal area,
3rd terminal group is configured at the 3rd terminal area, is setting situation of the opposite direction in the 1st direction as the 2nd direction
Under, the clock signal generating circuit is configured at the 2nd direction side of the 3rd terminal group.
So, can be by clock signal generating circuit between clock signal generating circuit and the terminal of the 3rd terminal group
Output signal or input signal are exported or inputted with the signal path of short path.Thereby, it is possible to reduce by clock signal
Harmful effect caused by the clocking noise produced in generative circuit.
In addition, in the mode of the present invention, Ke Yishi, the processing unit is configured at the 1st terminal area and institute
State between clock signal generating circuit.
So, between the 1st terminal group of the 1st terminal area and the 3rd terminal group of the 3rd terminal area across processing unit with
And clock signal generating circuit.Therefore, as the distance between the 1st terminal group and the 3rd terminal group, at least it is able to ensure that and handles
The width in portion and the corresponding distance of the width of clock signal generating circuit, can reduce the communication by being produced in digital interface portion
Harmful effect caused by noise etc..
In addition, in the mode of the present invention, Ke Yishi, when the oscillating circuit is configured at the processing unit and is described
Between clock signal generating circuit.
So, between the 1st terminal group of the 1st terminal area and the 3rd terminal group of the 3rd terminal area across processing unit,
Oscillating circuit and clock signal generating circuit.Therefore, as the distance between the 1st terminal group and the 3rd terminal group, at least can
Ensure distance corresponding with the width of the width of processing unit, the width of oscillating circuit and clock signal generating circuit, can drop
The low harmful effect caused by communication noise for being produced in digital interface portion etc..
In addition, the present invention a mode in, Ke Yishi, set from the described 2nd direction while towards the described 4th as
In the case of 3rd direction, the oscillating circuit is configured at the 3rd direction side of the 2nd terminal group.
In such manner, it is possible to be connected oscillating circuit with the terminal of the 2nd terminal group with the signal wire of short path, it can reduce by this
Harmful effect caused by parasitic capacitance of signal wire etc..
In addition, in the mode of the present invention, Ke Yishi, the oscillator is the constant temperature groove profile oscillator with thermostat,
Thermostat control comprising the constant temperature groove profile oscillator is configured at the 4th terminal along the 4th side with the 4th terminal group of terminal
Region.
The 4th of thermostat control terminal is included in such manner, it is possible to effectively be configured using the 4th terminal area of circuit arrangement
Terminal group.
In addition, in the mode of the present invention, Ke Yishi, the circuit arrangement is included and the thermostat control terminal
The thermostat control circuit of the thermostat control of the constant temperature groove profile oscillator is connected and carried out, is being set from the 4th side direction
In the case that the direction on the 2nd side is the 4th direction, the thermostat control circuit is configured at the institute of the 4th terminal area
State the 4th direction side.
In such manner, it is possible to control circuit and the thermostat of the 4th terminal group to control to use thermostat with the signal path of short path
Terminal is connected, and can realize more appropriate thermostat control.
In addition, in the mode of the present invention, Ke Yishi, the oscillating circuit is configured at the thermostat control circuit
Between the 2nd terminal area.
Thereby, it is possible to efficient, flexible thermostat control is configured with the region between the 4th terminal area and the 2nd terminal area
Circuit and oscillating circuit processed, realize the raising of positioning efficiency and the reduction of noise etc. in which can take into account.
In addition, in the mode of the present invention, Ke Yishi, the processing unit, which handled by Kalman filtering, to be estimated
The processing of the true value of the frequency control data, and according to the aging of the true value progress frequency control data estimated
Correction.
In such manner, it is possible to realize the age correction for the influence for considering observation noise and system noise, it is possible to increase aging school
Positive precision.
In addition, the other modes of the present invention are related to oscillator, the oscillator is included：Electricity described in any one above-mentioned mode
Road device；And the oscillator.
In addition, the other modes of the present invention are related to the electronics comprising the circuit arrangement described in any one above-mentioned mode and set
It is standby.
In addition, the other modes of the present invention are related to the moving body for including the circuit arrangement described in any one above-mentioned mode.
Brief description of the drawings
Fig. 1 is the basic structure example of the circuit arrangement of present embodiment.
Fig. 2 is the detailed construction example of the circuit arrangement of present embodiment.
Fig. 3 is the explanation figure of the phase noise problems for oscillator signal.
Fig. 4 is the explanation figure of the phase noise problems for oscillator signal.
Fig. 5 is the layout configuration structure example of the circuit arrangement of present embodiment.
Fig. 6 is other layout configuration structure examples of the circuit arrangement of present embodiment.
Fig. 7 is other layout configuration structure examples of the circuit arrangement of present embodiment.
Fig. 8 is other layout configuration structure examples of the circuit arrangement of present embodiment.
Fig. 9 is other layout configuration structure examples of the circuit arrangement of present embodiment.
Figure 10 is other layout configuration structure examples of the circuit arrangement of present embodiment.
Figure 11 is the 1st configuration example of clock signal generating circuit.
Figure 12 is the 2nd configuration example of clock signal generating circuit.
Figure 13 is the configuration example of temperature sensor.
Figure 14 is the configuration example of oscillating circuit.
Figure 15 is the 1st configuration example in digital I/F portions.
Figure 16 is the 2nd configuration example in digital I/F portions.
Figure 17 is the configuration example of reference signal generative circuit.
Figure 18 is the configuration example that thermostat controls circuit.
Figure 19 is the explanation figure of the component deviation for aging characteristics.
Figure 20 is the explanation figure for holding pattern (hold-over).
Figure 21 is the explanation figure for holding pattern.
Figure 22 is the explanation figure for the age correction for having used Kalman filtering to handle.
Figure 23 is the explanation figure for the age correction for having used Kalman filtering to handle.
Figure 24 is the detailed construction example of processing unit.
Figure 25 is the action specification figure of processing unit.
Figure 26 is the action specification figure of processing unit.
Figure 27 is the configuration example in age correction portion.
Figure 28 is the explanation figure of modified embodiment of the present embodiment.
Figure 29 is the configuration example of oscillator.
Figure 30 is the configuration example of electronic equipment.
Figure 31 is the configuration example of moving body.
Figure 32 is the detailed construction example of oscillator.
Figure 33 is the configuration example of the base station as one of electronic equipment.
Embodiment
Hereinafter, the preferred embodiment of the present invention is described in detail.In addition, the present embodiment illustrated below is not to right
Present disclosure described in claim carries out improper restriction, and all structures illustrated in the present embodiment are not all necessary
It is the solution of the present invention.
1. the structure of circuit arrangement
Fig. 1 shows the basic circuit structure of the circuit arrangement of present embodiment.As shown in figure 1, the electricity of present embodiment
Road device is included：Digital I/F portions 30, processing unit 50, oscillator signal generative circuit 140, clock signal generating circuit 160, the 1st,
2nd, the 3rd terminal group TG1, TG2, TG3.Furthermore it is possible to include register portion 32.In addition, the circuit arrangement of present embodiment is not
It is limited to Fig. 1 structure, can implements to omit one part structural element (such as clock signal generating circuit) or add other
The various modifications such as structural element.
Digital I/F portions (interface portion) 30 be carry out with the external device (ED) (microcomputer, controller etc.) of circuit arrangement it
Between interface processing circuit.Such as numeral I/F portions 30 are for inputting data (numerical data, numeral from external device (ED)
Signal) or output data to the interface of external device (ED).Have in processing unit 50 via the input of digital I/F portions 30 from outside
The data of device.For example there are the data from external device (ED) via the input of register portion 32.Processing unit 50 is according to the data of input
Carry out various signal transactings.
Digital I/F portions 30 can be realized by carrying out the circuit of serial line interface processing.For example numeral I/F portions 30 can lead to
The serial interface circuit of 2 lines comprising serial data line and serial time clock line, 3 lines or 4 lines is crossed to realize.That is, digital I/F portions
30 interface processing can be realized by using the serial communication mode of serial time clock line and the synchronous mode of serial data line.
I2C (Inter-Integrated Circuit can for example be passed through：Internal integrated circuit) mode, 3 lines or 4 lines SPI
(Serial Peripheral Interface：Serial Peripheral Interface (SPI)) mode etc. realizes.
Register portion 32 is the circuit being made up of multiple registers such as status register, command register, data register.
The external device (ED) of circuit arrangement accesses each register in register portion 32 via digital I/F portions 30.Moreover, external device (ED) can make
Confirm the state of circuit arrangement with the register in register portion 32 or order is sent to circuit arrangement.Or, can be to circuit
Device (processing unit 50) transmits data or reads data etc. from circuit arrangement (processing unit 50).
Processing unit 50 carries out various signal transactings according to the data inputted.For example, to via digital I/F portions 30 from outside
The frequency control data DFCI (FREQUENCY CONTROL code) of device (such as foreign frequency control data generating unit) input is carried out at signal
Reason.In addition, as described later, can be to coming in the case that in the inside of circuit arrangement, frequency control data generating unit is set
From frequency control data DFCI (the phase bit comparisons based on internal phase comparing section of the frequency control data generating unit of the inside
As a result frequency control data) carry out signal transacting.
Specifically, processing unit 50 (digital signal processing section) (comes from outside or internal to frequency control data DFCI
Frequency control data) carry out age correction processing, Kalman filtering processing, always according to needing to carry out the letter such as temperature-compensating processing
Number processing (Digital Signal Processing).Moreover, the frequency control data DFCQ after signal transacting is output into oscillator signal generation electricity
Road 140.The processing unit 50 can realize by ASIC circuits such as gate arrays, can also be by processor (DSP, CPU) and in processor
The program (program module) of upper work is realized.
Oscillator XTAL is, for example, that AT cuts type or SC cuts quartz vibrator of type equal thickness scissoring vibration type etc. or bending
The piezoelectric vibrator of oscillatory type etc..As one, oscillator XTAL is disposed in the thermostat of constant temperature groove profile oscillator (OCXO)
Type, but not limited to this can be the TCXO of the type without thermostat oscillator.Oscillator XTAL can also be humorous
Shake device (electromechanical resonator or the resonance circuit of electric).In addition, as oscillator XTAL, SAW (Surface can be used
Acoustic Wave：Surface acoustic wave) resonator, be used as silicon damping son MEMS (Micro Electro Mechanical
Systems：Microelectromechanical systems) oscillator etc. is used as piezoelectric vibrator.As oscillator XTAL baseplate material, usable quartz,
The piezoelectric ceramics such as the piezoelectric single crystals such as lithium tantalate, lithium niobate, lead zirconate titanate equipressure electric material or silicon semiconductor material etc..As shaking
Sub- XTAL motivator, can both use the means based on piezo-electric effect, can also use the electrostatic drive based on Coulomb force.
The generation oscillator signal of oscillator signal generative circuit 140 OSCK.Such as oscillator signal generative circuit 140 is used from place
The frequency control data DFCQ (frequency control data after signal transacting) and oscillator XTAL in reason portion 50, generation pass through FREQUENCY CONTROL
The oscillator signal OSCK of the frequency of oscillation of data DFCQ settings.As one, oscillator signal generative circuit 140 make oscillator XTAL by
Vibrated according to by the frequency control data DFCQ frequencies of oscillation set, generation oscillator signal OSCK.
In addition, oscillator signal generative circuit 140 can generate oscillator signal OSCK in direct digital synthesiser mode
Circuit.For example can also be using oscillator XTAL (oscillation source of built-in oscillation frequency) oscillator signal as reference signal, with numeral
Mode generates the oscillator signal OSCK by the frequency control data DFCQ frequencies of oscillation set.
Oscillator signal generative circuit 140 can include D/A converter sections 80 and oscillating circuit 150.But, oscillator signal generation electricity
Road 140 is not limited to such structure, can implement omission a portion structural element or additional other structures key element etc. various
Deformation.
D/A converter sections 80 carry out the D/A of the frequency control data DFCQ (output data of processing unit) from processing unit 50
Conversion.Be input to after the signal transacting that the frequency control data DFCQ of D/A converter sections 80 is processing unit 50 (such as age correction,
After temperature-compensating or the processing of Kalman filtering) frequency control data (FREQUENCY CONTROL code).It is used as D/A converter sections 80
D/A conversion regimes, for example, can use resistance serial type (resistance Splittable).But, D/A conversion regime not limited to this can also be used
The various modes such as resistance ladder type (R-2R ladder types etc.), capacitor array type or PWM-type.In addition, D/A converter sections 80 except
Beyond D/A converter, circuit, modulation circuit (jitter modulation or PWM etc.), filter circuit can also be controlled comprising it
Deng.
Oscillating circuit 150 uses the output voltage VQ and oscillator XTAL of D/A converter sections 80, generation oscillator signal OSCK.Shake
Swing circuit 150 and be connected to oscillator XTAL via the 1st, the 2nd oscillator terminal (oscillator pad).For example, oscillating circuit 150 is logical
Crossing makes oscillator XTAL (piezoelectric vibrator, resonator etc.) vibrate and generate oscillator signal OSCK.Specifically, oscillating circuit 150 makes
Oscillator XTAL is so that the frequency of oscillation of the output voltage VQ of D/A converter sections 80 as frequency control voltage (vibrational control voltage) to be entered
Row vibration.For example, being to control the circuit (VCO) that the vibration to oscillator XTAL is controlled using voltage in oscillating circuit 150
In the case of, the variable capacitance capacitor (transfiguration that oscillating circuit 150 can change comprising capacitance according to frequency control voltage
Diode etc.).
In addition, as described above, oscillating circuit 150 can be realized by direct digital synthesiser mode, in this case,
Oscillator XTAL frequency of oscillation turns into reference frequency, the frequency as the frequency of oscillation different from oscillator signal OSCK.
Clock signal generating circuit 160 generates clock signal CK according to oscillator signal OSCK.Such as clock signal generation electricity
Road 160 at least has phase comparing section 161 (comparing and computing unit), generates the frequency after oscillator signal OSCK frequency of oscillation frequency multiplication
The clock signal CK of rate.Clock signal generating circuit 160 is for example with output buffer 168, and output buffers electricity by the output
Clock signal CK after the buffering of road 168.The clock signal generating circuit 160 is the PLL circuit with such as PLL loops.PLL electricity
Road can be analog form or digital form (ADPLL).In addition, generating oscillator signal OSCK frequency of oscillation
In the case of clock signal CK after frequency multiplication, frequency (overtones band) can be more than 1, can also be smaller than 1.In addition, frequency
It is not limited to integer or decimal.
1st terminal group TG1 of connection of the circuit arrangement comprising numeral I/F portions 30, oscillator signal generative circuit 140 shake
Swing the 2nd terminal group TG2, the 3rd terminal of the connection of clock signal generating circuit 160 (PLL circuit) of the connection of circuit 150
Group TG3.Here, the terminal group of connection refers to the meaning of the terminal group of the external connection for making each circuit block and external connection
Think.These TG1~TG3 each terminal group (pad group) is for example comprising multiple terminals (pad).Terminal is external connection terminals, is used
Inputted or output signal (data signal, analog signal) between (external device (ED)) outside Yu Yu.
For example, the 1st, the 2nd, the 3rd terminal group TG1, TG2, TG3 be and digital I/F portions 30, oscillating circuit 150, clock signal
The terminal group that generative circuit 160 is connected.1st, the 2nd, the 3rd terminal group TG1, TG2, TG3 can be via I/O units and numeral I/F
Portion 30, oscillating circuit 150, each circuit block connection of clock signal generating circuit 160.As I/O units, exist slow with input
Rush the input I/O units of device, the output I/O units with output buffer, with input buffer and output buffer
Input and output I/O units etc..For example by signal from outside input to digital I/F portions 30, oscillating circuit 150, clock signal life
Into circuit 160 each circuit block in the case of, can by signal from the 1st, the 2nd, the 3rd terminal group TG1, TG2, TG3 each terminal
Each circuit block is input to via input I/O units (or input and output I/O units).It is outer signal is output to from each circuit block
In the case of portion, signal via output I/O units (or input and output I/O units) can be output to the 1st by each circuit block, the
2nd, the 3rd terminal group TG1, TG2, TG3 each terminal.These I/O units can be set between each circuit block and each terminal, also may be used
To be not provided with these I/O units.
The 1st terminal group TG1 in digital I/F portions 30 can for example include the serial of the serial line interface in numeral I/F portions 30
The terminal (pad) of clock line, the terminal (pad) of serial data line.In addition, there is signal input serial data line and letter
In the case of number output serial data line, the 1st terminal group TG1 can include the terminal and letter of signal input serial data line
The terminal of number output serial data line.In addition, the 1st terminal group TG1 is in addition to these terminals, such as power supply can also be included
Voltage VSS (GND) terminal, piece selects terminal etc..
2nd terminal group TG2 of oscillating circuit 150 can for example include the be connected with oscillator XTAL the 1st, the 2nd oscillator and use
Terminal (oscillator pad).For example the 1st oscillator terminal is connected with oscillator XTAL one end, the 2nd oscillator terminal and oscillator
XTAL other end connection.In addition, the 2nd terminal group TG2 can include such as oscillator signal OSCK lead-out terminal, stable electricity consumption
The connection terminal of container, frequency of oscillation adjust the connection terminal of electricity container or the connection terminal of wave filter etc..
3rd terminal group TG3 of clock signal generating circuit 160 can for example include clock signal CK lead-out terminal.
For example in different multiple clock signal CK1~CKj (such as Figure 33 of the output frequency of clock signal generating circuit 160 (frequency)
CK1~CK5) in the case of, can comprising export these multiple clock signal CK1~CKj multiple lead-out terminals.In addition,
3rd terminal group TG3 can comprising output by buffer circuit 168 buffer before the lead-out terminal of clock signal (pll clock signal is defeated
Go out terminal) and buffering before clock signal input terminal (pll clock signal input terminal).In addition, Figure 11 as be described hereinafter that
Sample, as the oscillator VCXO for the outside that circuit arrangement is used in the generation in the clock signal CK of clock signal generating circuit 160
In the case of, the 3rd terminal group TG3 can include the lead-out terminal of the frequency control voltage to oscillator VCXO.
Fig. 2 shows the detailed construction example of the circuit arrangement of present embodiment.In fig. 2, the structure relative to Fig. 1, enters one
It (is inventionbroadly phase that step, which is provided with temperature sensor 10, A/D converter sections 20, storage part 34, frequency control data generating unit 40,
Comparing section), reference signal generative circuit 180, thermostat control circuit 190, the 4th terminal group TG4 etc..In addition, circuit arrangement
Structure is not limited to Fig. 2 structure, can implement to omit one part structural element (such as frequency control data generating unit, benchmark
Signal generating circuit, thermostat control circuit etc.) or the various modifications such as additional other structures key element.Setting can for example be used
Temperature sensor in the outside of circuit arrangement is used as temperature sensor 10.
The output temperature of temperature sensor 10 detection voltage VTD.Specifically, will be according to the temperature of environment (circuit arrangement)
The temperature-independent voltage of change is exported as temperature detection voltage VTD.The concrete structure example of temperature sensor 10 is repeated later.
A/D converter sections 20 carry out the A/D conversions of the temperature detection voltage VTD from temperature sensor 10, output temperature inspection
Survey data DTD.For example export digital temperature detection data DTD corresponding with temperature detection voltage VTD A/D transformation results
(A/D result datas)., for example can be using gradually manner of comparison or with gradually being compared as the A/D conversion regimes of A/D converter sections 20
Mode similar mode etc..Also, A/D conversion regimes are not limited to this mode, (attribute, ratio in parallel in various manners can be adopted
Compared with type or Serial-Parallel Type etc.)
Various information needed for the various processing of the memory circuit arrangement of storage part 34, action.The storage part 34 for example can
Realized by nonvolatile memory.As nonvolatile memory, such as can use EEPROM.As EEPROM,
MONOS (Metal-Oxide-Nitride-Oxide-Silicon can for example be used：Metal oxidation-silicon oxynitride) type storage
Device etc..The flash memory for the memory that make use of MONOS types can for example be used.Or as EEPROM, floating gate type etc. can be used
Other kinds of memory.In addition, as long as storage part 34 can also preserve the storage of simultaneously storage information even if power supply is not supplied
Device, such as also can by fuse circuit realize.
The storage part 34 for example store Kalman filtering processing system noise setting system noise constant (V) with
And the observation noise constant (W) of the setting of the observation noise of Kalman filtering processing.Such as the system in product (oscillator)
Make, shipment when, carry out the measurement (inspection) for monitoring the various information such as frequency of oscillation.And system is determined according to the measurement result
System noise constant, observation noise constant, and write such as in the storage part 34 of the realization as nonvolatile memory.So, energy
Enough realize reduces dysgenic system noise constant, the setting of observation noise constant caused by component deviation.
Processing unit 50 includes holding mode treatment portion 52 (circuit or program module that keep mode treatment), Kalman's filter
Ripple portion 54 (Kalman filtering processing circuit or program module), age correction portion 56 (age correction processing circuit or
Program module), temperature compensation division 58 (temperature-compensating processing circuit or program module).Keep mode treatment portion 52 carry out with
The related various processing of holding pattern.Kalman filtering portion 54 is handled by Kalman filtering and is for example obtained FREQUENCY CONTROL number
According to the processing of the true value of (frequency of oscillation).Age correction portion 56 is carried out for compensating the aging school that frequency of oscillation changes with time
Just.Temperature compensation division 58 enters at the temperature-compensating of line of hitch oscillator frequency according to the temperature detection data DTD from A/D converter sections 20
Reason.Specifically, temperature compensation division 58 according to the temperature detection data DTD (temperature-independent data) changed corresponding to temperature with
And the coefficient data (data of the coefficient of approximate function) of temperature-compensating processing etc., carry out for there are the feelings of temperature change
Reduce the temperature-compensating processing of the variation of frequency of oscillation under condition.
Reference signal RFCK is input to circuit via the terminal TRFCK (pad) of the external connection terminals as circuit arrangement
Device.The signal PLOCK notified whether is in the lock state to outside PLL circuit via as the outside of circuit arrangement to connect
The terminal TPLOCK (pad) of connecting terminal is input to circuit arrangement.Outside PLL circuit is the outside by being arranged at circuit arrangement
Foreign frequency control data generating unit 200 and be arranged at circuit arrangement inside oscillator signal generative circuit 140 constitute
PLL circuit.
The generation frequency control data of frequency control data generating unit 40 DFCI.For example by the input based on oscillator signal OSCK
Signal is compared with reference signal RFCK, generation frequency control data DFCI.The frequency control data DFCI generated is defeated
Enter to processing unit 50.Here, the input signal based on oscillator signal OSCK can be oscillator signal OSCK in itself or by
The signal (such as the signal after dividing) of oscillator signal OSCK generations.Hereinafter, with input signal it is mainly oscillator signal OSCK sheets
Illustrated in case of body.
Frequency control data generating unit 40 includes phase comparing section 41 and digital filtering part 44.Phase comparing section 41 (compares
Operational part) it is electricity of the progress as the oscillator signal OSCK and reference signal RFCK of input signal phase bit comparison (comparison operation)
Road, includes counter 42, TDC 43 (time-to-digit converter).
Counter 42 generates numerical data, and the numerical data with reference signal RFCK reference frequency (such as 1Hz) with being removed
With the integer portion correspondence of result obtained by oscillator signal OSCK frequency of oscillation.TDC 43 generates the fractional part with the result of division
Corresponding numerical data.TDC 43 for example comprising：Multiple delay elements；Multiple latch cicuits, they are reference signal RFCK's
Regularly the multiple delay clock signals exported by multiple delay elements are latched at edge (height)；And circuit, it is more by carrying out
The coding of the output signal of individual latch cicuit, generates numerical data corresponding with the fractional part of result of division.Moreover, phase bit comparison
Portion 41 is by the numerical data corresponding with integer portion from counter 42 and from the digital numbers corresponding with fractional part of TDC 43
According to addition, the phase error between detection and setpoint frequency.Moreover, digital filtering portion 44 is by carrying out the smoothing of phase error
Processing, generation frequency control data DFCI.For example setting frequency of the oscillator signal OSCK frequency as FOS, reference signal RFCK
For FRF, in the case that divider ratio corresponding with setpoint frequency (frequency dividing ratio) is FCW, so that FOS=FCW × FRF relation is set up
Mode generate frequency control data DFCI.Or, counter 42 can be counted to oscillator signal OSCK clock number.
That is, counter 42 carries out counting action by the input signal based on oscillator signal OSCK.Also, phase comparing section 41 can lead to
Cross integer, by reference signal RFCK n cycle (n be may be set to more than 2 integer) in counter 42 count value and
The desired value (n × FCW) of count value is compared.Slave phase bit comparison portion 41 exports the count value of such as desired value and counter 42
Difference, be used as phase error data.
In addition, the structure of frequency control data generating unit 40 is not limited to the structure shown in Fig. 2, various modifications can be implemented.
For example, phase comparing section 41 can be made up of the phase-comparison circuit of analog circuit, or by the filtering part (loop of analog circuit
Wave filter) constitute digital filtering portion 44.Furthermore, it is possible to be processing (the phase error number that processing unit 50 carries out digital filtering portion 44
According to smoothing techniques).For example, processing unit 50 handles with other and (keeps mode treatment, Kalman filtering processing etc.) sequentially
Carry out the processing in digital filtering portion 44.Phase comparative result (phase error data) of such as processing unit 50 to phase comparing section 41
It is filtered processing (smoothing techniques).
In addition, in the present embodiment, additionally it is possible to by the foreign frequency control data for the outside for being arranged at circuit arrangement
Generating unit 200 and oscillator signal generative circuit 140, form the loop of PLL circuit.In this case, from foreign frequency control
The frequency control data DFCI of data generating section 200 is input to processing unit 50 via digital I/F portions 30.50 pairs of processing unit is from outer
The frequency control data DFCI of portion's frequency control data generating unit 200 carries out the signal transactings such as temperature-compensating processing, age correction,
Frequency control data DFCQ after signal transacting is input into oscillator signal generative circuit 140.Moreover, oscillator signal generative circuit
140 use frequency control data DFCQ generation oscillator signals OSCK.The oscillator signal OSCK of generation is via the 2nd terminal group TG2
Lead-out terminal be output to foreign frequency control data generating unit 200.Foreign frequency control data generating unit 200 carries out the vibration
Signal OSCK and reference signal RFCK phase bit comparison (comparison operation) generates frequency control data DFCI.The foreign frequency control
Data generating section 200 processed can be realized by the structure same with frequency control data generating unit 40 inside circuit arrangement,
Phase comparing section and digital filtering portion with counter and TDC can for example be included.
The reference signals such as the generation reference voltage V of reference signal generative circuit 180 RF, reference current IRF.The reference signal is given birth to
Benchmark is generated into the generative circuit of constant pressure such as can include band gap reference voltage of circuit 180, according to constant pressure generated etc.
Voltage VRF circuit, reference current IRF circuit etc. is generated according to constant pressure generated etc..The reference voltage V RF that is generated,
Reference current IRF is fed into analog circuit (such as A/D converter sections 20, D/A converter sections 80 or the thermostat control of circuit arrangement
Circuit 190 processed etc.).Analog circuit carries out analog circuitry processes using these reference voltage Vs RF, reference current IRF.
Thermostat controls oscillator (double thermostats, the Dan Heng that circuit 190 is the constant temperature groove profile with thermostat in oscillator XTAL
Warm groove etc.) in the case of, carry out the oscillator XTAL of constant temperature groove profile thermostat control.For example thermostat control circuit 190 is controlled
The heating of the heater (heater element) of the adjustment of thermostat temperature.Specifically, using the perseverance being correspondingly arranged with heater
The temperature sensor of warm groove control controls the heating of heater.Moreover, so that thermostat temperature turns into the side of design temperature
Formula enters trip temperature adjustment.
4th terminal group TG4 is the connection terminal group (pad group) of (external connection use) of thermostat control circuit 190.
Oscillator XTALs of the 4th terminal group TG4 comprising constant temperature groove profile thermostat control terminal.For example the 4th terminal group TG4 can be wrapped
The lead-out terminal of the control voltage containing heater is used as thermostat control terminal.For example in the situation of described later pair of constant temperature slot structure
Under, the lead-out terminal of 2 heater control voltages corresponding with the control of each thermostat can be included.In addition, the 4th terminal group
TG4 can (in the case of double constant temperature slot structures, be and 2 comprising the connection terminal of temperature sensor of thermostat control
Corresponding 2 connection terminals of temperature sensor), thermostat control stabilising condenser connection terminal or thermostat control
The input terminal of reference voltage etc..
2. phase noise
As described above, in the circuit arrangement of present embodiment, being provided with digital I/F portions 30, processing unit 50 being capable of basis
The data inputted from external device (ED) via digital I/F portions 30 carry out various signal transactings.As one, as described above, frequency control
Data DFCI processed is transfused to everywhere from as the foreign frequency control data generating unit 200 of external device (ED) via digital I/F portions 30
Reason portion 50.Moreover, oscillator signal generative circuit 140 generates oscillator signal according to the frequency control data DFCQ after signal transacting
OSCK, oscillator signal OSCK feeds back to foreign frequency control data generating unit 200 via the 2nd terminal group TG2 lead-out terminal,
Thus, the PLL loops of outside PLL circuit are formd.
In addition, in the present embodiment, being provided with generation by the frequency after oscillator signal OSCK frequency of oscillation frequency multiplication
Clock signal CK clock signal generating circuit 160.In such manner, it is possible to be shaken by clock signal generating circuit 160 according to constant
The oscillator signal OSCK for swinging frequency generates the clock signal CK of arbitrary frequency, and is supplied to and is assembled with the electronics of circuit arrangement and sets
Standby each circuit.If by taking the electronic equipment of Figure 33 described later base station as an example, clock signal generating circuit 160 can be passed through
Clock signal CK1~CK5 is generated, and is supplied to each circuit for constituting base station.
In this case, frequency control data generating unit 40 (phase comparing section 41) or foreign frequency control data are passed through
PLL circuit (hereinafter referred to as the 1st grade of PLL circuit) and low frequency that generating unit 200 and oscillator signal generative circuit 140 are constituted
Generate oscillator signal OSCK to the reference signal RFCK Phase synchronizations of (such as 1Hz).Therefore, by being locked as low-frequency benchmark
It is small but in high frequency that the oscillator signal OSCK of signal RFCK the 1st grade of PLL circuit generation turns into phase noise in low-frequency band
The big signal of phase noise in band.Such as being superimposed with various noises in the reference signal RFCK from GPS, by
In the influence of the noise etc., phase noise increases of the oscillator signal OSCK in high frequency band.
On the other hand, the 2nd grade of the PLL circuit realized by clock signal generating circuit 160 compares reference signal with frequency
Clock signal CK is generated to oscillator signal OSCK Phase synchronizations high RFCK, therefore, it is possible to reduce the phase noise in high frequency band.
Therefore, according to the PLL circuit by the 1st grade generates oscillator signal OSCK, by the 2nd grade of PLL circuit, (clock signal generates electricity
Road 160) and the circuit arrangement of clock signal CK present embodiment is generated by oscillator signal OSCK, pass through the 1st grade of PLL circuit
The phase noise in low-frequency band can be reduced, the phase noise in high frequency band can be reduced by the 2nd grade of PLL circuit.Therefore,
Have the advantages that the small clean clock signal CK of phase noise can be being generated from the broadband of low-frequency band tremendously high frequency band.Example
Such as in Figure 33 described later base station, receptivity in order to improve RF circuits 608 etc. is supplied to RF circuits 608, it is necessary to reduce
Clock signal CK5 phase noise., can be in the wideband from low-frequency band tremendously high frequency band according to the circuit arrangement of present embodiment
The low clock signal CK5 (=CK) of phase noise is generated in band and RF circuits 608 are supplied to, the raising of receptivity is realized
Deng.
So, in the circuit arrangement of present embodiment, have the following advantages that：Come dual by using 2 grades of PLL circuits
Ground reduces phase noise, can generate the few clean clock signal CK of noise.
But, in the present embodiment, due to being provided with digital I/F portions 30, thus, it is found that there are the following problems：By
The communication noise that the digital I/F portions 30 are produced result in clock signal CK phase noise increase.For example, numeral I/F portions 30
Communication noise in terminal group TG1 is delivered to the terminal group TG3 of clock signal generating circuit 160, makes clock signal CK phase
Noise increase.
For example, Fig. 3 is the figure for the phase noise example for showing clock signal CK.Transverse axis is frequency, and the longitudinal axis is phase noise.Figure
3 G1 is phase noise corresponding with the frequency of the communication clock in digital I/F portions 30.For example in digital I/F portions 30, string is used
Row clock line and serial data line are communicated, but produce in clock signal CK the communication clock frequency of the serial time clock line
The phase noise of (such as 100KHz).In addition, shown in the low G3 of the frequency band even in the high G2 of the frequency than G1, the frequency than G1
Frequency band in, also produce big phase noise.So, when the big phase noise shown in G1, G2, G3 is superimposed upon clock signal CK
When middle, the problems such as receptivity for for example generating Figure 33 RF circuits 608 declines.
Moreover, when the noise of the terminal group TG2 generations by oscillating circuit 150 is delivered to clock signal generating circuit 160
Terminal group TG3, or on the contrary, when being delivered to terminal group TG2 by the terminal group TG3 noises produced, phase noise further increases
Plus.
3. layout configuration
In the present embodiment, in order to solve the above the problem of, using the layout method of following explanation.For example Fig. 5 is shown
One of the layout configuration of the circuit arrangement of present embodiment.In addition, the layout of the circuit arrangement in present embodiment is configured not
It is limited to Fig. 5 configuration, various modifications (such as Fig. 6~Figure 10 described later) can be implemented.
As shown in Figure 1, Figure 2, Figure 5, the circuit arrangement of present embodiment includes numeral I/F portions 30, processing unit 50, vibration letter
Number generative circuit 140 (oscillating circuit 150), clock signal generating circuit 160 (PLL circuit), the 1st, the 2nd, the 3rd terminal group TG1,
TG2、TG3.Here, processing unit 50 has from external device (ED) (such as foreign frequency control data life via the input of digital I/F portions 30
Into portion 200) data (such as frequency control data DFCI), carry out signal transacting.For example carry out temperature-compensating processing, aging school
It is positive to wait signal transacting.Oscillator signal generative circuit 140 uses frequency control data DFCQ and oscillator XTAL from processing unit 50,
Generate the oscillator signal OSCK by the frequency control data DFCQ frequencies of oscillation set.Clock signal generating circuit 160 is at least
With phase comparing section 161, generation makes the clock signal CK of the frequency after oscillator signal OSCK frequency of oscillation frequency multiplication.
Here, as shown in figure 5, set circuit arrangement with the 1st when SD1 intersects (vertical) as the 2nd while SD2, with the 1st while
SD1 it is relative while for the 3rd while SD3.In addition, set with the 2nd when SD2 is relative as the 4th side SD4.
In this case, the 1st terminal group TG1 of the connection in digital I/F portions 30 is configured at the 1st side along circuit arrangement
SD1 the 1st terminal area AT1.On the other hand, the 3rd terminal group TG3 of the connection of clock signal generating circuit 160 is configured at
Along the 2nd while SD2 the 2nd terminal area AT2, along the 3rd while SD3 the 3rd terminal area AT3, the 4th end along the 4th side SD4
Any one terminal area in subregion AT4.Specifically, in Figure 5, the 2nd terminal group of the connection of oscillating circuit 150
TG2 is configured at the 2nd terminal area AT2 along the 2nd side SD2, the 3rd terminal group of the connection of clock signal generating circuit 160
TG3 is configured at the 3rd terminal area AT3 along the 3rd side SD3.
In addition, as the collocation method of the terminal group in present embodiment etc., such as can be said in Fig. 6~Figure 10 described later
Implement various modifications as bright.For example the 2nd terminal group TG2 can be configured at the 3rd terminal area AT3, by the 3rd terminal group
TG3 is configured at the 2nd terminal area AT2.That is, the 2nd terminal group TG2 is configured at an end in the 2nd, the 3rd terminal area AT2, AT3
Subregion, the 3rd terminal group TG3 is configured at another terminal area in AT2, AT3.In addition, along the 4th side SD4's
The 4th terminal group TG4 is configured with 4th terminal area AT4.
Here, the 1st~the 4th side SD1~end edges of the SD4 equivalent to the IC of circuit arrangement.1st~the 4th terminal area AT1~
AT4 is disposed on the region of the Rack of the 1st~the 4th side SD1~SD4 inner side.1st~the 4th terminal area AT1~AT4
Long side direction be that, along the 1st~the 4th side SD1~SD4 direction, the Rack is the 1st~the 4th terminal area AT1~AT4
Short side direction on width.
1st~the 4th terminal area AT1~AT4 is known as the region of so-called I/O regions (outer peripheral areas), except end
Outside the pad groups such as subgroup TG1~TG4, I/O units can also be configured.I/O units are from the outside through by each terminal input signal
Input I/O units, by signal via each terminal be output to outside output I/O units, input and output dual-purpose input and output
I/O units etc..Terminal group TG1~TG4 each terminal and numeral I/F portions 30, oscillating circuit 150, clock signal generating circuit 160
It can connect, can also be connected not via I/O units via these I/O units etc. each circuit block.
In the present embodiment, as shown in figure 5, the terminal group TG1 in numeral I/F portions 30 is configured at along side SD1 end
Subregion AT1, on the other hand, the terminal group TG2 of oscillating circuit 150 is configured at along the terminal with the SD2 when SD1 intersects
Region AT2.Therefore, it is possible to make terminal group TG1 and TG2 distance i.e. L12 elongated, can effectively it suppress in digital I/F portions 30
The communication noise of generation is delivered to terminal group TG2.As a result, the oscillator signal that is added to caused by the communication noise can be reduced
OSCK phase noise.Because oscillator signal OSCK phase noise is lowered, therefore, clock signal CK phase noise also drops
It is low.
In addition, in the present embodiment, the terminal group TG1 in digital I/F portions 30 is configured at the terminal area along side SD1
AT1, on the other hand, the terminal group TG3 of clock signal generating circuit 160 are configured at along the end with the SD3 when SD1 is relative
Subregion AT3.Therefore, it is possible to make terminal group TG1 and TG3 distance i.e. L13 elongated, can effectively it suppress in digital I/F portions 30
The communication noise of middle generation is delivered to terminal group TG3.As a result, the clock letter that is added to caused by the communication noise can be reduced
Number CK phase noise.
Moreover, in the present embodiment, terminal group TG2 is configured at the terminal area AT2 along side SD2, and on the other hand, end
Subgroup TG3 is configured at along the terminal area AT3 with the SD3 when SD2 intersects.Thus, it is also possible to make terminal group TG2 and TG3
Distance be L23 elongated.Thus, for example, can suppress to produce in terminal group TG2 caused by oscillator signal OSCK etc. makes an uproar
Sound transmission is to terminal group TG3, and the noise that can also suppress to produce in terminal group TG3 caused by clock signal CK etc. is passed
It is delivered to terminal group TG2.
For example, as described above, the 1st grade of PLL circuit (frequency control data generating unit 40,200 and oscillator signal generation electricity
Road 140) it is different from the locking frequency of the 2nd grade of PLL circuit (clock signal generating circuit 160).Moreover, so, being locked when existing
When determining different 2 PLL circuits of frequency, signal noise is mutually transmitted, thus, the phase noise increase of superposition.
In this regard, in Figure 5, terminal group TG1, TG2, TG3 are configured at different terminal area AT1, AT2, AT3.That is, terminal
Group TG1, TG2, TG3 are configured at terminal area AT1, AT2, the AT3 being correspondingly arranged respectively from different 3 sides SD1, SD2, SD3.
Therefore, can not only make terminal group TG1 and TG2 apart from L12, terminal group TG1 and TG3 it is elongated apart from L13, additionally it is possible to make end
Subgroup TG2's and TG3 is elongated apart from L23.Therefore, the phase as caused by the communication noise in digital I/F portions 30 can not only be reduced
Noise, additionally it is possible to reduction phase noise as caused by the transmission of the signal noise between 2 PLL circuits.It is therefore, compared with the past,
Can provide can generate the clock signal CK after noise is decreased sufficiently, oscillator signal OSCK circuit arrangement.
For example, figure 4 illustrates the phase noise of the clock signal CK in the case of the method for applying present embodiment
Example., can be from low-frequency band according to present embodiment if by Fig. 3 G1, G2, G3 compared with Fig. 4 G4, understood
Reduce clock signal CK phase noise in the broadband of tremendously high frequency band.Therefore, it is possible to the clean clock signal for lacking noise
CK is supplied to each circuit (such as Figure 33 RF circuits 608) for the electronic equipment for being assembled with circuit arrangement.
In addition, in Figure 5, side SD1 is the short side of circuit arrangement, terminal group TG1 is configured at along the side SD1 as short side
Terminal area AT1.I.e., in Figure 5, side SD1, SD3 is the short side of circuit arrangement, while SD2, SD4 be circuit arrangement it is long while,
The terminal group TG1 of the connection in digital I/F portions 30 is configured at the terminal area AT1 along the side SD1 as short side.So, energy
Terminal group TG1 and other terminal groups are enough made to separate distance corresponding with long SD2, SD4 while i.e..For example, digital I/F portions can be made
The terminal group TG1 of the 30 connection and terminal group TG3 of the connection of clock signal generating circuit 160 is separated and long while i.e.
SD2, SD4 are corresponding apart from L13.Terminal is delivered to thereby, it is possible to the communication noise that effectively suppresses to produce in digital I/F portions 30
Group TG3.
In addition, in Figure 5, setting terminal group TG1 and terminal group TG2 distance as L12, terminal group TG1 and terminal group TG3
Distance be L13, terminal group TG2 and terminal group TG3 distance be L23 in the case of, at least one ratio in L12 and L13
L23 length.Specifically, in Figure 5, L13 ＞ L23, terminal group TG1 are longer apart from L13 with terminal group TG3, accordingly, it is capable to effectively
The communication noise for suppressing to produce in digital I/F portions 30 is delivered to terminal group TG3.In addition, in Figure 5, L12 ＞ L23, terminal group
TG1 is longer apart from L12 with terminal group TG2, accordingly, it is capable to effectively suppress the communication noise transmission produced in digital I/F portions 30
To terminal group TG2.As a result, can fully reduce caused by the communication noise in digital I/F portions 30 with clock signal CK,
The phase noise of oscillator signal OSCK superpositions.In addition, the distance of terminal group and terminal group can be set to for example each terminal group institute
Comprising multiple terminals in the mutual distance of centrally located terminal (the representational mutual distance of terminal).In addition, in Fig. 5
In, L13 and L12 both sides are longer than L23 longer than L23 but it is also possible to be one in only L13 and L12.
In addition, in the present embodiment, as illustrated in fig. 2, from foreign frequency control data generating unit 200
Frequency control data DFCI is input to processing unit 50 via terminal group TG1, numeral I/F portions 30, foreign frequency control data life
Compare into input signal (such as oscillator signal OSCK) of 200 pairs of the portion based on oscillator signal OSCK in itself with reference signal RFCK
Compared with.Moreover, oscillator signal generative circuit 140 comes from foreign frequency control data generating unit according to what is inputted via processing unit 50
200 frequency control data DFCQ generation oscillator signals OSCK.
In such manner, it is possible to foreign frequency control data generating unit 200 of the efficient, flexible with the outside for being arranged at circuit arrangement,
PLL circuit, generation oscillator signal OSCK are constituted together with internal oscillator signal generative circuit 140.For example, in circuit arrangement
In the case that outside system realizes foreign frequency control data generating unit 200 by microcomputer, controller, DSP etc.,
Can efficient, flexible constitute PLL circuit with its hardware assets, generation oscillator signal OSCK.
Moreover, in the case where so flexibly using foreign frequency control data generating unit 200, from foreign frequency control
The frequency control data DFCI of data generating section 200 is input to processing unit 50 via digital I/F portions 30.Accordingly, it is possible to by based on
The communication noise of frequency control data DFCI input causes to produce the larger phase noise shown in Fig. 3 G1, G2, G3.
In this regard, in the present embodiment, as shown in figure 5, by the way that terminal group TG1, TG2, TG3 to be configured to different terminals
Region AT1, AT2, AT3, can make TG1's and TG2 elongated apart from L13 apart from L12, TG1 and TG3.Therefore, as described above that
Sample, in the case of constituting PLL circuit, also can effectively press down in efficient, flexible with foreign frequency control data generating unit 200
Make the increase of the phase noise caused by frequency control data DFCI communication noise.
In addition, as shown in Fig. 2 the circuit arrangement of present embodiment have to the input signal based on oscillator signal OSCK with
The phase comparing section 41 (frequency control data generating unit 40) that reference signal RFCK phase is compared.The phase comparing section
What the 41st, the frequency control data generating unit 40 with phase comparing section 41 can for example be formed at Fig. 5 is configured with processing unit 50
The region of control logic.Such as by automatically configuring the control logic that wiring is formed as gate array, phase bit comparison can be realized
Portion 41, frequency control data generating unit 40.
Moreover, oscillator signal generative circuit 140 is under the 1st pattern, passed through according to from foreign frequency control data generating unit 200
The frequency control data DFCQ inputted by processing unit 50 generates oscillator signal.That is, 50 pairs of processing unit is from foreign frequency control data
The frequency control data DFCI that generating unit 200 is inputted is carried out after the signal transactings such as temperature-compensating processing, age correction, signal transacting
Frequency control data DFCQ be input into oscillator signal generative circuit 140, generation oscillator signal OSCK.
On the other hand, oscillator signal generative circuit 140 is under the 2nd pattern, according to (the FREQUENCY CONTROL number of slave phase bit comparison portion 41
According to generating unit 40) generate oscillator signal OSCK via the frequency control data DFCQ of the input of processing unit 50.That is, under the 2nd pattern,
50 couples of frequency control data DFCI based on the phase comparative result in the phase comparing section 41 inside circuit arrangement of processing unit enter
Frequency control data DFCQ after the signal transactings such as trip temperature compensation deals, age correction, signal transacting is input into vibration letter
Number generative circuit 140, generation oscillator signal OSCK.In addition, in processing unit 50, can be defeated from frequency control data generating unit 40
Enter and the frequency control data DFCI after processing is filtered by digital filtering portion 44.Or processing unit 50 can input phase ratio
Processing is filtered compared with the phase comparative result in portion 41, and to phase comparative result.
So, in the case where outside system has foreign frequency control data generating unit 200, by the work of circuit arrangement
Operation mode is set as the 1st pattern, can efficient, flexible constituted with the foreign frequency control data generating unit 200 of external system
PLL circuit, generation oscillator signal OSCK.
On the other hand, in the case where outside system does not have foreign frequency control data generating unit 200, circuit is filled
The Working mode set put is the 2nd pattern, can be by (the FREQUENCY CONTROL of phase comparing section 41 of the inside for being arranged at circuit arrangement
Data generating section 40) constitute PLL circuit, generation oscillator signal OSCK.
There is foreign frequency control data generating unit 200 and do not have therefore, it is possible to the system of tackling outside
The situation both of these case of foreign frequency control data generating unit 200, realizes raising of convenience etc..
In addition, in the present embodiment, as digital I/F portions 30, can use and include serial data line and serial clock
The serial interface circuit of 2 lines of line, 3 lines or 4 lines.So, as digital I/F portions 30, gone here and there such as can use I2C, SPI
Line interface circuit.Therefore, there is the serial interface circuits such as I2C, SPI in external device (ED)s such as microcomputer, controllers
Under, the serial line interface processing based on I2C, SPI is carried out between the external device (ED), external device (ED) (foreign frequency can will be come from
Control data generating unit 200) data (frequency control data) be input to processing unit 50.
In addition, in Figure 5, if from the 1st when SD1 is towards the 3rd the direction on SD3 side be the 1st direction DR1, the 1st direction
DR1 opposite direction is the 2nd direction DR2.Intersect the direction of (vertical) with the 1st direction DR1 as the 3rd direction DR3, the 3rd in addition, setting
Direction DR3 opposite direction is the 4th direction DR4.In this case, in the circuit arrangement of present embodiment, as shown in figure 5,
Processing unit 50 is configured at the 1st terminal group TG1 (the 1st terminal area AT1) the 1st direction DR1 sides.For example in the 1st terminal group TG1
The 1st direction DR1 sides configuration numeral I/F portions 30 of (the 1st terminal area AT1), are configured in the 1st direction DR1 sides in digital I/F portions 30
Processing unit 50 is configured.
In such manner, it is possible to by frequency control data from external device (ED) inputted using the 1st terminal group TG1 terminal etc.
Data are input to processing unit 50 via digital I/F portions 30 with the signal path of short path.Thereby, it is possible to will such as FREQUENCY CONTROL number
According to etc. data communication noise generating source position restriction in the 1st terminal group TG1 position, the 2nd direction DR2 of processing unit 50
The vicinity of the position of side.Therefore, it is possible to make the generating source and the 2nd terminal group TG2, the 3rd terminal group TG3 distance of the communication noise
(L12, L13) is elongated, can reduce the phase noise produced using communication noise as reason.
In addition, in Figure 5, the 2nd terminal group TG2 is configured at the 2nd terminal area AT2, the 3rd terminal group TG3 is configured at the 3rd end
Subregion AT3, clock signal generating circuit 160 is configured at the 3rd terminal group TG3 (the 3rd terminal area AT3) the 2nd direction DR2
Side.Such as the 3rd terminal group TG3 is not adjacent to clock signal generating circuit 160 across other circuit blocks (circuit element).
In such manner, it is possible to by output signal (such as clock signal CK, FREQUENCY CONTROL from clock signal generating circuit 160
Voltage signal) the 3rd terminal group TG3 terminal is output to the signal path of short path from clock signal generating circuit 160.This
Outside, can will be defeated to the input signal of the terminal of the 3rd terminal group from the 3rd terminal group TG3 terminal with the signal path of short path
Enter to clock signal generating circuit 160.Thereby, it is possible to by signal (the clock signal CK based on clock signal generating circuit 160
Deng) clocking noise generating source position restriction in the 3rd terminal group TG3 position, clock signal generating circuit 160 the 1st
The vicinity of the position of direction DR1 sides.Therefore, it is possible to make the generating source of the clocking noise and the 2nd terminal group TG2 distance (L23)
It is elongated, the phase noise produced using clocking noise as reason can be reduced.
In addition, in Figure 5, processing unit 50 is configured between the 1st terminal area AT1 and clock signal generating circuit 160.Example
Processing unit 50 such as is configured in the 1st terminal area AT1 the 1st direction DR1 sides, in the 1st direction DR1 sides configurable clock generator of processing unit 50
Signal generating circuit 160.Moreover, configuring the 3rd terminal area AT3 in the 1st direction DR1 sides of clock signal generating circuit 160.
So, between the 1st terminal area AT1 the 1st terminal group TG1 and the 3rd terminal area AT3 the 3rd terminal group TG3
Across processing unit 50 and clock signal generating circuit 160.Therefore, as between the 1st terminal group TG1 and the 3rd terminal group TG3
Apart from L13, distance corresponding with the width of width and clock signal generating circuit 160 of processing unit 50 is at least able to ensure that.That is,
As apart from L13, the width pair on the 1st direction DR1 with processing unit 50 and clock signal generating circuit 160 is at least able to ensure that
The distance answered.Therefore, it is possible to make the 1st terminal group TG1 and the 3rd terminal group TG3 elongated apart from L13, it can reduce with digital I/F
The phase noise that communication noise in portion 30 produces for reason.
In addition, in Figure 5, oscillating circuit 150 is configured between processing unit 50 and clock signal generating circuit 160.For example,
Oscillating circuit 150 is configured in the 1st direction DR1 sides of processing unit 50, in the 1st direction DR1 sides configurable clock generator letter of oscillating circuit 150
Number generative circuit 160.In addition, configuring such as generation reference voltage and benchmark electricity between processing unit 50 and oscillating circuit 150
The reference signal generative circuit 180 of stream.In addition, configuring temperature sensor 10, A/D between processing unit 50 and oscillating circuit 150
Converter section 20.
So, between the 1st terminal area AT1 the 1st terminal group TG1 and the 3rd terminal area AT3 the 3rd terminal group TG3
Across processing unit 50, oscillating circuit 150 and clock signal generating circuit 160.Therefore, as the 1st terminal group TG1 and the 3rd end
The distance between subgroup TG3 L13, is at least able to ensure that the width, the width of oscillating circuit 150, clock signal with processing unit 50
The corresponding distance of width of generative circuit 160.Therefore, it is possible to further make the 1st terminal group TG1 and the 3rd terminal group TG3 distance
L13 is elongated, can further reduce the phase noise produced using the communication noise in digital I/F portions 30 as reason.
In addition, in Figure 5, oscillating circuit 150 is configured at the 2nd terminal group TG2 the 3rd direction DR3 sides.Such as oscillating circuit
150 are not adjacent to the 2nd terminal group TG2 across other circuit blocks (circuit element).
In such manner, it is possible to which oscillating circuit 150 is connected with the 2nd terminal group TG2 terminal with the signal path of short path.By
This, for example, can shorten the length of oscillator signal OSCK signal wire, can reduce and be posted in oscillator signal OSCK signal wire
Raw parasitic capacitance.Therefore, it is possible to suppress following situation：The communication noise warp of the 1st terminal group TG1 from digital I/F portions 30
Oscillator signal OSCK signal wire is delivered to by parasitic capacitance, and increases oscillator signal OSCK phase noise.In addition, also can
Enough suppress following situation：The clocking noise of the 3rd terminal group TG3 from clock signal generating circuit 160 is passed via parasitic capacitance
Oscillator signal OSCK signal wire is delivered to, and increases oscillator signal OSCK phase noise.
In addition, in the present embodiment, as oscillator XTAL, the oscillator of the constant temperature groove profile with thermostat can be used.
In this case, in Figure 5, the 4th terminal group TG4 configurations of the thermostat control terminal of the oscillator XTAL comprising constant temperature groove profile
In the 4th terminal area AT4 along the 4th side SD4.For example, the connection of the lead-out terminal, temperature sensor of heater control voltage
The thermostat control terminal such as terminal is configured at the 4th terminal area AT4 as the 4th terminal group TG4.
So, used in digital I/F portions 30, oscillating circuit 150 is used, the 1st of clock signal generating circuit 160 the, the 2nd, the 3rd
Terminal group TG1, TG2, TG3 are respectively arranged at the 1st, the 2nd, in the case of the 3rd terminal area AT1, AT2, AT3, can be effectively sharp
With remaining 4th terminal area AT4, configuration includes the 4th terminal group TG4 of thermostat control terminal.I.e. by the 1st,
2nd, the 3rd terminal area AT1, AT2, AT3 configurations the 1st, the 2nd, the 3rd terminal group TG1, TG2, TG3, phase can be reduced as described above
Position noise, and by configuring the 4th terminal group TG4 for including thermostat control terminal in remaining 4th terminal area AT4,
The oscillator XTAL of constant temperature groove profile thermostat control can be realized.
Moreover, the circuit arrangement of present embodiment, which is included, is connected with the 4th terminal group TG4 thermostat control terminal simultaneously
And carry out the thermostat control circuit 190 of the oscillator XTAL of constant temperature groove profile thermostat control.And in Figure 5, the thermostat
Control circuit 190 is configured at the 4th terminal area AT4 the 4th direction DR4 sides.
In such manner, it is possible to signal path connection thermostat control circuit 190 and the 4th terminal group TG4 of short path constant temperature
Groove control terminal, can realize more appropriate thermostat control.For example, as thermostat control terminal, setting heater
The lead-out terminal of control voltage, the connection terminal of temperature sensor.In this case, thermostat control circuit 190 is configured at the 4th
Terminal area AT4 the 4th direction DR4 sides, thereby, it is possible to shorten connection thermostat control circuit 190 and heater control voltage
The signal routing of lead-out terminal, the signal routing of the connection terminal of connection thermostat control circuit 190 and temperature sensor
Length.Dead resistance therefore, it is possible to reduce these signal routings etc., so the dead resistance etc. can be reduced to thermostat control
The harmful effect brought is made, more appropriate thermostat control can be realized.
In addition, in Figure 5, oscillating circuit 150 is configured between thermostat control circuit 190 and the 2nd terminal area AT2.
For example in the 4th terminal area AT4 the 4th direction DR4 sides configuration thermostat control circuit 190, circuit 190 is controlled in thermostat
4th direction DR4 sides configures oscillating circuit 150, and the 2nd terminal area AT2 is set in the 4th direction DR4 sides of oscillating circuit 150.
Thereby, it is possible to efficient, flexible with the region between the 4th terminal area AT4 and the 2nd terminal area AT2, to constant temperature
Groove controls circuit 190 to be laid out configuration with oscillating circuit 150.Therefore, it is possible to short path connection thermostat control circuit 190
With the 4th terminal group TG4, and oscillating circuit 150 is being connected and while the 2nd terminal group TG2 with short path, in the 4th terminal region
In region between domain AT4 and the 2nd terminal area AT2, efficiently layout configuration thermostat controls circuit 190 and oscillating circuit
150.Therefore, it is possible to take into account realize the reduction of phase noise and the downsizing of the layout area of circuit arrangement.
In addition, in the present embodiment, processing unit 50 (processor) carries out handling estimation frequency control by Kalman filtering
The processing of data DFCI processed true value, and according to the true value estimated, carry out frequency control data DFCI age correction.
So, if handling estimation frequency control data DFCI true value by Kalman filtering, and according to estimating
True value carries out age correction, then can greatly improve the precision of age correction.That is, it can realize and consider observation noise, system
The age correction of the influence of noise.
More specifically, processing unit 50 preserves the detection moment with keeping pattern in the case where detecting holding pattern
True value at the time of correspondence.The detection moment of pattern can be to maintain at the time of preserving the true value in itself or the moment
At the time of before etc..Moreover, processing unit 50 is aging after correction by carrying out the calculation process based on the true value preserved, generation
Frequency control data DFCQ.The frequency control data DFCQ of generation is output to oscillator signal generative circuit 140.The aging school
The generation processing of frequency control data DFCQ after just is performed by age correction portion 56.
For example during usual action, 50 pairs of frequency controls based on the phase comparative result in phase comparing section 41 of processing unit
Data DFCI processed or the frequency control data DFCI inputted from foreign frequency control data generating unit 200 carry out such as temperature and mended
The signal transactings such as processing are repaid, the frequency control data DFCQ after signal transacting is output to oscillator signal generative circuit 140.Vibration
Signal generating circuit 140 generates oscillator signal OSCK using frequency control data DFCQ and oscillator XTAL from processing unit 50,
And it is output to frequency control data generating unit 40 (phase comparing section 41) or foreign frequency control data generating unit 200.Thus,
Form by frequency control data generating unit 40 (phase comparing section 41) or foreign frequency control data generating unit 200 and vibration
The loop for the PLL circuit that signal generating circuit 140 is constituted, can be generated and the phase locked accurate vibrations of reference signal RFCK
Signal.
And in the present embodiment, interior during the usual action before detecting holding pattern, processing unit 50
Kalman filtering portion 54 also acted, to frequency control data DFCI perform Kalman filtering processing.
That is, it is handled as follows：Estimation is handled for frequency control data DFCI observation by Kalman filtering
True value.
When detecting holding pattern, true value at the time of will be corresponding with the detection moment for keeping pattern is saved in processing unit
In 50.Specifically, age correction portion 56 preserves the true value.Moreover, age correction portion 56 is true based on what is preserved by carrying out
Frequency control data DFCQ after the calculation process of value, generation age correction.
So, due to carrying out age correction according to true value of the detection moment with keeping pattern at the time of corresponding, accordingly, it is capable to
Enough increase substantially the precision of age correction.That is, the aging school for the influence for considering observation noise and system noise can be realized
Just.
In addition, processing unit 50 (is compensated and led by aging by the calculation process carried out to the true value preserved plus corrected value
The calculation process of the frequency change of cause), generate the frequency control data DFCQ after age correction.For example by each defined
Corrected value corresponding with rate of ageing (gradient of aging, aging coefficient) (is eliminated the frequency caused by rate of ageing by the moment successively
Rate change corrected value) and with keep pattern detection the moment it is corresponding at the time of true value be added, generate age correction after frequency
Rate control data DFCQ.In addition, the addition processing of present embodiment is subtraction process comprising the processing plus negative value.
It is AC (k) that time step k corrected value, which is for example set, as the frequency control data after D (k), time step k age correction.
In this case, processing unit 50 obtains the FREQUENCY CONTROL after time step k+1 age correction by AC (k+1)=AC (k)+D (k)
Data AC (k+1).Processing unit 50 carries out the corrected value D (k) of each such time step addition processing, until from the pattern of holding
Untill (moment being released at the time of recovery).
In addition, processing unit 50 true value is added the calculation process of the corrected value after filtering process.For example, to corrected value
D (k) carries out the filtering process such as low-pass filtering treatment, true value is added successively the fortune of the corrected value D ' (k) after filtering process
Calculation is handled.Specifically, AC (k+1)=AC (k)+D ' (k) calculation process is carried out.
In addition, processing unit 50 handled according to Kalman filtering in observation residual error, obtain corrected value.For example, processing unit 50
During before detecting holding pattern, the processing of the corrected value according to observation residual error estimation age correction is carried out.For example exist
If observing residual error in the case of ek, by carrying out D (k)=D (k-1)+Eek processing, to estimate corrected value D (k).Here E
E.g. constant, but it is also possible to substitute constant E, and use kalman gain.Moreover, preserving the detection moment pair with keeping pattern
Corrected value at the time of answering, the calculation process that the corrected value for being about to preserve of going forward side by side is added with true value, is thus generated after age correction
Frequency control data DFCQ.
In addition, as the collocation method of the terminal group in present embodiment etc., can implement for example shown in Fig. 6~Figure 10
Various modifications.For example in figure 6, terminal group TG1 is configured at the terminal area AT1 along side SD1, on the other hand, terminal group TG3
It is configured at the terminal area AT4 along side SD4.In addition, terminal group TG2 is configured at the terminal area AT2 along side SD2.In addition,
Terminal group TG3 can also be dispersedly configured in terminal area AT4 and terminal area AT3 (being configured in both sides).Terminal group TG2
Similarly can dispersedly it configure in terminal area AT2 and terminal area AT3.In addition, as shown in fig. 6, expect terminal group TG2,
TG3 be configured at compared to while SD1 closer to while SD3 side.Thereby, it is possible to make terminal group TG1 and terminal group TG2, TG3 distance
It is more separated.
In the figure 7, with Fig. 6 on the contrary, terminal group TG3 is configured at terminal area AT2, terminal group TG2 is configured at terminal region
Domain AT4.In other words, in Fig. 5 etc., during vertical view from the direction intersected from the substrate (semiconductor substrate) with circuit arrangement
When vertical view () from the forming region side of transistor, side SD2 is the right, and side SD4 is the left side but it is also possible to be side SD2 is
The left side, side SD4 is the right.Similarly, side SD1, SD3 be not necessarily top, it is following.
In fig. 8, terminal group TG1, TG2 is configured at terminal area AT1, and terminal group TG3 is configured at terminal area AT3.That is,
Terminal group TG2 can also be configured at the terminal area beyond terminal area AT2.In addition, in this case, terminal group TG3 also may be used
To be configured at terminal area AT2 or terminal area AT4.
In Fig. 9, Tu10Zhong, terminal group TG1 is configured at terminal area AT1, on the other hand, terminal group TG2 and terminal group
TG3 is configured at terminal area AT2.Moreover, in fig .9, terminal group TG3 is configured at than terminal group TG2 further from terminal group TG1's
Region.In addition, in Fig. 10, terminal group TG2 is configured at than terminal group TG3 further from terminal group TG1 region.Furthermore it is possible to
Terminal group TG2 and terminal group TG3 are configured at terminal area AT4 or terminal area AT3.
As described above, in the present embodiment, the terminal group TG1 of the connection in digital I/F portions 30 is configured at terminal area
AT1, on the other hand, the terminal group TG3 of the connection of clock signal generating circuit 160 is configured at terminal area AT2, AT3, AT4
In any one terminal area.In addition, the terminal group TG2 of the connection of oscillating circuit 150 is configured at and is configured with and for example holds
Subgroup TG1, terminal group the TG3 different terminal area of terminal area.In addition, can also implement terminal as Fig. 9, Figure 10
Group TG2, TG3 are configured at the deformation in same terminal region.
4. clock signal generating circuit
Figure 11 illustrates the 1st configuration example of clock signal generating circuit 160.Figure 11 clock signal generating circuit 160
Include phase comparing section 161, charge pump circuit 162, filtering part 163, frequency divider 165,166, output buffer 168.In addition,
In fig. 11, the outer of circuit arrangement is arranged at by oscillator signal generative circuit 164 and oscillator XTAL2 the oscillator VCXO constituted
Portion.That is, using as exterior member and set oscillator VCXO formation PLL circuit loop.However, it is also possible to implement to shake
Swing the deformation that signal generating circuit 164 etc. is arranged at the inside of circuit arrangement.
The clock signal CKS generated by the oscillator signal generative circuit 164 of clock signal generating circuit 160 is input into point
Frequency device 165.And frequency divider 165 exports and CKS frequency is set to the clock signal CKN after 1/N.In addition, shaking by Fig. 1, Fig. 2
The oscillator signal OSCK for swinging the generation of signal generating circuit 140 is input to frequency divider 166 as reference signal.Moreover, frequency divider
OSCK frequency is set to the clock signal CKM after 1/M by 166 outputs.Phase comparing section 161 enters row clock signal CKN's and CKM
Phase bit comparison, exports the up/down pulse signal as phase comparative result.Charge pump circuit 162 changes up/down pulse signal
For up/down current signal, and it is output to filtering part 163.Up/down current signal is converted to DC voltage by filtering part 163, and is made
Oscillator signal generative circuit 164 is output to for vibrational control voltage.The generation of oscillator signal generative circuit 164 is controlled by the vibration
The clock signal CKS of the frequency of voltage setting processed.Clock signal CKS is output buffer circuit 168 and buffered, and is used as clock signal
CK and be output to outside via lead-out terminal TCK.In this case, the clock division based on frequency divider 169 is carried out.In addition, defeated
It is the terminal included in Fig. 5 terminal group TG3 to go out terminal TCK.
So, clock signal generating circuit 160 generate the frequency after the frequency of oscillation frequency multiplication by oscillator signal OSCK when
Clock signal CK.In this case frequency is set by the frequency dividing ratio of frequency divider 165,166,169.
Figure 12 is the 2nd configuration example of clock signal generating circuit 160.The clock signal generating circuit 160 of 2nd configuration example leads to
The PLL circuit of direct digital synthesiser mode is crossed to realize.
Phase comparing section 380 (comparing and computing unit) carries out the oscillator signal OSCK and clock signal CKS as reference signal
Phase bit comparison (comparison operation).Digital filtering portion 382 carries out the smoothing techniques of phase error.The knot of phase comparing section 380
The phase comparing section 41 of structure, action and Fig. 2 is same, can include counter, TDC (time-to-digit converter).Digital filtering portion
The 382 digital filtering portion 44 equivalent to Fig. 2.Numerical Control type oscillator 384 is to use to shake from the benchmark with oscillator XTAL2
The reference oscillator signal of device 386 is swung, the circuit of digit synthesis is carried out to arbitrary frequency, waveform.I.e., the root as VCO it is not
Frequency of oscillation is controlled according to the control voltage from D/A converter, but uses the frequency control data and reference oscillator of numeral
386 (oscillator XTAL2), the clock signal CKS for generating arbitrary frequency of oscillation is handled by digital operation.Clock signal CKS quilts
Output buffer 168 is buffered, and is output to outside via lead-out terminal TCK as clock signal CK.Pass through Figure 12 knot
Structure, can realize the ADPLL circuits of direct digital synthesiser mode.
In addition, clock signal generating circuit 160 can not include the whole circuit elements for being used for generating clock signal.Example
Such as, it would however also be possible to employ following structure：The circuit for constituting a part by the discrete part for the outside for being arranged at circuit arrangement 500 will
Element, and be connected via the 3rd terminal group TG3 with clock signal generating circuit 160.
5. temperature sensor, oscillating circuit
Figure 13 shows the configuration example of temperature sensor 10.Figure 13 temperature sensor 10 has current source IST and current collection
Pole is provided to the bipolar transistor TRT from current source IST electric current.Bipolar transistor TRT turns into its colelctor electrode and base stage quilt
The diode connection of connection, temperature detection voltage of the node output with temperature characterisitic of bidirectional bipolar transistor TRT colelctor electrode
VTDI.Temperature detection voltage VTDI temperature characterisitic be due to bipolar transistor TRT emitter-to-base voltage temperature according to
Rely property and produce.The temperature detection voltage VTDI of the temperature sensor 10 for example (has negative ladder with negative temperature characterisitic
1 temperature characterisitic of degree).
Figure 14 shows the configuration example of oscillating circuit 150.The oscillating circuit 150 have current source IBX, bipolar transistor TRX,
Resistance RX, variable capacitance capacitor CX1, capacitor CX2, CX3.
Current source IBX bidirectional bipolar transistors TRX colelctor electrode provides bias current.Resistance RX is arranged at bipolar transistor
Between TRX colelctor electrode and base stage.
The variable capacitance capacitor CX1 of variable capacitance one end is connected with oscillator XTAL one end.Specifically, it is variable
Capacitive battery container CX1 one end is connected to oscillator XTAL via the 1st oscillator terminal (oscillator pad) of circuit arrangement
One end.Capacitor CX2 one end is connected with the oscillator XTAL other end.Specifically, capacitor CX2 one end is via circuit
The 2nd oscillator terminal (oscillator pad) of device and the other end for being connected to oscillator XTAL.Capacitor CX3 one end and oscillator
XTAL one end connection, the other end is connected with bipolar transistor TRX colelctor electrode.These the 1st, the 2nd oscillators are in Fig. 5 with terminal
The 2nd terminal group TG2 in the terminal that includes.
The base emitter interpolar electric current that oscillator XTAL vibration is flowed through in bipolar transistor TRX and is produced.Also,
When base emitter interpolar electric current increases, bipolar transistor TRX colelctor electrode-transmitting electrode current increase, from current source IBX
Reduce to the bias current of resistance RX branches, therefore, collector voltage VCX reductions.On the other hand, when bipolar transistor TRX's
When base emitter interpolar electric current reduces, colelctor electrode-transmitting electrode current reduces, from current source IBX to the biasing of resistance RX branches
Electric current increases, therefore, and collector voltage VCX rises.Collector voltage VCX feeds back to oscillator XTAL via capacitor CX3.
Oscillator XTAL frequency of oscillation has temperature characterisitic, the output voltage VQ that the temperature characterisitic passes through D/A converter sections 80
(frequency control voltage) is compensated.That is, output voltage VQ is input into variable capacitance capacitor CX1, and utilizes output
Voltage VQ is controlled to variable capacitance capacitor CX1 capacitance.Occur in variable capacitance capacitor CX1 capacitance
During change, the resonant frequency of oscillating loop can change, therefore the oscillator XTAL change of frequency of oscillation that causes of temperature characterisitic
It is dynamic to be compensated.Variable capacitance capacitor CX1 can be by such as varicap (varactor：Varactor) etc. it is real
It is existing.
In addition, the oscillating circuit 150 of present embodiment is not limited to Figure 14 structure, various modifications can be implemented.For example in figure
It is illustrated in 14 in case of CX1 is variable capacitance capacitor, but it is also possible to which CX2 or CX3 are set into profit
The variable capacitance capacitor controlled with output voltage VQ.In addition it is also possible to which multiple in CX1~CX3 are set to utilize VQ controls
The variable capacitance capacitor of system.
In addition, oscillating circuit 150 can not include the whole circuit elements for being used for vibrating oscillator XTAL.For example, also may be used
To use following structure：The circuit element of a part is made up of the discrete part for the outside for being arranged at circuit arrangement 500, and is passed through
It is connected by the 2nd terminal group TG2 with oscillating circuit 150.
6. numeral I/F portions, reference signal generative circuit, thermostat control circuit
Figure 15 shows the 1st configuration example in digital I/F portions 30.The string for the I2C modes that Figure 15 digital I/F portions 30 pass through 2 lines
Line interface circuit is realized, includes I2C control circuits 35 and buffer circuit 36.R1, R2 are pull-up resistors.I2C modes are to pass through
This 2 signal wires of serial time clock line SCL and two-way serial data line SDA are come the serial communication side of synchronous mode that is communicated
Formula.Can connect multiple from device in I2C bus, main device specify be individually determined from the address of device select from
After device, communicated with this from device.
Figure 16 shows the 2nd configuration example in digital I/F portions 30.The SPI side that Figure 16 digital I/F portions 30 pass through 3 lines or 4 lines
The serial interface circuit of formula is realized, includes SPI control circuit 37 and buffer circuit 38.R3, R4, R5 are pull-up resistors.SPI side
Formula is the serial communication side by serial time clock line SCK and unidirectional 2 serial data lines SDI, SDO synchronous mode communicated
Formula.It can connect multiple from device in SPI bus, and in order to be determined to them, main device is needed to use from device
Selection line is selected from device, in this case, it is necessary to from device selection line.
Figure 17 shows the configuration example of reference signal generative circuit 180.The reference signal generative circuit 180 includes bandgap reference
Circuit 182, reference voltage generating circuit 184, reference current generating circuit 186.Bandgap reference circuit 182 includes operational amplifier
OPA1, bipolar transistor BA1, BA2, transistor TA1, resistance RA1, RA2, RA3, generate the constant pressure as band gap reference voltage
VBG.Bipolar transistor BA1, BA2 are the diode connections for connecting collector and emitter.Bandgap reference circuit 182 uses this
A little bipolar transistor BA1, BA2 eliminate the temperature dependency of band gap voltage, generate the constant pressure constant relative to temperature change
VBG。
Reference voltage generating circuit 184 includes operational amplifier OPA2, transistor TA2, resistance RA4, RA5.Moreover, generation
It is used as VRF=VBG × { (RA4+RA5)/RA5 } reference voltage V RF.Reference current generating circuit 186 includes operational amplifier
OPA3, transistor TA3, TA4, resistance RA6, RA7.Moreover, generating constant current IRF according to constant pressure VBG.
Figure 18 shows that thermostat controls the configuration example of circuit 190.Thermostat control circuit 190 comprising operational amplifier OPB,
Resistance RB1~RB6.RB1~RB5 is that its resistance value is controlled as variable resistance.
Temperature sensor 193 is the temperature sensor of thermostat control, is disposed on the temperature sensor in oscillator
(the 460 of Figure 32 described later or 462).In figure 18, temperature sensor 193 is realized by thermistor.
Temperature sensor 193 is connected via connection terminal TCTS with thermostat control circuit 190.Connection terminal TCTS is bag
It is contained in the terminal in Fig. 5 the 4th terminal group TG4.
By being split by the resistance of resistance RB1, RB2 supply voltage carried out, the voltage of thermostat temperature setting is generated
VB1.Moreover, according to the thermostat temperature of oscillator, being used as the resistance change of the thermistor of temperature sensor 193, voltage
VB2 changes.Operational amplifier OPB is acted so that the voltage VB1 of voltage VB2 and thermostat temperature setting is by virtually connecing
Ground and as identical voltage, and generate heater control voltage VBQ.
The heater control voltage VBQ for controlling circuit 190 to generate by thermostat is output to via lead-out terminal TVBQ to be set
The heater 191 (450, the 452 of Figure 32) being placed in oscillator.Lead-out terminal TVBQ is contained within Fig. 5 the 4th terminal group TG4
In terminal.Heater 191 includes the heating power bipolar transistor 192 as heater element.Pass through heater control voltage
Base voltage of VBQ control heating powers bipolar transistor 192 etc., realizes the heating control of heater 191.
In addition, thermostat control circuit 190 is not limited to Figure 18 structure.For example can also be by heater as following
As the control circuit for heater 190 of the circuit structure of heater control object, the heater is configured to use diode conduct
Temperature sensor, and heating heater MOS transistor is set as heater element.
7. frequency of oscillation changes caused by aging
In the oscillators such as OCXO, TCXO, due to being referred to as changing with time for aging, frequency of oscillation changes.Moreover,
In the characteristic that the aging of frequency of oscillation between the individual of oscillator changes, exist by constituting the performance of the part of oscillator, part
With caused by the individual deviation (hereinafter referred to as component deviation) of the installment state of oscillator or the use environment of oscillator etc.
Difference.
Figure 19 A1~A5 is the measurement knot of the aging characteristics of the multiple oscillators identical or different on shipment lot number
One of fruit.As shown in Figure 19 A1~A5, there is the difference along with component deviation in the mode that aging changes.
Be considered as the dust that is produced in hermetic container the reason for the variation of frequency of oscillation caused by from aging to
Oscillator come off and adhere to, the environmental change based on some emergent gas or the bonding agent that uses in an oscillator at any time
Between change.
As the countermeasure for suppressing such variation of frequency of oscillation caused by aging, there is following method：Going out
It is initial aged during implementing to make oscillator operation certain before goods, make shipment again after frequency of oscillation initial shifts.But, for
It is required that the purposes of high frequency stability, it is inadequate only to take such initial aged countermeasure, and expected compensation is caused by aging
Frequency of oscillation variation age correction.
In addition, in the case where oscillator is used as into the reference signal source of base station, there is so-called holding pattern
Problem.For example in a base station, by using PLL circuit by the oscillator signal (output signal) of oscillator and from GPS or network
Reference signal it is synchronous, suppress frequency variation.But, disappear when reference signal of the generation from GPS or network (internet) turns into
During the holding pattern of mistake or exception, it is impossible to obtain for synchronous reference signal.
When producing such holding pattern, the oscillator signal produced by the self-oscillation of oscillator turns into the base of base station
Calibration signal source.It is therefore desirable to following holding mode performance：The moment is being produced to from keeping pattern recovery from the pattern of holding
During holding pattern untill moment (releasing the moment), suppress the variation of the frequency of oscillation caused by the self-oscillation of oscillator.
But, as described above, because there is the degree that can not ignore caused by aging in the frequency of oscillation of oscillator
Change, therefore, because this and presence can not realize the problem of high holding mode performance.The pattern phase is kept such as at 24 hours
In, in the case where defining the frequency departure (Δ f/f) allowed, if there is caused by aging frequency of oscillation it is larger
Change, then can not meet the regulation of the tolerance frequency deviation.
For example as base station and the communication mode of communication terminal, it is proposed that FDD (Frequency Division Duplex：
FDD), TDD (Time Division Duplex：Time division duplex) etc. various modes.Moreover, in TDD modes, it is up
With descending use identical frequency according to time division way transceiving data, when being set with protection between distributing to the time slot of each equipment
Between.Therefore, in order to realize appropriate communication, it is necessary to carry out timing synchronization in each equipment, it is desirable to there is accurately absolute moment
Timing.
Figure 20 B1 represent to generate holding pattern in the case of preferable frequency of oscillation aging characteristic.The opposing party
Face, B2 (dotted line) represents the characteristic for causing frequency of oscillation to change due to aging.B3 is the change of the frequency of oscillation caused by aging
Dynamic amplitude.In addition, Figure 21 B4, which represents to generate, is used for the FREQUENCY CONTROL electricity close to B1 characteristic in the case of holding pattern
The passage of pressure.On the other hand, FREQUENCY CONTROL electricity B5 (dotted line) is represented at the time of generating reference signal and disappearing or be abnormal
Press as constant state.
In order to enter to exercise the correction that preferable characteristic shown in characteristic and B1 shown in Figure 20 B2 is close, aging school is carried out
Just.If for example, by age correction, and changing frequency control voltage as shown in Figure 21 B4, then it can enter to exercise
The correction of preferable characteristic shown in characteristic close to B1 shown in Figure 20 B2, if for example, improve correction accuracy, can be by
Characteristic correction shown in B2 is the preferable characteristic shown in B1.On the other hand, aging is not carried out shown in the B5 such as Figure 21
In the case of correction, as shown in Figure 20 B2, during holding pattern, frequency of oscillation changes, if for example, to keeping mould
The requirement specification of formula performance is the B1 shown in Figure 20, then can not meet the requirement.
The holding mould of the offset (total amount) of the time of such as variation based on frequency of oscillation during expression holding pattern
Formula time θtotIt can be represented as following formula (1).
Here, T1Represent the elapsed time of the aging caused by holding pattern.f0It is nominal oscillation frequency, Δ f/f0It is frequency
Rate deviation.In above formula (1), T1×f0Total clock number is represented, (Δ f/f0)×(1/f0) represent 1 clock at the time of skew
Amount.Moreover, frequency deviation f/f0Holding mode time θ can be usedtotWith elapsed time T1, represented as above formula (2).
Here, suppose that frequency deviation f/f0Relative to the elapsed time in 1 function with constant slope variation.At this
In the case of, with elapsed time T1It is elongated, keep mode time θtotIn 2 functions it is elongated.
For example, in the case of TDD modes, in order to prevent from setting the Time Slot Overlap of guard time, it is desirable to keep pattern
Time is such as θtotThe μ s of ＜ 1.5.Therefore, from above formula (2), the frequency deviation f/f allowed as oscillator0, it is desirable to
Very small value.Especially, elapsed time T1It is longer, the smaller value of the tolerance frequency deviation requirement.For example, as from holding
From the generation moment of pattern, to using time of the upkeep operation untill at the time of keeping pattern recovery exemplified by time for assuming
Such as T1In the case of=24 is small, tolerance frequency deviation is used as, it is desirable to very small value.It is additionally, since in frequency deviation f/f0
In the frequency departure comprising such as temperature-independent and the frequency departure caused by aging, therefore, in order to meet above-mentioned requirements, it is necessary to
Very high-precision age correction.
8. the age correction for having used Kalman filtering to handle
In the present embodiment, the burn-in correction method handled using Kalman filtering is employed.Specifically, in this reality
Apply in mode, during before detecting holding pattern, estimation is handled by Kalman filtering and (shaken for frequency control data
Swing frequency) observation true value.Moreover, in the case where detecting holding pattern, preserve and detect holding pattern when
The true value at (time point) at the time of carving correspondence, and the calculation process based on the true value preserved is carried out, hereby it is achieved that aging school
Just.
Figure 22 is the figure for the measurement result example for showing the variation of frequency of oscillation caused by aging.Transverse axis is the elapsed time
(ageing time), the longitudinal axis is frequency departure (the Δ f/f of frequency of oscillation0).As shown in Figure 22 C1, in the measurement as observation
There is deviation big as caused by system noise, observation noise in value.Also included as caused by environment temperature partially in the deviation
Difference.
When so existing in the measurement under the situation of big deviation, in order to correctly obtain true value, in present embodiment
In, handled based on Kalman filtering the state estimation of (such as linear Kalman filter processing).
Figure 23 shows the state-space model of time series, the discrete time state equation formula of the model by following formula (3),
(4) equation of state, observation equation are provided.
X (k+1)=Ax (k)+v (k) (3)
Y (k)=x (k)+w (k) (4)
X (k) is moment k state, and y (k) is observation.V (k) is system noise, and w (k) is observation noise, and A is system
Matrix.In the case where x (k) is frequency of oscillation (frequency control data), A is for example equivalent to rate of ageing (aging coefficient).Always
Change rate representation frequency of oscillation relative to the rate of change during process.
For example, generating holding pattern at the time of being set to shown in the C2 in Figure 22.In this case, according to reference signal
Time of day x (k) at the time of the C2 that RFCK is interrupted and rate of ageing (A) execution equivalent to the slope shown in Figure 22 C3
Age correction.Specifically, as reducing the compensation (correction) changed as frequency caused by the rate of ageing shown in C3, example
Such as to eliminate the corrected value that (counteractings) frequency changes, the true value of the frequency of oscillation (frequency control data) at the time of entering to exercise C2
The age correction that x (k) changes successively.That is, the frequency change under the rate of ageing shown in Figure 20 B2 is eliminated, so as to B1
The corrected value of shown preferable characteristic changes true value x (k).So, for example the feelings during holding pattern for 24 hours
Under condition, Figure 22 of variation as the frequency of oscillation after 24 hours FDV can be compensated by age correction.
Here, include and become as caused by temperature change in the variation of frequency of oscillation (frequency departure) shown in the C1 in Figure 22
The dynamic and variation as caused by aging.Therefore, in the present embodiment, for example by using the constant temperature slot structure with thermostat
Oscillator (OCXO), the variation of the frequency of oscillation as caused by temperature change is suppressed to Min..In addition, using Fig. 2's
The grade of temperature sensor 10 performs the temperature-compensating processing of the variation of reduction frequency of oscillation as caused by temperature change.
Moreover, during PLL circuit (internal PLL circuit, outside PLL circuit) is synchronous with reference signal RFCK (generally
During action) in, monitoring frequency control data (FREQUENCY CONTROL code) is obtained after removal error (system noise, observation noise)
True value, and it is stored in register.Moreover, in the disappearance due to reference signal RFCK or lock that is abnormal and relieving PLL circuit
In the case of fixed, held according to the true value (for the true value of the observation of frequency control data) preserved at the time of latch-release
Row age correction.For example, as reduce by Figure 22 C3 slope be rate of ageing caused by frequency change compensation, enter
The true value of frequency control data of the row to being preserved adds the processing for the corrected value for for example eliminating frequency change successively, thus,
Generate holding pattern during self-oscillation when frequency control data DFCQ, make oscillator XTAL vibrate.So, due to can be with
Minimal error is obtained into true value at the time of holding pattern, and performs age correction, will be changed therefore, it is possible to realize by aging
Caused harmful effect is suppressed to minimal holding mode performance.
9. the structure of processing unit
Figure 24 shows the detailed construction example of processing unit 50.As shown in figure 24, processing unit 50 includes Kalman filtering portion 54, old
Change correction unit 56, temperature compensation division 58, selector 62,63, adder 65.
The input of Kalman filtering portion 54 has frequency control data DFCI (to eliminate the FREQUENCY CONTROL number of environmental turbulence composition
According to), perform Kalman filtering processing.Moreover, output is estimated equivalent to the posteriority that the true value estimated is handled by Kalman filtering
Evaluation x^ (k).In addition, being that the symbol " ^ " of the hat of estimate is properly arranged to 2 characters by expression in this manual
To be recorded.
Kalman filtering processing refers to following processing：Made an uproar assuming that being included in the variable of observation and the state for representing system
Sound (error), uses the optimum state for carrying out estimating system from the past to the observation obtained now.Specifically, sight is repeated
Survey and update (observation process) and time renewal (prediction process), estimated state.Observation renewal is to be updated using observation with the time
Result update the process of kalman gain, estimate, error covariance.Time is updated the result for being to be updated using observation and come
Predict estimate, the process of error covariance of subsequent time.In addition, in the present embodiment, primarily illustrating using linear
The method of Kalman filtering processing, but also can be using EKF processing.Kalman on present embodiment filters
The details of ripple processing, will be described later.
Age correction portion 56 inputs posterior estimate x^ (k) and corrected value D ' (k) from Kalman filtering portion 54.Moreover, logical
The calculation process for carrying out that corrected value D ' (k) is added to the posterior estimate x^ (k) of the true value equivalent to frequency control data is crossed, it is raw
It is AC (k) into the frequency control data after age correction.Here D ' (k) is the correction (after low-pass filtering treatment) after filtering process
Value D (k).That is, setting time step k, (moment k) corrected value (corrected value after filtering process) is D ' (k), time step k aging
In the case that frequency control data after correction is AC (k), age correction portion 56 is obtained by AC (k+1)=AC (k)+D ' (k)
Frequency control data AC (k+1) after time step k+1 (moment k+1) age correction.
The input temp of temperature compensation division 58 detects data DTD, carries out temperature-compensating processing, generates for making frequency of oscillation phase
Stationary temperature offset data TCODE (temperature-compensating code) is remained for temperature change.
The temperature characterisitic of frequency of oscillation has relatively large deviation according to the sample of each product.Therefore, at product (oscillator)
Manufacture, shipment when inspection operation in, measure frequency of oscillation temperature characterisitic and temperature detection number corresponding with environment temperature
According to variation characteristic.And the coefficient A of the multinomial (approximate function) of following formula (5) is obtained according to measurement result0~A5, will ask
The coefficient A obtained0~A5Information be written in Fig. 2 storage part 34 (nonvolatile memory) and stored.
TCODE=A5·X5+A4·X4+A3·X3+A2·X2+A1·X+A0···(5)
In above formula (5), X is equivalent to the temperature detection data DTD (A/D conversion values) obtained by A/D converter sections 20.Due to
The temperature detection data DTD changed relative to environment temperature change is also measured, therefore, passes through the multinomial institute of above formula (5)
Environment temperature, can be mapped by the approximate function of expression with frequency of oscillation.Temperature compensation division 58 is read from storage part 34
Number A0~A5Information, according to coefficient A0~A5The calculation process of above formula (5) is carried out with temperature detection data DTD (=X), it is raw
Into temperature compensation data TCODE (temperature-compensating code).Thereby, it is possible to realize for making frequency of oscillation relative to the change of environment temperature
Change remains stationary temperature compensation deals.
Selector 62,63 is selected " 1 " in the case where the logic level of selection terminal S input signal is " 1 " (effective)
The input signal of the terminal of side, and exported as output signal.In addition, the logic level of the input signal in selection terminal S
In the case of " 0 " (invalid), the input signal of the terminal of " 0 " side is selected, and is exported as output signal.
Signal KFEN is the enable signal of Kalman filtering processing.Kalman filtering portion 54 is logic level in signal KFEN
Kalman filtering processing is performed in the case of " 1 " (following, to be abbreviated as " 1 ").Signal PLLLOCK be PLL circuit for locking shape
Turn into the signal of " 1 " in the case of state.Signal HOLDOVER is to turn into " 1 " during the holding pattern of holding pattern is detected
Signal.
Signal TCEN is the enable signal of temperature-compensating processing.Hereinafter, mainly using signal TCEN as " 1 " and selector 63
Illustrated in case of the input signal for selecting " 1 " side.In addition, signal KFEN is also " 1 ".
During usual action, because signal HOLDOVER is that ((following, to be abbreviated as " 0 ") therefore, is selected logic level " 0 "
Select the frequency control data DFCI that device 62 selects " 0 " terminals side.Moreover, being added by 65 couples of frequency control data DFCI of adder
Upper temperature compensation data TCODE, the frequency control data DFCQ after temperature-compensating processing are output to the oscillator signal life of rear class
Into circuit 140.
On the other hand, during holding pattern, signal HOLDOVER is " 1 ", and selector 62 selects the AC of " 1 " terminals side
(k).AC (k) is the frequency control data after age correction.
Figure 25 is the truth table for the action for illustrating Kalman filtering portion 54.All it is the feelings of " 1 " in signal PLLLOCK, KFEN
Under condition, Kalman filtering portion 54 performs true value estimation processing (Kalman filtering processing).That is, PLL electricity in during usual action
In the case that road (PLL circuit either internally or externally) is in the lock state, the lasting FREQUENCY CONTROL number carried out as observation
Handled according to DFCI true value estimation.
Moreover, in the state as the pattern of holding, the locking of PLL circuit is released, so that signal PLLLOCK is the feelings of " 0 "
Under condition, Kalman filtering portion 54 keeps the output state of last time.For example in fig. 24, preserve and continue to export the inspection of holding pattern
The value gone out the moment under (at the time of the latch-release of PLL circuit), is used as the posteriority for the true value for being estimated as frequency control data DFCI
Estimate x^ (k) and age correction corrected value D ' (k).
Age correction portion 56 during holding pattern in, using the posterior estimate x^ (k) from Kalman filtering portion 54,
Corrected value D ' (k) carries out age correction.Specifically, posterior estimate x^ (k), the correction at the detection moment of holding pattern are preserved
Value D ' (k), carries out age correction.
In addition, in fig. 24, it (is inventionbroadly environment that input, which eliminates temperature change composition, in Kalman filtering portion 54
Variance components) and temperature change composition in aging variance components frequency control data DFCI.54 pairs of Kalman filtering portion is gone
Except the frequency control data DFCI of temperature change composition (environmental turbulence composition) carries out Kalman filtering processing, estimation is for frequency
Rate control data DFCI true value.That is, posterior estimate x^ (k) is obtained.Moreover, age correction portion 56 is according to the true value estimated
That is posterior estimate x^ (k) carries out age correction.More specifically, according to the posterior estimate x^ from Kalman filtering portion 54
(k) the frequency control data AC (k) after age correction is obtained with corrected value D ' (k).Moreover, the FREQUENCY CONTROL number after age correction
Adder 65 is input to via selector 62 according to i.e. AC (k), adder 65 carries out adding temperature compensation data TCODE to AC (k)
The processing of (the compensation data of environmental turbulence composition).
For example, as shown in Figure 26 schematic diagram, when temperature change, as shown in E1, frequency control data is also corresponding
Ground changes.Therefore, when carrying out Kalman filtering using the frequency control data changed as E1 along with temperature change
During processing, the true value at holding pattern detection moment also produces fluctuation.
Therefore, in the present embodiment, the frequency control data for eliminating temperature change composition is obtained, and is input to karr
Graceful filtering part 54.That is, by the temperature change eliminated in temperature change composition (environmental turbulence composition) and aging variance components into
The frequency control data divided is input to Kalman filtering portion 54.That is, the frequency control data shown in input Figure 26 E2.E2 frequency
Rate control data is eliminates the frequency control data that temperature change composition remains aging variance components.
Kalman filtering portion 54 to so eliminating temperature change composition by remaining the frequencies of aging variance components
Control data DFCI carries out Kalman filtering processing, obtains the correction of the posterior estimate x^ (k) for being estimated true value, age correction
Value D ' (k).Moreover, the true value i.e. posterior estimate x^ (k), the corrected value D ' (k) that will be estimated at the detection moment of the pattern of holding
Age correction portion 56 is saved in, for performing age correction.
The processing plus temperature compensation data TCODE is for example carried out by adder 65, frequency control data DFCQ turns into
By the frequency control data after temperature-compensating.Therefore, input has frequency control data DFCQ oscillator signal generative circuit 140 defeated
The oscillator signal OSCK of the frequency of oscillation gone out after temperature-compensating.Therefore, PLL is constituted together with the oscillator signal generative circuit 140
Fig. 2 of circuit (or the foreign frequency control data generating unit 200 of frequency control data generating unit 40.It is same below) will be such as figure
Eliminating the frequency control data DFCI after temperature change composition is supplied to processing unit 50 like that shown in 26 E2.Moreover, as schemed
Shown in 26 E2, remain and change with the elapsed time in the frequency control data DFCI for eliminating the temperature change composition
Aging variance components.Therefore, 54 pairs of the Kalman filtering portion of processing unit 50 remains the FREQUENCY CONTROL of the aging variance components
Data DFCI carries out Kalman filtering processing, if the result that age correction portion 56 is handled according to Kalman filtering carries out aging school
Just, then high-precision age correction can be realized.
In addition, as Figure 24 variation, can be without the place plus temperature compensation data TCODE in adder 65
Reason, and the calculation process of the temperature change composition (environmental turbulence composition) for removing frequency control data DFCI is carried out, and will
Frequency control data DFCI after calculation process is input to Kalman filtering portion 54.For example omit Figure 17 adder 65 and choosing
The structure of device 63 is selected, the prime in Kalman filtering portion 54 is set subtracts temperature compensation data from frequency control data DFCI
TCODE subtracter, Kalman filtering portion 54 is input to by the output of the subtracter.In addition, in age correction portion 56 and selection
The adder that the output in age correction portion 56 is added with temperature compensation data TCODE is set between device 62, by the defeated of adder
Go out to be input to the terminal of " 1 " side of selector 62.By such structure, also temperature change composition can will be eliminated and only residual
The frequency control data DFCI for leaving aging variance components is input to Kalman filtering portion 54.
Figure 27 shows the detailed construction example in age correction portion 56.During usual action, signal HOLDOVER is
" 0 ", therefore, selection " 0 " terminals side of selector 360,361.Thus, in during usual action, transported by Kalman filtering portion 54
Posterior estimate x^ (k), the corrected value D ' (k) (corrected value after filtering process) calculated be saved in respectively register 350,
351。
When detecting holding pattern, so that when signal HOLDOVER is " 1 ", selector 360,361 selects " 1 " terminals side.
Thus, during selector 361 is during holding pattern, lasting output is stored in register 351 at the detection moment of the pattern of holding
Corrected value D ' (k).
Moreover, adder 340 is handled as follows：According to each time step, to being stored at the detection moment of the pattern of holding
The posterior estimate x^ (k) of register 350 is successively plus the corrected value D ' for being stored in register 351 and being exported from selector 361
(k) (corrected value).Hereby it is achieved that the age correction shown in following formula (6).
AC (k+1)=AC (k)+D ' (k) (6)
That is, it is handled as follows to realize age correction：To the true value i.e. Posterior estimator preserved at the time of Figure 22 C2
Value x^ (k) adds corrected value D ' (k) successively, and the corrected value D ' (k) is used to eliminate the aging of (compensation) by the slope equivalent to C3
Frequency changes caused by speed.
10. Kalman filtering processing
Next, the details to the Kalman filtering processing of present embodiment are illustrated.The model of Kalman filtering
Equation of state, observation equation are represented as following formula (7), (8).
X (k+1)=Ax (k)+v (k) (7)
Y (k)=CT+x(k)+w(k)···(8)
K is denoted as the time step of discrete time.X (k) is time step k (state of moment k) system, e.g. n
The vector of dimension.A is referred to as sytem matrix.Specifically, A is n × n matrix, there will be no in the case of system noise when
The state relation of the state of spacer step k system and time step k+1 system gets up.V (k) is system noise.Y (k) is observation,
W (k) is observation noise.C is that observed differential is vectorial (n dimensions), and T represents transposed matrix.
In the Kalman filtering processing of above formula (7), the model of (8), the processing of following formula (9)~(13) is carried out, estimation is true
Value.
P-(k)=AP (k-1) AT+v(k)···(10)
P (k)=(1-G (k) CT)·P-(k)···(13)
x^(k)：Posterior estimate
x^-(k)：Priori estimates
P(k)：Posteriority covariance
P-(k)：Priori covariance
G(k)：Kalman gain
Above formula (9), (10) are the formulas for the time updating (prediction process), and above formula (11)~(13) are that observation updates (observation
Process) formula.Often advance 1 as the time step k of discrete time, then carry out the time of 1 Kalman filtering processing more
Newly (formula (9), (10)) and observation update (formula (11)~(13)).
X^ (k), x^ (k-1) are the posterior estimates of time step k, k-1 Kalman filtering processing.x^-(k) it is to be seen
The priori estimates predicted before measured value.P (k) is the posteriority covariance of Kalman filtering processing, P-(k) be obtain observation it
The priori covariance of preceding prediction.G (k) is kalman gain.
In Kalman filtering processing, in observation updates, kalman gain G (k) is obtained by above formula (11).In addition,
According to observation y (k), by above formula (12), posterior estimate x^ (k) is updated.In addition, by above formula (13), updating error
Posteriority covariance P (k).
In addition, in Kalman filtering processing, in the time updates, such as shown in above formula (9), after time step k-1
Estimate x^ (k-1) and sytem matrix A is tested, prediction future time walks k priori estimates x^-(k).In addition, such as above formula (10)
It is shown, according to time step k-1 posteriority covariance P (k-1), sytem matrix A, system noise v (k), prediction future time step k's
Priori covariance P-(k)。
In addition, when the Kalman filtering processing of above formula to be performed (9)~(13), the processing load mistake of processing unit 50 sometimes
Greatly, the large-scale of circuit arrangement is caused.For example for the x^ for obtaining above formula (9)-(k)=Ax^ (k-1) A is, it is necessary to expansion card
Kalman Filtering processing.Moreover, the processing load of EKF processing is weighed very much, when will be by that can be extended karr
The hardware of graceful filtering process realizes during processing unit 50 that the circuit area of processing unit 50 easily becomes very large.Therefore, when internal
It is placed in the circuit arrangement of oscillator to be strongly required under the situation of miniaturization, is inappropriate.On the other hand, when use fixed value
When scalar value is as sytem matrix A, realize that difficulty during appropriate age correction is improved.
Therefore, as solution when needing to avoid such situation, in the present embodiment, above formula (9) are not passed through
~(13), and Kalman filtering is realized by the processing based on following formula (14)~(19) and is handled.That is, (the Kalman of processing unit 50
Filtering part 54) perform the Kalman filtering processing based on following formula (14)~(19).
P-(k)=P (k-1)+v (k) (15)
P (k)=(1-G (k)) P-(k)···(18)
In addition, be frequency control data as the x (k) of the object of the estimation processing of true value in the present embodiment, observation
Value y (k) is also frequency control data, therefore, C=1.Further, since A scalar value is infinitely close to 1, therefore, it is possible to use
Above formula (15) substitutes above formula (10).
As described above, compared with the situation for being used as Kalman filtering processing is handled using EKF, at this
In the Kalman filtering processing of embodiment, such as shown in above formula (14), passage time step k-1 posterior estimate x^ (k-1) with
Corrected value D (k-1) addition handles to obtain time k priori estimates x^-(k).It therefore, there is no need to use spreading kalman
Filtering process is excellent in terms of realizing that the mitigation of processing load of processing unit 50, the increase of circuit scale suppress.
In the present embodiment, above formula (14) is exported by the deformation of following formulas.
For example above formula (20) can be deformed as above formula (21).Here, because (A-1) of above formula (21) is very small
Number, therefore, such as shown in above formula (22), (23), can use (A-1) x^ (k-1) being replaced into (A-1) F0It is approximate.So
Afterwards, by (A-1) F0It is replaced into corrected value D (k-1).
And as shown in above formula (19), when being updated from time step k-1 to time step k time, it is corrected value D (k)
=D (k-1)+E (y (k)-x^-(k))=D (k-1)+Eek renewal processing.Here, ek=y (k)-x^-(k) it is referred to as card
Observation residual error in Kalman Filtering processing.In addition, E is constant.In addition, can also substitute constant E, and implement to increase using Kalman
The deformation of beneficial G (k).I.e., it is possible to be D (k)=D (k-1)+G (k) ek.
So, in formula (19), set observation residual error be E as ek, constant in the case of, pass through D (k)=D (k-1)+E
Ek obtains corrected value D (k).In such manner, it is possible to carry out reflecting observation residual error ek, the corrected value D (k) in Kalman filtering processing
Renewal processing.
As described above, in the present embodiment, such as shown in above formula (14), the priori that processing unit 50 is handled in Kalman filtering
In the renewal processing (time renewal) of estimate, it is handled as follows：By the posterior estimate x^ (k-1) at the time of last time with
Corrected value D (k-1) addition processing, priori estimates x^ at the time of obtaining this-(k).Moreover, at according to Kalman filtering
The result of reason, carries out the age correction of frequency control data.That is, carry out last time at the time of be time step k-1 posterior estimate x
^ (k-1) is added processing with corrected value D's (k-1), passes through x^-(k)=x^ (k-1)+D (k-1) i.e. times at the time of obtain this
Walk k priori estimates x^-(k)。
Moreover, the result (true value, corrected value) that is handled according to the Kalman filtering of processing unit 50 (age correction portion 56) come
Carry out age correction.That is, time step k corrected value is being set as the frequency after D (k) (or D ' (k)), time step k age correction
In the case that rate control data is AC (k), time step k is obtained by AC (k+1)=AC (k)+D (k) (or AC (k)+D ' (k))
Frequency control data AC (k+1) after+1 age correction.
In addition, processing unit 50 is filtered as shown in above formula (19) according to the corrected value D (k-1) at the time of last time and Kalman
Observation residual error ek in ripple processing, the corrected value D (k) at the time of obtaining this.For example, by carrying out school at the time of to last time
The processing that the value based on observation residual error is Eek (or G (k) ek), school at the time of obtaining this are added on the occasion of D (k-1)
On the occasion of D (k).Specifically, according to last time it is during time step k-1 corrected value D (k-1) and Kalman filtering is handled at the time of
Observe residual error ek, i.e. time step k corrected value D (k) at the time of obtaining this.For example, being E setting observation residual error as ek, constant
In the case of, corrected value D (k) is obtained by D (k)=D (k-1)+Eek.
For example in the present embodiment, as illustrated in Figure 26, the environmental turbulences such as temperature change composition information are obtained
Composition information, and using the environmental turbulence composition information obtained, acquirement is eliminated in environmental turbulence composition and aging variance components
Environmental turbulence composition frequency control data.Here, environmental turbulence composition information can be power supply voltage variation composition, air pressure
Variance components or gravity variance components etc..Then, according to the frequency control data for eliminating environmental turbulence composition, aging is carried out
Correction.Specifically, if environmental turbulence composition is temperature.According to temperature detection data DTD, obtain and believe as environmental turbulence composition
The temperature change composition information of breath, temperature detection data DTD is by from the work for obtaining environmental turbulence composition information
Obtained for the temperature detection voltage VTD of Fig. 2 of environmental turbulence information acquiring section temperature sensor 10.Moreover, using taking
The temperature change composition information obtained, obtains the frequency control data for eliminating temperature change composition.Such as Figure 24 temperature-compensating
Portion 58 obtains temperature compensation data TCODE, and the addition for carrying out temperature compensation data TCODE by adder 65 is handled, and thus, is gone
Except temperature change composition frequency control data DFCI from frequency control data generating unit 40 (or foreign frequency control data life
Into portion 200) input, and obtained by processing unit 50.That is, as shown in Figure 26 E2, acquirement eliminates temperature change composition and remained
There is the frequency control data DFCI of aging variance components, and be input to Kalman filtering portion 54.
In addition, eliminating the frequency control data of environmental turbulence composition except comprising completely eliminated environmental turbulence composition
Outside the frequency control data of appropriate state, there is the environmental turbulence for the degree that can ignore that also in frequency control data
The frequency control data of the state of composition.
For example, can be by detecting environmental turbulence composition information, TEMP as environmental turbulence information acquiring section
Device and voltage detecting circuit etc. obtain the environmental turbulence composition such as temperature change composition information or power supply voltage variation composition information
Information.On the other hand, aging variance components are the variance components for the frequency of oscillation passed through with the time and changed, it is difficult to pass through sensing
Device etc. directly detects the information of the aging variance components.
Therefore, in the present embodiment, obtaining can be become by environment such as the temperature change composition informations of the detections such as sensor
Dynamic composition information, and the environmental turbulence composition information is utilized, acquirement is eliminated in environmental turbulence composition and aging variance components
The frequency control data of environmental turbulence composition.That is, by carrying out removing environmental turbulence from the variance components of frequency control data
The processing (such as addition process of adder 65) of composition, can be obtained as shown in Figure 26 E2 and only remain aging change
The frequency control data of dynamic composition.Then, if carrying out Kalman according to the frequency control data for remaining aging variance components
Filtering process etc., then can estimate the true value for frequency control data.If moreover, entered according to the true value so estimated
Row age correction, then can realize the high-precision age correction that can not be realized in the prior embodiment.
So, in the present embodiment, input eliminates temperature change composition (environmental turbulence in Kalman filtering portion 54
Composition) and remain the frequency control data DFCI of aging variance components.And as shown in Figure 19, Figure 22, if the phase of restriction
Between, then within this period, it can be assumed that frequency of oscillation is changed with constant rate of ageing.It can be assumed that for example with Figure 22 C3 institutes
The constant slope variation shown.
In the present embodiment, by D (k)=D (k-1)+Eek formula, obtained for compensating (elimination) by this
The corrected value of frequency change caused by the aging variance components of sample under constant rate of ageing.That is, obtained for compensate by
The corrected value D (k) that frequency changes caused by the rate of ageing of the slope of C3 equivalent to Figure 22.Here, rate of ageing is not permanent
Fixed, but as shown in Figure 19, Figure 22, change with the elapsed time.
In this regard, in the present embodiment, as D (k)=D (k-1)+Eek, the observation handled according to Kalman filtering
Residual error ek=y (k)-x^-(k) the renewal processing of corrected value D (k) corresponding with rate of ageing, is carried out.Therefore, it is possible to realize also
Reflect change, corrected value D (k) the renewal processing of rate of ageing corresponding with the elapsed time.It is higher therefore, it is possible to realize
The age correction of precision.
11. variation
Then, the various modifications example of present embodiment is illustrated.Figure 28 shows the circuit arrangement of modified embodiment of the present embodiment
Configuration example.
It is different from Fig. 1, Fig. 2 in Figure 28, D/A converter sections 80 are not provided with oscillator signal generative circuit 140.Also,
The oscillator signal OSCK generated by oscillator signal generative circuit 140 frequency of oscillation is according to the FREQUENCY CONTROL number from processing unit 50
It is directly controlled according to DFCQ.That is, oscillator signal OSCK frequency of oscillation is controlled not via D/A converter sections.
For example in Figure 28, oscillator signal generative circuit 140 has variable capacitance circuit 142 and oscillating circuit 150.At this
Fig. 1, Fig. 2 D/A converter sections 80 are not provided with oscillator signal generative circuit 140.Also, replace Figure 14 variable capacitance electric capacity
Device CX1 and the variable capacitance circuit 142 is set, one end of variable capacitance circuit 142 is connected with oscillator XTAL one end.
The capacitance of the variable capacitance circuit 142 is controlled according to the frequency control data DFCQ from processing unit 50.
For example, variable capacitance circuit 142 has multiple capacitors (array of capacitors), controls each switch according to frequency control data DFCQ
The switched on and off multiple switch element (switch arrays) of element.Each switch element of this multiple switch element and multiple electric capacity
Each capacitor electrical connection of device.Also, by being switched on or switched off in this multiple switch element, multiple capacitors, one end with shaking
The number of the capacitor of sub- XTAL one end connection changes.Thus, the capacitance of variable capacitance circuit 142 is controlled, and is shaken
The capacitance of sub- XTAL one end changes.Therefore, variable capacitance circuit is directly controlled using frequency control data DFCQ
142 capacitance, control oscillator signal OSCK frequency of oscillation.
12. oscillator, electronic equipment, moving body
Figure 29 shows the configuration example of the oscillator 400 of the circuit arrangement 500 comprising present embodiment.As shown in figure 29, shake
Swing device 400 and include oscillator 420 and circuit arrangement 500.Oscillator 420 and circuit arrangement 500 are installed on the encapsulation 410 of oscillator 400
It is interior.Also, the terminal of oscillator 420 and the terminal (pad) of circuit arrangement 500 (IC) are electrically connected using the internal wiring of encapsulation 410
Connect.
Figure 30 shows the configuration example of the electronic equipment of the circuit arrangement 500 comprising present embodiment.The electronic equipment is included
The oscillators such as circuit arrangement 500, the quartz vibrator of present embodiment 420, antenna ANT, communication unit 510 and processing unit 520.In addition,
Operating portion 530, display part 540 and storage part 550 can also be included.Oscillator 400 is constituted by oscillator 420 and circuit arrangement 500.
In addition, electronic equipment is not limited to Figure 30 structure, it is possible to implement omit the structural element or additional other structures of a portion
The various modifications such as key element.
As Figure 30 electronic equipment, such as it can be assumed that network relevant device base station or router, high-precision
Measuring apparatus, GPS onboard clocks, biological information detecting equipment (sphygmometer, pedometer etc.) or head-mount formula display device
It is whole etc. mobile informations such as wearable device, smart mobile phone, mobile phone, portable type game device, notebook PC or tablet PCs
Hold the various equipment such as the image documentation equipments such as (mobile terminal), content providing terminal, digital camera or the video camera of issuing content.
Communication unit 510 (radio-circuit) carries out sending data via antenna ANT from external reception data or to outside
Processing.Processing unit 520 carries out the control process of electronic equipment and to the various numbers for the data received and dispatched via communication unit 510
Word processing etc..The function of the processing unit 520 such as can by microcomputer processor and realize.
Operating portion 530 is used to carry out input operation for user, can be by operation button, touch panel display etc. come real
It is existing.Display part 540 is used to show various information, can be realized by liquid crystal, organic EL etc. display.In addition, using tactile
Touch in the case that panel display is used as operating portion 530, the touch panel display has operating portion 530 and display part concurrently
540 function.Storage part 550 is used for data storage, and its function can (hard disk drives by the semiconductor memories such as RAM, ROM or HDD
Dynamic device) etc. realize.
Figure 31 shows the example of the moving body of the circuit arrangement comprising present embodiment.The circuit arrangement of present embodiment
In (oscillator) various moving bodys such as can be assembled into vehicle, aircraft, motorcycle, bicycle or ship.Mobile style
Have drive mechanism, steering wheel or the Duo Deng steering mechanism such as engine or motor and various electronic equipments (vehicle-mounted to set in this way
It is standby), and on land, aerial or marine mobile device.Figure 31 summary is shown as the concrete example of moving body
Automobile 206.The oscillator (not shown) of circuit arrangement and oscillator with present embodiment is assembled in automobile 206.Control dress
208 bases are put to be acted by the clock signal that the oscillator is generated.Control device 208 according to such as car body 207 posture
Soft durometer to suspension is controlled, or the braking of each wheel 209 is controlled.Control device can for example be utilized
208 realize the automatic operating of automobile 206.In addition, the equipment for the circuit arrangement or oscillator for being assembled with present embodiment is not limited to
This control device 208, can also be assembled in the various equipment (mobile unit) set by the grade moving body of automobile 206.
Figure 32 is the detailed construction example of oscillator 400.Figure 32 oscillator 400 is that double constant temperature slot structures (are inventionbroadly
Constant temperature slot structure) oscillator.
Encapsulation 410 is made up of substrate 411 and housing 412.Various electronic units (not shown) are equipped with substrate 411.
The 2nd container 414 is provided with the inside of housing 412, the 1st container 413 is provided with the inside of the 2nd container 414.Also, in the 1st container
The medial surface (downside) of 413 upper surface is provided with oscillator 420.In addition, the upper surface of the 1st container 413 lateral surface (on
The circuit arrangement 500, heater 450 and temperature sensor 460 of present embodiment are installed sideways).Heater 450 can be passed through
(heater element), adjusts the temperature of such as inside of the 2nd container 414.Further, it is possible to which by temperature sensor 460, detection is for example
The temperature of the inside of 2nd container 414.
2nd container 414 is arranged on substrate 416.Substrate 416 is can to carry the circuit substrate of various electronic units.
The reverse side in face in substrate 416, being provided with the 2nd container 414 installs having heaters 452 and temperature sensor 462.It can pass through
The temperature in such as space between heater 452 (heater element), the adjustment container 414 of housing 412 and the 2nd.Further, it is possible to pass through
The temperature in the space between temperature sensor 462, the detection container 414 of housing 412 and the 2nd.
As the heater element of heater 450,452, for example, heating power bipolar transistor, heating type can be used to add
Hot device MOS transistor, heating resistor, Peltier element etc..The control example of the heating of these heaters 450,452 is if logical
The thermostat of oversampling circuit device 500 controls circuit to realize.As temperature sensor 460,462, for example, it can use temperature-sensitive electricity
Resistance, diode etc..
In Figure 32, due to that can realize that the temperature of the grade of oscillator 420 is adjusted by the thermostat of double constant temperature slot structures, because
This, realizes stabilisation of the frequency of oscillation of oscillator 420 etc..
Figure 33 is the configuration example of the base station (base station apparatus) as one of electronic equipment.Physical layer circuit 600 carry out via
The processing of physical layer in the communication process of network.Network processing unit 602 leaned on than physical layer the processing (link layer of upper layer
Deng).Switch portion 604 carries out the various hand-off process of communication process.DSP 606 carries out the various data signals needed for communication process
Processing.RF circuits 608 are included：The receiving circuit being made up of low-noise amplifier (LNA)；The transmission electricity being made up of power amplifier
Road；D/A converter and A/D converter etc..
Selector 612 is by the reference signal RFCK1 from GPS 610, the reference signal from physical layer circuit 600
Any one in RFCK2 (clock signal for carrying out automatic network) is output to the circuit of present embodiment as reference signal RFCK
Device 500.It is synchronous with reference signal RFCK that circuit arrangement 500 enters to exercise oscillator signal (input signal based on oscillator signal)
Processing.And generation different various clock signal CK1, CK2, CK3, CK4, CK5 of frequency, and be supplied to physical layer circuit 600,
Network processing unit 602, switch portion 604, DSP606, RF circuit 608.
According to the circuit arrangement 500 of present embodiment, in the base station shown in Figure 33, oscillator signal can be made to believe with benchmark
Number RFCK synchronizations, base station is supplied to by the high clock signal CK1~CK5 of the frequency stability generated according to the oscillator signal
Each circuit.
In addition, present embodiment is described in detail as described above, and for those of ordinary skill in the art, should
It can easily understand that the various deformation of the new item and effect that do not actually detach the present invention.Therefore, such variation is all included
Within the scope of the invention.For example, in specification or accompanying drawing, at least one times from more broad sense or synonymous different terms
The term (temperature change composition etc.) that (environmental turbulence composition etc.) is together recorded all may be used in the arbitrary portion of specification or accompanying drawing
To be replaced into the different terms.In addition, all combinations of present embodiment and variation are also included within the scope of the present invention.This
Outside, circuit arrangement, oscillator, electronic equipment, structure/action of moving body, circuit block, the collocation method of terminal, age correction
Processing, Kalman filtering processing, keep that mode treatment, temperature-compensating processing etc. be also not necessarily limited to illustrate in present embodiment it is interior
Hold, various modifications can be implemented.
Claims (16)
1. a kind of circuit arrangement, wherein, the circuit arrangement is included：
Digital interface portion；
Processing unit, it is connected with the digital interface portion；
Oscillator signal generative circuit, it uses oscillator and the data generation oscillator signal from the processing unit；
Clock signal generating circuit, it is generated the clock signal of the frequency after the frequency of oscillation frequency multiplication of the oscillator signal；
The terminal group of the connection in the digital interface portion, set circuit arrangement with the 1st while intersect while as the 2nd side and institute
State the 1st when relative be the 3rd while, with the described 2nd while it is relative while for the 4th while in the case of, the company in the digital interface portion
The terminal group connect is configured at the 1st region along the 1st side；And
The terminal group of the connection of the clock signal generating circuit, its be configured at the 2nd region along the 2nd side, along
Described 3rd while the 3rd region, along the described 4th while the 4th region in any one region.
2. circuit arrangement according to claim 1, wherein,
The circuit arrangement is also comprising the terminal group for being configured at the 2nd region, oscillator signal generative circuit connection.
3. circuit arrangement according to claim 2, wherein,
The terminal group of the connection of the clock signal generating circuit is configured at the 3rd region.
4. circuit arrangement according to claim 1, wherein,
1st side is the short side of the circuit arrangement.
5. circuit arrangement according to claim 2, wherein,
In the terminal group and the terminal group of the connection of the oscillator signal generative circuit for setting the connection in the digital interface portion
The distance between used for the connection of L12, the terminal group of the connection in the digital interface portion and the clock signal generating circuit
The distance between terminal group be L13, the terminal group of the connection of the oscillator signal generative circuit gives birth to the clock signal
In the case that the distance between terminal group of connection into circuit is L23, at least one in L12 and L13 is longer than L23.
6. circuit arrangement according to claim 1, wherein,
FREQUENCY CONTROL number from the external device (ED) being compared to the input signal based on the oscillator signal and reference signal
The processing unit is input to according to the terminal group and the digital interface portion of the connection via the digital interface portion,
The processing unit is to frequency control data progress signal transacting, the frequency control data after output processing,
The oscillator signal generative circuit generates the oscillator signal according to the frequency control data after the processing.
7. circuit arrangement according to claim 6, wherein,
The circuit arrangement also includes phase comparing section, phase of the phase comparing section to the input signal based on the oscillator signal
Position and the phase of the reference signal are compared,
The oscillator signal generative circuit is given birth under the 1st pattern according to the frequency control data from the external device (ED)
Into the oscillator signal,
The oscillator signal generative circuit is under the 2nd pattern, according to the frequency control data from the phase comparing section
Generate the oscillator signal.
8. circuit arrangement according to claim 1, wherein,
The digital interface portion is the serial line interface electricity of 2 lines comprising serial data line and serial time clock line, 3 lines or 4 lines
Road.
9. circuit arrangement according to claim 1, wherein,
The processing unit is configured between the 1st region and the clock signal generating circuit.
10. circuit arrangement according to claim 9, it is characterised in that
The oscillating circuit is configured between the processing unit and the clock signal generating circuit.
11. circuit arrangement according to claim 1, wherein,
The circuit arrangement also includes and is configured at the 4th region, the thermostat control terminal comprising constant temperature groove profile oscillator
Terminal group, the constant temperature groove profile oscillator include the oscillator and thermostat.
12. circuit arrangement according to claim 11, wherein,
The circuit arrangement also includes and is connected with the thermostat control with terminal and carries out the perseverance of the constant temperature groove profile oscillator
The thermostat control circuit of warm groove control.
13. circuit arrangement according to claim 12, wherein,
The oscillating circuit is configured between the thermostat control circuit and the 2nd region.
14. a kind of oscillator, wherein, the oscillator includes oscillator and circuit arrangement,
The circuit arrangement is included：
Digital interface portion；
Processing unit, it is connected with the digital interface portion；
Oscillator signal generative circuit, it uses oscillator and the data generation oscillator signal from the processing unit；
Clock signal generating circuit, it is generated the clock signal of the frequency after the frequency of oscillation frequency multiplication of the oscillator signal；
The terminal group of the connection in the digital interface portion, set circuit arrangement with the 1st while intersect while as the 2nd side and institute
State the 1st when relative be the 3rd while, with the described 2nd while it is relative while for the 4th while in the case of, the company in the digital interface portion
The terminal group connect is configured at the 1st region along the 1st side；And
The terminal group of the connection of the clock signal generating circuit, its be configured at the 2nd region along the 2nd side, along
Described 3rd while the 3rd region, along the described 4th while the 4th region in any one region.
15. a kind of electronic equipment, wherein, the electronic equipment includes the circuit arrangement described in claim 1.
16. a kind of moving body, wherein, the moving body includes the circuit arrangement described in claim 1.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016-001303 | 2016-01-06 | ||
| JP2016001303 | 2016-01-06 | ||
| JP2016-137666 | 2016-07-12 | ||
| JP2016137666A JP6680121B2 (en) | 2016-01-06 | 2016-07-12 | Circuit devices, oscillators, electronic devices and mobile units |
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| CN107040208A true CN107040208A (en) | 2017-08-11 |
| CN107040208B CN107040208B (en) | 2022-03-22 |
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| CN201611167174.2A Active CN107040208B (en) | 2016-01-06 | 2016-12-16 | Circuit device, oscillator, electronic apparatus, and moving object |
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| CN (1) | CN107040208B (en) |
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| CN111245433A (en) * | 2018-11-29 | 2020-06-05 | 精工爱普生株式会社 | Oscillator, electronic apparatus, and moving object |
| CN111245433B (en) * | 2018-11-29 | 2023-06-20 | 精工爱普生株式会社 | Oscillator, electronic apparatus, and moving object |
| CN112339679A (en) * | 2019-08-09 | 2021-02-09 | 广州汽车集团股份有限公司 | Vehicle-mounted display control system, method, terminal and vehicle |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107040208B (en) | 2022-03-22 |
| JP6680121B2 (en) | 2020-04-15 |
| JP2017123631A (en) | 2017-07-13 |
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