CN107039443B - Memory component and preparation method thereof - Google Patents
Memory component and preparation method thereof Download PDFInfo
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- CN107039443B CN107039443B CN201510437235.1A CN201510437235A CN107039443B CN 107039443 B CN107039443 B CN 107039443B CN 201510437235 A CN201510437235 A CN 201510437235A CN 107039443 B CN107039443 B CN 107039443B
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Abstract
The invention discloses a kind of memory component and preparation method thereof, which includes semiconductor substrate, separation layer, the first conductor layer, the first conductor layer, contact plunger, multiple insulating layers, multiple second conductor layers, channel layer and accumulation layer.Separation layer is located on semiconductor substrate.First conductor layer is located on separation layer contact plunger and passes through separation layer and in electrical contact with the first conductor layer and semiconductor substrate.Multiple insulating layers are located in the first conductor layer.Multiple second conductor layers and insulating layer cross laminates, and electrically isolated with the first conductor layer.Channel layer is located at first at least one side wall of opening and bottom surface, and in electrical contact with contact plunger, wherein first runs through opening across insulating layer and the second conductor layer, and contact plunger is exposed to outer.Accumulation layer is between channel layer and the second conductor layer.
Description
Technical field
The invention relates to a kind of nonvolatile memory (Non-Volatile Memory, NVM) element and its production
Method.In particular to a kind of vertical channel memory component and preparation method thereof.
Background technique
There are non-volatile memory device the data in deposit element will not disappear because of the interruption that power supply is supplied
Characteristic, thus become one of the memory component for being generally used to storage data at present.Flash memory is a kind of typical non-volatile
Memory technology.
The non-volatile memory device with vertical channel, such as the method for vertical channel nand flash memory are made, generally
It is first to form multi-layer laminate structure on a semiconductor substrate with multiple insulating layers and polysilicon layer cross laminates, then at multilayer laminated
It is formed in structure through opening, substrate is exposed to outer；And sequentially blanket covers accumulation layer, such as silicon-on the side wall through opening
Si oxide-silicon nitride-Si oxide-silicon (SONOS) accumulation layer and polysilicon channel layer, are used in accumulation layer, channel layer
And multiple storage units are defined on polysilicon layer, and storage unit is made by channel layer and shares source electrode line as bottom
Substrate be electrically connected.Wherein, source electrode line is shared in bottom can be utilized for the block erasing of non-volatile memory device
(block erase) operation.
However, since the doping that source electrode line is formed in generally by the mode of ion implanting substrate is shared in traditional bottom
Area, resistance value are higher.In addition the engagement interface between ion implantation doping area and substrate can generate parasitic capacitance, not only will increase
Power consumption and can to signal generate interference and time delay (RC delay), and then reduce memory component write-in/reading
The reliability and element speeds of extract operation.
Therefore, in need that a kind of vertical channel flash element and preparation method thereof is provided, it is faced to solve known technology
The problem of.
Summary of the invention
Of the invention one is towards relating to a kind of memory component, including semiconductor substrate, separation layer, the first conductor
Layer, contact plunger, multiple insulating layers, multiple second conductor layers, channel layer and accumulation layer.Separation layer is located at semiconductor substrate
On.First conductor layer is located on separation layer.Contact plunger passes through separation layer and is electrically connected with the first conductor layer and semiconductor substrate
Touching.Second conductor layer and insulating layer cross laminates are electrically isolated with the first conductor layer in the first conductor layer.Channel layer is located at
First at least one side wall of opening and bottom surface, and in electrical contact with contact plunger, wherein first through opening across
Insulating layer and the second conductor layer, and contact plunger is exposed to outer.Accumulation layer is between channel layer and the second conductor layer.
Another production method towards a kind of memory component is related to of the invention.The system of this memory component
Include the following steps: as method firstly, forming the first conductor layer on separation layer in forming separation layer on semiconductor substrate.
Later, multi-layer laminate structure (multilayers stack) is provided, makes multi-layer laminate structure that there are multiple insulating layers and multiple sacrificial
Domestic animal layer is mutually stacked in the first conductor layer, and sacrificial layer and the first conductor layer is isolated.At least one is re-formed first to run through
Opening passes through multi-layer laminate structure, the first conductor layer and separation layer, partly by insulating layer, sacrificial layer and semiconductor substrate
It is exposed to outer.Then, it is selectively deposited (selective deposition) technique, to run through the bottom of opening in first
Contact plunger is formed, it is in electrical contact with the first conductor layer and semiconductor substrate.Then, in first through at least one side of opening
Accumulation layer and channel layer are sequentially formed on wall, are located in accumulation layer between channel layer and remaining sacrificial layer, and make channel layer
It is in electrical contact with contact plunger.It is subsequent, formed at least one second through opening, pass through multi-layer laminate structure, make the first conductor
Layer, insulating layer and sacrificial layer are partially exposed to outer.And after running through the surplus sacrificial layer of opening removal by second, and in surplus
On the position of remaining sacrificial layer, multiple second conductive layers are formed.
Another production method towards a kind of memory component is related to of the invention.Under this production method includes
State step: firstly, in sequentially forming the first separation layer, the first conductor layer and the second separation layer on semiconductor substrate；And shape
At at least one contact openings, the second separation layer, the first conductor layer and separation layer are passed through, the substrate of a part is exposed to
Outside.Later, contact plunger is formed in contact openings, keeps it in electrical contact with the first conductor layer and substrate.Then, multilayer is provided
Laminated construction makes multi-layer laminate structure that there are multiple insulating layers and multiple sacrificial layers to be mutually stacked on the second separation layer.Then,
At least one is formed first through opening, multi-layer laminate structure and the second separation layer is passed through, and by insulating layer, sacrificial layer and connects
It is exposed to touching plug section outer.Accumulation layer and channel layer are sequentially formed at least one side wall of opening then at first,
It is located in accumulation layer between channel layer and remaining sacrificial layer, and keeps channel layer in electrical contact with contact plunger.It is subsequent, it is formed
At least one second through opening, pass through multi-layer laminate structure and the second separation layer, make the first conductor layer, insulating layer and residue
Sacrificial layer is partially exposed to outer；And after running through the remaining sacrificial layer of opening removal by second, in the position of remaining sacrificial layer
It sets and forms multiple second conductive layers.
According to above-described embodiment, the present invention is to provide a kind of three-dimensional storage element and preparation method thereof.It is half
A separation layer and a conductor layer are sequentially formed above conductor substrate, and forms at least one across separation layer and conductive layer and with half
The contact plunger of conductor and conductive layer electrical property.And the multi-layer laminate structure with multiple storage units is formed in conductor layer, with
And it is multiple be used to concatenate storage unit to form the serial channel layer of multiple storage units longitudinally through multi-layer laminate structure, and make
Each channel layer generates in electrical contact with a corresponding contact plunger.Wherein, the distance between conductor layer and channel layer are small
In the distance between semiconductor substrate and channel layer.
Due to, memory component provided by the embodiment of the present invention be using independent conductor layer, rather than it is semiconductor-based
Material shares source electrode line as the serial bottom of different storage units.Therefore it is used to the electric current into read/write operations, stream
It is shorter than the current path that memory component provided by known technology flows through semiconductor substrate through conductor layer path, therefore deposit
The operation electric current path of memory element, can reduce the operation resistance of memory component.In addition provided by the embodiment of the present invention
Memory component can't share the doped region for being formed in source electrode line and having p-n junction in bottom, can avoid the formation of parasitic capacitance,
The operation reliability of memory component can be promoted, solve known technology problem encountered.
Detailed description of the invention
In order to be clearer and more comprehensible to the above embodiment of the present invention and other objects, features and advantages, spy lift it is several compared with
Good embodiment, and cooperate institute's accompanying drawings, it is described in detail below:
Figure 1A to Fig. 1 J is a series of technique knot of production memory components depicted in an embodiment according to the present invention
Structure diagrammatic cross-section；
Fig. 2A to Fig. 2 G is a series of technique of production memory components depicted according to another embodiment of the present invention
Structural profile illustration；And
Fig. 3 A to Fig. 3 G is a series of production vertical channel floating grids depicted according to still another embodiment of the invention
The process structure diagrammatic cross-section of nand flash memory element.
[symbol description]
100,200,300: memory component 101: semiconductor substrate
102,202: 103: the first conductor layer of separation layer
The top surface 204,104 of 103a: the first conductor layer: contact plunger
204a, 104a: 105: the second conductive layer of top surface of contact plunger
107,307: accumulation layer 108: channel layer
109: insulating materials 110: multi-layer laminate structure
110a, 110b: first through opening 111-115: sacrificial layer
111a: the bottom surface 121-126: insulating layer of sacrificial layer
129: clearance wall dielectric layer 130: the air gap
131: weld pad 132: coating
133: the second through opening 134: metal plug
136: bit line 137: storage unit
139: interior online 203: contact openings
301: 302: the first alcove of protective layer
303: interval 304: floating gate electrode
305: tunnel oxide C: electric current
Specific embodiment
The present invention is to provide a kind of semiconductor element and preparation method thereof, and it is inclined can to improve known semiconductor element contact resistance
High problem.In order to be clearer and more comprehensible to the above embodiment of the present invention and other objects, features and advantages, it is cited below particularly one
In-line memory element with memory cell, logic unit and high voltage unit and preparation method thereof is as preferably implementation
Example, and institute's accompanying drawings is cooperated to elaborate.
But it must be noted that these specific case study on implementation and method, be not intended to limit the invention.The present invention still may be used
It is implemented using other features, element, method and parameter.The it is proposed of preferred embodiment is only of the invention to illustrate
Technical characteristic, the claim being not intended to limit the invention.Have usually intellectual in the technical field, it can basis
The description of following description is not departing from scope of the invention, makees impartial modification and variation.Different embodiments with
Among schema, identical element will be indicated with identical component symbol.
Figure 1A to Fig. 1 J is please referred to, Figure 1A to Fig. 1 J is that a series of production depicted in an embodiment according to the present invention are deposited
The process structure diagrammatic cross-section of memory element 100.Among the present embodiment, memory component 100 is a kind of vertical channel
Nand flash memory element.The method of production memory component 100 includes the following steps:
Firstly, forming the first conductor layer 103 on separation layer 102 in forming separation layer 102 on semiconductor substrate 101；
And a multi-layer laminate structure 110 is provided in the first conductor layer 103 (as depicted in Figure 1A).In some embodiments of the present invention
In, semiconductor layer substrate 101 can be by, such as p-type doping, n-type doping or undoped polysilicon, germanium or other suitable half
Conductor material, is constituted.Separation layer 102 can be by dielectric material, such as Si oxide (oxide), silicon nitride, silicon nitrogen oxidation
Object (oxynitride), silicate (silicate) or above-mentioned any combination, are constituted.First conductor layer 103 is by conduction
Material, for example, can polysilicon (poly-silicon), doping semiconductor material, metal or above-mentioned any combination, constituted.
Among the present embodiment, semiconductor substrate 101 is made of the polysilicon of p-type doping；Separation layer 102 is by Si oxide institute
It constitutes；First conductor layer 103 is made of the polysilicon of n-type doping.
Multi-layer laminate structure 110 include multiple sacrificial layer 111-115 for being formed in the first conductor layer 103 and it is multiple absolutely
Edge layer 121-126.Insulating layer 121-126 is to be parallel to each other, and fold along Z-direction is interlaced with each other with sacrificial layer 111-115
Layer is in the first conductor layer 103.Among the present embodiment, insulating layer 126 is located at the top layer of multi-layer laminate structure 110, insulation
Layer 121 is located at the bottom of multi-layer laminate structure 110, and directly contacts with the first conductor layer 103, and using makes sacrificial layer 111-
115 and first conductor layer 103 be isolated.In some embodiments of the invention, the thickness of separation layer 102 is preferably than insulating layer 121-
126 thickness is big.Separation layer 102 thickness essence between 200 angstroms (Angstrom,) between 1500 angstroms.Preferably 500
Angstrom.
Sacrificial layer 111-115 can be by (nitride) containing silicon nitride, such as silicon nitride (SiN), silicon oxynitride
(SiON), fire sand (SiCN) or above-mentioned any combination, are constituted.In the present embodiment, sacrificial layer 111-115 is by nitrogen
SiClx is constituted.Insulating layer 121-126 can be by dielectric material, such as Si oxide, silicon nitride, silicon nitrogen oxides, silicic acid
Salt or above-mentioned any combination, are constituted.In some embodiments of the invention, sacrificial layer 111-115 and insulating layer 121-126
It can be by, for example, low-pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) work
Skill is made.Wherein, the material of sacrificial layer 111-115 and insulating layer 121-126 must be different.
Then, technique is performed etching to multi-layer laminate structure 110, runs through opening 110a and 110b to form multiple first,
Through multi-layer laminate structure 110, the first conductor layer 103 and separation layer 102, uses and be exposed to the substrate 101 of a part outside
(as depicted in Figure 1B).In some embodiments of the invention, the first etching technics through opening 110a and 110b, packet are formed
It includes with patterning hard mask layer (not being painted) as etching mask, passes through anisotropic etching technics (anisotropic etching
Process), such as reactive ion etching (Reactive Ion Etching, RIE) technique, to multi-layer laminate structure 110,
One conductor layer 103 and separation layer 102 perform etching.It uses in multi-layer laminate structure 110, the first conductor layer 103 and separation layer 102
Among formed and extended downwardly along Z-direction, and cross sectional shape be substantially circular through hole (first through opening 110a and
110b), first a part of substrate 101 through the bottom surface of opening 110a and 110b will be located at, and is used as first and runs through
A part of insulating layer 121-126, sacrificial layer 111-115, the first conductor layer 103 and the separation layer of the side wall of opening 110a and 110b
102 are exposed.
Later, be selectively deposited (selective deposition) technique, in first through opening 110a and
Contact plunger 104 is formed on the bottom 110b, (as depicted in Fig. 1 C) in electrical contact with the first conductor layer 103 and semiconductor substrate 101.
Among one embodiment of the invention, contact plunger 104 be can be through atomic layer chemical vapor deposition (Atomic Layer
Chemical Vapor Deposition, ALCVD) technique is formed by polysilicon contact plug, or it is outer via selectivity
Prolong growth (Selective Epitaxial Growth, SEG) and is formed by monocrystalline or polysilicon layer or above-mentioned any combination.
In addition, being connect first after the opening bottom 110a and 110b formation contact plunger 104 in order to eliminate to be formed in
The bubble (void) in plug 104 is touched, preferably will do it a thermal annealing (anneal) technique.After thermal annealing (anneal) technique
If contact plunger 104 there is a phenomenon where tightening, can also carry out selective deposition technique above-mentioned into one, be inserted with supplying contact
The height of plug 104.In the present embodiment, the height of contact plunger 104, half is started by the bottom surface of conductor substrate 101, is preferably exceeded
In the first conductor layer 103 and it is lower than sacrificial layer 111-115 (but not limited to this).In detail, among the present embodiment, contact is inserted
The top surface 104a of plug 104 is substantially higher than the top surface 103a of the first conductor layer 103, but the top surface 104a of contact plunger 104 is substantially low
In the bottom surface 111a of the sacrificial layer 111 of the bottom.
Then, accumulation layer 107 and channel layer 108 are sequentially formed on the side wall of opening 110a and 110b in first, and
Accumulation layer 107 is located between channel layer 108 and a little sacrificial layer 111-115, and makes channel layer 108 and contact plunger 104
Top surface 104a (as depicted in Fig. 1 D) in electrical contact.In some implementations of the invention, the formation of accumulation layer 107 includes following steps
It is rapid: to have first by depositing operation, such as low-pressure chemical vapor deposition process, formation, such as silicon oxide-silicon nitride-oxidation
Silicon (Oxide-Nitride-Oxide, ONO), oxide-nitride-oxide-silicon-nitride and silicon oxide (Oxide-Nitride-
Oxide-Nitride-Oxide, ONONO) or oxide-nitride-oxide-silicon-nitride and silicon oxide-silicon-nitride and silicon oxide
(Oxide-Nitride-Oxide-Nitride-Oxide-Nitride-Oxide, ONONONO) structure composite layer (but not with
This is limited), conformal blanket is overlying on surface and the first side wall and bottom through opening 110a and 110b of multi-layer laminate structure 110
Portion.Later, a part of silicon oxide-silicon nitride-oxygen for being located at first through the opening bottom 110a and 110b is removed with etching technics
SiClx, oxide-nitride-oxide-silicon-nitride and silicon oxide or oxide-nitride-oxide-silicon-nitride and silicon oxide-
A part of top surface 104a of contact plunger 104 is exposed to outer by silicon nitride-silicon oxide silicon structure.
It forms accumulation layer 107 and then by depositing operation, such as low-pressure chemical vapor deposition process, is formed by silicon, germanium
Other doping or undoped semiconductor material, the channel layer 108 constituted, make its conformal blanket be overlying on accumulation layer 107 and
Contact plunger 104 is exposed on outer top surface 104a.In the present embodiment, channel layer 108 is by undoped polysilicon structure
At.
Again with insulating materials 109, such as silica, silicon nitride or other suitable dielectric materials, filling first runs through
Be open 110a and 110b, and forms an at least the air gap (air gap) 130 in opening 110a and 110b first.?
It is etched back after insulating materials 109, forms weld pad 131 above insulating materials 109, and form coating 132 to cover multilayer
Laminated construction 110 and weld pad 131 (as depicted in Fig. 1 E).In one embodiment of this invention, coating 132 is aoxidized including silicon
Object.
Later, carry out another etching technics, formed in multi-layer laminate structure 110 at least one along Z-direction to
Lower extension, through multi-layer laminate structure 110 second through opening 133, and by insulating layer 121-126 and sacrificial layer 111-115
And first the top surface 103a of conductor layer 103 be partially exposed to outer (as depicted in Fig. 1 F).
Then, remaining sacrificial layer 111-115 is removed.It is using phosphoric acid (H among the present embodiment3PO4) solution passes through
Second is removed remaining sacrificial layer 111-115 through opening 133, and the accumulation layer 107 of a part is exposed to outside.
(as depicted in Fig. 1 G).In some embodiments of the invention, outer the is exposed to through opening 133 via second in order to protect
One conductor layer 103 can be preferably exposed on outer top surface 103a before removing sacrificial layer 111-115 in the first conductor layer 103
Form a protective layer 128.In the present embodiment, the Si oxide hard mask layer of protective layer 128 is by the first conductor
Layer 103 is exposed to the oxidation technology carried out on outer top surface 103a and is formed, and can be used to protect the first conductor in the subsequent process
Layer 103.
Later, by depositing operation, such as low-pressure chemical vapor deposition process, multiple second conductive layers 105 is formed and are filled
In on the original position removed remaining sacrificial layer 111-115, and then in each second conductive layer 105 and accumulation layer 107
A storage unit 137 is formed with the region that channel layer 108 is overlapped, and forms memory array in multi-layer laminate structure 110
(as depicted in Fig. 1 H).In some embodiments of the invention, the second conductive layer 105 can be by polysilicon, metal or other
Conductive material is constituted.Among the present embodiment, the second conductive layer 105 of control be a metal layer, such as titanium nitride/tungsten (TiN/W),
Tantalum nitride/tungsten (TaN/W), tantalum nitride/copper (TaN/Cu) and other possible materials.
After forming the second conductive layer 105, protective layer 128 is first removed；Then at second through opening 133 at least one
Clearance wall dielectric layer (dielectric spacer) 129 is formed on side wall, and is formed metal in opening 133 in second and inserted
Plug 134, it is in electrical contact with the first conductor layer 103, and electrically isolated by the clearance wall dielectric layer 129 with the second conductor layer 105
(as depicted in Fig. 1 I).
It is subsequent, interlayer dielectric layer 135 is formed above coating 132；Multiple positions are formed on interlayer dielectric layer 135
Line 136 keeps bit line 136 in electrical contact with weld pad 131 via interior online 139.Later, it (is not drawn via a succession of last part technology
Show), complete the preparation of memory component 100 (as depicted in Fig. 1 J).In some embodiments of the invention, the first conductor layer
Share source electrode line in 103 bottoms that can be used as memory component 100.And be located at memory array in by the second conductor layer 105 with deposit
Reservoir 107 and channel layer 108 are formed by storage unit 137, can be coupled to decoder, such as line decoder via bit line 136
Or column decoder or (not being painted).
Since the electric current C from bit line 136 can pass through channel layer 108, contact plunger 104,103 (bottom of the first conductor layer
Share source electrode line in portion) and metal plug 134 and be grounded.In other words, for be read out/electric current of write operation can't flow
By substrate 101.Compared with known technology, not only current path shortens, and will not the first conductor layer 103 and substrate 101 it
Between formed have p-n junction doped region, can avoid parasitic capacitance formation, can be greatly reduced memory component 100 operation electricity
Resistance, and solve known technology because bottom share between source electrode line and substrate generate parasitic capacitance caused by signal interference with
And time delay issue, and then promote the operation reliability and element speeds of memory component.
A to Fig. 2 G referring to figure 2., Fig. 2A to Fig. 2 G are a series of production depicted according to another embodiment of the present invention
The process structure diagrammatic cross-section of memory component 200.Among the present embodiment, memory component 200 is also a kind of with vertical
The nand flash memory element of straight channel.The method of production memory component 200 includes the following steps:
Firstly, sequentially in forming the first separation layer 102, the first conductor layer 103 and the second separation layer on semiconductor substrate 101
202.Multiple contact openings 203 are re-formed, the second separation layer 202, the first conductor layer 103 and the first separation layer 103 are passed through, it will
The substrate 101 of a part is exposed to outer.Later, it is respectively formed contact plunger 204 in contact openings, makes itself and the first conductor layer
103 and semiconductor substrate 101 it is (as depicted in Fig. 2A) in electrical contact.
Among some embodiments of the present invention, forms contact plunger 204 and include the following steps: firstly, with etching technics
Second separation layer 202, the first conductor layer 103 and the first separation layer 103 of a part are removed to form contact openings 203.Again
With depositing operation, such as low-pressure chemical vapor deposition process, conductive material, such as polysilicon are deposited on the second separation layer 202,
And fill contact openings 203.And then with the second separation layer 202 be stop-layer, carry out flatening process, such as chemical machinery
It polishes (Chemical Mechanical Polish, CMP), to remove the conductive material being located on the second separation layer 202, is formed
Contact plunger 204.In other words, the top surface 204a of contact plunger 204 is substantially higher than the top of the first conductor layer 103 in the present embodiment
Face 103a, and essence is coplanar with the top surface 202a of the second separation layer 202.
Then, a multi-layer laminate structure 110 is provided, makes multi-layer laminate structure that there are multiple insulating layer 121-126 and multiple
Sacrificial layer 111-115 is mutually stacked on the second separation layer 202.Then, multiple first are formed through opening with etching technics
110a and 110b passes through multi-layer laminate structure 110, and the contact plunger 204 of a part is exposed to outside.(as Fig. 2 B is drawn
Show).In order to allow first to be accurately aimed at contact plunger 204 through opening 110a and 110b, in some embodiments of the present invention
In, the size of contact plunger 204 can preferably be greater than first through the section of opening 110a and 110b, be run through with increasing production first
The process margin (process windows) of the etching technics of opening 110a and 110b.
Then.Accumulation layer 107 is sequentially formed at least one side wall of opening 110a and 110b then at first and is led to
Channel layer 108 is located in accumulation layer 107 between channel layer 108 and sacrificial layer 111-115, and make channel layer 107 with contact insert
Fill in 204 (as depicted in Fig. 2 C) in electrical contact.
Again with insulating materials 109, such as silica, silicon nitride or other suitable dielectric materials, filling first runs through
Be open 110a and 110b, and forms an at least the air gap 130 in opening 110a and 110b first.In eatch-back insulation material
After material 109, weld pad 131 is formed above insulating materials 109, and form coating 132 to cover multi-layer laminate structure 110
And weld pad 131 (as depicted in Fig. 2 D).
Another etching technics is carried out, forms at least one in multi-layer laminate structure 110 along Z-direction to downward
It stretches, across multi-layer laminate structure 110 and the second separation layer 202 second through opening 133, and by insulating layer 121-126 and sacrificial
The domestic animal layer 111-115 and top surface 103a of the first conductor layer 103 is partially exposed to outer.Some embodiments of the present invention it
In, it can be provided on the top surface 103a outside the first conductor layer 103 be exposed to and protective layer 128 is formed by by oxidation technology,
For protecting the first conductor layer 103 in the subsequent process (as depicted in Fig. 2 E).
Then, remaining sacrificial layer 111-115 is removed, and the accumulation layer 107 of a part is exposed to outside.Later, pass through
Depositing operation, such as low-pressure chemical vapor deposition process form multiple second conductive layers 105 and are filled in removed remaining sacrifice
On layer 111-115 original position, and then the area Chong Die with accumulation layer 107 and channel layer 108 in each the second conductive layer 105
Domain forms a storage unit 137, and forms memory array in multi-layer laminate structure (as depicted in Fig. 2 F).
After forming the second conductive layer 105, clearance wall dielectric layer 129 and metal are formed in opening 133 in second
Plug 134 keeps metal plug 134 and the first conductor layer 103 in electrical contact, and metal plug 134 is made to pass through clearance wall dielectric layer
129 electrically isolate with the second conductor layer 105.It is subsequent, interlayer dielectric layer 135 is formed above coating 132；Then at interlayer dielectric
Multiple bit lines 136 are formed on layer 135, keep bit line 136 in electrical contact with weld pad 131 via interior online 139.Later, via one
Consecutive last part technology (is not painted), completes the preparation of memory component 200 (as depicted in Fig. 2 G).
Among some embodiments of the present invention, memory component is also possible to a kind of vertical channel floating grid NAND sudden strain of a muscle
Deposit element.Such as A to Fig. 3 G referring to figure 3., Fig. 3 A to Fig. 3 G are depicted according to still another embodiment of the invention a series of
Make the process structure diagrammatic cross-section of vertical channel floating grid nand flash memory element 300.Among the present embodiment, production is deposited
The method of memory element 300 is substantially similar to method depicted in Figure 1A to Fig. 1 J, and difference is only that the side of production accumulation layer 307
Method is different.It is identical since the material and production method of other elements have been specified among the embodiment of Figure 1A to Fig. 1 J
Technique and no longer this is repeated.
Among the present embodiment, the production method of accumulation layer 307 is by Fig. 1 C.After forming contact plunger 104 first
Protective layer 301 is formed in the top 104a of contact plunger 104；An etch-back technics is carried out again, removes a part of sacrificial layer 111-
115, it uses and defines first alcove 302 in two neighboring insulating layer 121-126.Among the present embodiment, it is etched back work
Skill is using phosphoric acid (H3PO4) solution wet-etching technology, can be used to remove positioned at two adjacent insulating layer 121-126 it
Between via first be exposed to outer a part of sacrificial layer 111-115 through opening 110a and 110b.In other words, each is first recessed
Room 302 be by be left behind come a part of sacrificial layer 111-115, defined between two adjacent insulating layer 121-126
Interlayer space out (as depicted in Fig. 3 A).
Oxidation technology is carried out again, each sacrificial layer 111-115 is exposed to outer part by the first alcove 302 and is subject to oxygen
Change, to form wall 303.It in other words, is the formation wall 303 on the longitudinal side wall of the first alcove 302.In this reality
The step of applying among example, aoxidizing sacrificial layer 111-115 include steam in situ generate (In-Situ-Steam-Generation,
A part of sacrificial layer 111-115 that material is silicon nitride can be oxidized to material and be substantially Si oxide by ISSG) oxidation technology
Wall 303 (as depicted in Fig. 3 B).
It is subsequent, it forms multiple floating gate electrodes 304 and fills each first alcove 302 respectively (as depicted in Fig. 3 C).It is floating
The generation type for setting gate electrode 304 includes the following steps: firstly, carry out depositing operation, such as low-pressure chemical vapor deposition process,
Conductive material (not being painted) is deposited on multi-layer laminate structure 110 and fills first through opening 110a and 110b and the first alcove
302.It is removed again by etch-back technics and is located at first a part of conductive material in opening 110a and 110b, and retained and be located at
A part of conductive material in first alcove 302 is substantially cricoid floating gate electrode 304 to be formed.Of the invention some
In embodiment, the conductive material of floating gate electrode 304 can be polysilicon or metal, for example, aluminium (Al), copper (Cu), golden (Au),
Silver-colored (Ag), platinum (Pt) or above-mentioned alloy.
After forming floating gate electrode 304, it is initially formed tunnel oxide (tunnel oxide layer) 305, is covered
It is exposed on outer part via first through opening 110a and 110b in insulating layer 121-126 and floating gate electrode 304.So
Afterwards, channel layer 108 is re-formed, making it, conformally (conformal) blanket is overlying on tunnel oxide 305 and contact plunger 104 passes through
It is exposed on outer top surface 104a (as depicted in Fig. 3 D) as first through opening 110a and 110b.
In the present embodiment, the production method of tunnel oxide 305 includes the following steps: firstly, by depositing operation shape
At silicon oxide layer, make its blanket be overlying on multi-layer laminate structure 110 surface and first through opening 110a and 110b side wall
On upper and bottom surface.And then a part being located on multi-layer laminate structure 110 and protective layer 301 is removed by etching technics
Silicon oxide layer is used to form tunnel oxide 305.In some embodiments of the invention, same etching work can preferably be passed through
Skill removes protective layer 301 together, is exposed to a part of contact plunger 104 outer.Channel layer 108 is by depositing operation shape
It is overlying on the first polysilicon layer on the side wall and bottom surface of opening 110a and 110b at blanket, 305 sandwiched of oxide layer can be tunneled through
Between channel layer 108 and floating gate electrode 304, and keep channel layer 108 and contact plunger 104 in electrical contact.
And then with insulating materials 109, such as silica, silicon nitride or other suitable dielectric materials, filling first
An at least the air gap 130 is formed in opening 110a and 110b through opening 110a and 110b, and first.It is exhausted in eatch-back
After edge material 109, weld pad 131 is formed above insulating materials 109, and form coating 132 to cover multilayer laminated knot
Structure 110 and weld pad 131.Another etching technics is carried out again, at least one is formed in multi-layer laminate structure 110 along Z axis
Direction extends downwardly, across multi-layer laminate structure 110 second through opening 133, and by insulating layer 121-126 and sacrificial layer
The 111-115 and top surface 103a of the first conductor layer 103 is partially exposed to outer (as depicted in Fig. 3 E).
Then, remaining sacrificial layer 111-115 is removed, and the wall 303 of a part is exposed to outside.Later, pass through
Depositing operation, such as low-pressure chemical vapor deposition process form multiple second conductive layers 105 and are filled in removed remaining sacrifice
On layer 111-115 original position.It in turn, can be in the second conductive layer 105, wall 303, floating gate electrode 304, tunnel oxide
The region that layer 107 and channel layer 108 are overlapped forms multiple vertical channel floating gate memory cells 306, and in multi-layer laminate structure structure
It is middle to form the floating gate memory array (as depicted in Fig. 3 F) with vertical channel.In the present embodiment, each vertical channel
The second conductive layer 105 in floating gate memory cell 306 can be used as control grid electrode；Wall 303, corresponding floating gate electrode
304 and the combination of 305 three of tunnel oxide can be considered the accumulation layer of vertical channel floating gate memory cell 306.Wherein, each
Wall 303 can be used as the grid interbed between corresponding control grid electrode (the second conductive layer 105) and floating gate electrode 304
(Inter-Poly Dielectric layer, IPD layer).
After forming the second conductive layer 105, metal plug 134 is formed in opening 133 in second, with the first conductor
Layer 103 is in electrical contact, and is electrically isolated by the clearance wall dielectric layer 129 with the second conductor layer 105.It is subsequent, then connect via one
It goes here and there last part technology (not being painted), forms interlayer dielectric layer 135 above coating 132；It is formed on interlayer dielectric layer 135 more
A bit line 136, and it is in electrical contact with weld pad 131 via interior online 139, the preparation of memory component 300 is completed (such as Fig. 3 G institute
It is painted).
According to above-described embodiment, the present invention is to provide a kind of three-dimensional storage element and preparation method thereof.It is half
A separation layer and a conductor layer are sequentially formed above conductor substrate, and forms at least one across separation layer and conductive layer and with half
The contact plunger of conductor and conductive layer electrical property.And the multi-layer laminate structure with multiple storage units is formed in conductor layer, with
And it is multiple be used to concatenate storage unit to form the serial channel layer of multiple storage units longitudinally through multi-layer laminate structure, and make
Each channel layer generates in electrical contact with a corresponding contact plunger.Wherein, the distance between conductor layer and channel layer are small
In the distance between semiconductor substrate and channel layer.
Due to, memory component provided by the embodiment of the present invention be using independent conductor layer, rather than it is semiconductor-based
Material shares source electrode line as the serial bottom of different storage units.Therefore it is used to the electric current into read/write operations, stream
It is shorter than the current path that memory component provided by known technology flows through semiconductor substrate through conductor layer path, therefore deposit
The operation electric current path of memory element, can reduce the operation resistance of memory component.In addition provided by the embodiment of the present invention
Memory component can't share the doped region for being formed between source electrode line and substrate and having p-n junction in bottom, can avoid parasitic electricity
The formation of appearance, and then the operation reliability and element speeds of memory component can be promoted, what solution known technology was faced asks
Topic.
Although the present invention has been disclosed as a preferred embodiment, however, it is not to limit the invention, any technology neck
Have usually intellectual in domain, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, therefore this
Subject to the protection scope of invention ought be defined depending on appended claims range.
Claims (10)
1. a kind of memory component, comprising:
Semiconductor substrate；
One separation layer is located on the semiconductor substrate；
One first conductor layer is located on the separation layer；
One contact plunger passes through the separation layer and in electrical contact with first conductor layer and the semiconductor substrate；
Multiple insulating layers are located in first conductor layer；
Multiple second conductor layers, and these insulating layer cross laminates, and electrically isolated with first conductor layer；
One channel layer, positioned at one first in at least one side wall of opening and a bottom surface, and it is in electrical contact with the contact plunger,
Wherein this first through opening across these insulating layers and these second conductor layers, and by the contact plunger be exposed to outside；And
One accumulation layer, between the channel layer and these second conductor layers.
2. memory component according to claim 1, wherein the accumulation layer includes:
One tunnel oxide, between second conductor layer and the channel layer；
Multiple floating gate electrodes are located between these each second conductor layers and the tunnel oxide；And
Multiple gate spacing layers are located between each floating gate electrode one corresponding with these the second conductor layers.
3. memory component according to claim 1, wherein the accumulation layer includes silicon monoxide-silicon-nitride and silicon oxide knot
Structure, and it is located at this first on the side wall of opening, and it is located between the accumulation layer and these second conductor layers.
4. memory component according to claim 1, further includes:
One clearance wall dielectric layer, positioned at one second through opening at least one side wall on, wherein this second through opening across this
First conductor layer is exposed to outer by a little insulating layers and these second conductor layers；And
One metal plug, be located at this second through opening in, it is in electrical contact with first conductor layer, and pass through the clearance wall dielectric
Layer is electrically isolated with these second conductor layers；And the contact plunger has the top surface for being substantially higher than first conductor layer.
5. a kind of production method of memory component, comprising:
In forming a separation layer on semiconductor substrate；
In one first conductor layer of formation on the separation layer；
One multi-layer laminate structure is provided, makes the multi-layer laminate structure that there are multiple insulating layers and multiple sacrificial layers to be mutually stacked on this
In first conductor layer, and these sacrificial layers and first conductor layer are isolated；
At least one first is formed through opening, the multi-layer laminate structure, first conductor layer and the separation layer are passed through, by these
Insulating layer, these sacrificial layers and the semiconductor substrate are partially exposed to outer；
A selective deposition technique is carried out, first to form a contact plunger through bottom for opening in this, first is led with this
Body layer and the semiconductor substrate are in electrical contact；
In sequentially forming an accumulation layer and a channel layer in the first at least one side wall for running through opening, it is located in the accumulation layer
Between the channel layer and these remaining sacrificial layers, and keep the channel layer and the contact plunger in electrical contact；
At least one second is formed through opening, passes through the multi-layer laminate structure, make first conductor layer, these insulating layers and is remained
These remaining sacrificial layers are partially exposed to outer；
By this second remaining these sacrificial layers are removed through opening；And
In on the position of these remaining sacrificial layers, multiple second conductive layers are formed.
6. the production method of memory component according to claim 5, wherein the step of forming the accumulation layer includes:
First these a part of sacrificial layers are removed through opening by this, uses and define multiple first between these insulating layers
Alcove；
It aoxidizes these each sacrificial layers and is exposed to outer a part, to form a wall in these each first alcoves；
Multiple floating gate electrodes are formed, fill these each first alcoves respectively；And
A tunnel oxide is formed, these insulating layers and these floating gate electrodes is covered in and first is exposed to through opening via this
On outer part.
7. the production method of memory component according to claim 5, wherein being included in the step of forming the accumulation layer
This first through opening the side wall on formed silicon monoxide-silicon nitride-silicon oxide silicon structure.
8. a kind of production method of memory component, comprising:
In sequentially forming one first separation layer, one first conductor layer and one second separation layer on semiconductor substrate；
An at least contact openings are formed, second separation layer, first conductor layer and the separation layer are passed through, by being somebody's turn to do for a part
Semiconductor substrate is exposed to outer；
A contact plunger is formed in the contact openings, it is in electrical contact with first conductor layer and the semiconductor substrate；
One multi-layer laminate structure is provided, makes the multi-layer laminate structure that there are multiple insulating layers and multiple sacrificial layers to be mutually stacked on this
On second separation layer；
At least one first is formed through opening, passes through the multi-layer laminate structure and second separation layer, and these are insulated
Layer, these sacrificial layers and the contact plunger are partially exposed to outer；
In sequentially forming an accumulation layer and a channel layer in the first at least one side wall for running through opening, it is located in the accumulation layer
Between the channel layer and these remaining sacrificial layers, and keep the channel layer and the contact plunger in electrical contact；
At least one second is formed through opening, passes through the multi-layer laminate structure and second separation layer, make first conductor layer, this
A little insulating layers and these remaining sacrificial layers are partially exposed to outer；
By this second remaining these sacrificial layers are removed through opening；And
In forming multiple second conductive layers on the position of these remaining sacrificial layers.
9. the production method of memory component according to claim 8, wherein the step of forming the accumulation layer includes:
First these a part of sacrificial layers are removed through opening by this, uses and define multiple first between these insulating layers
Alcove；
It aoxidizes these each sacrificial layers and is exposed to outer a part, to form a wall in these each first alcoves；
Multiple floating gate electrodes are formed, fill these each first alcoves respectively；And
A tunnel oxide is formed, these insulating layers and these floating gate electrodes is covered in and first is exposed to through opening via this
On outer part.
10. the production method of memory component according to claim 8, wherein the step of forming the accumulation layer, including
In formation silicon monoxide-silicon nitride-silicon oxide silicon structure on first side wall for running through opening.
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Families Citing this family (13)
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| CN106409837B (en) * | 2015-07-27 | 2020-03-17 | 旺宏电子股份有限公司 | Memory and manufacturing method thereof |
| US10373904B2 (en) | 2017-08-28 | 2019-08-06 | Micron Technology, Inc. | Semiconductor devices including capacitors, related electronic systems, and related methods |
| US10685914B2 (en) | 2017-08-31 | 2020-06-16 | SK Hynix Inc. | Semiconductor device and manufacturing method thereof |
| CN107863346B (en) * | 2017-11-09 | 2019-02-22 | 长江存储科技有限责任公司 | A kind of NAND string structure and preparation method thereof |
| CN107946310B (en) * | 2017-11-16 | 2021-01-01 | 长江存储科技有限责任公司 | 3D NAND flash memory preparation method adopting air gap as dielectric layer and flash memory |
| CN109860198B (en) * | 2017-11-30 | 2021-01-05 | 旺宏电子股份有限公司 | Memory element and manufacturing method thereof |
| TWI669805B (en) * | 2018-01-04 | 2019-08-21 | 力晶積成電子製造股份有限公司 | Non-volatile memory structure and manufacturing method thereof |
| EP3830872A4 (en) | 2018-10-23 | 2022-03-16 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device having semiconductor plug formed using backside substrate thinning |
| US10930669B2 (en) * | 2019-02-12 | 2021-02-23 | Macronix International Co., Ltd. | Three dimensional memory device and method for fabricating the same |
| KR20200118705A (en) * | 2019-04-08 | 2020-10-16 | 에스케이하이닉스 주식회사 | Electronic device and method for fabricating the same |
| EP3931868A4 (en) * | 2019-04-12 | 2023-01-04 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device with deposited semiconductor plugs and methods for forming the same |
| US11211287B2 (en) * | 2019-07-22 | 2021-12-28 | Nanya Technology Corporation | Semiconductor device and method for fabricating the same |
| JP2021136346A (en) * | 2020-02-27 | 2021-09-13 | キオクシア株式会社 | Semiconductor storage device and method for manufacturing the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6706594B2 (en) * | 2001-07-13 | 2004-03-16 | Micron Technology, Inc. | Optimized flash memory cell |
| CN1917185A (en) * | 2005-08-15 | 2007-02-21 | 力晶半导体股份有限公司 | Frash memory, and manufacturing method |
| CN101241927A (en) * | 2008-03-13 | 2008-08-13 | 复旦大学 | A resistance memory based on diode selection and its making method |
| CN101685820A (en) * | 2008-09-23 | 2010-03-31 | 力晶半导体股份有限公司 | Semiconductor element, memory element and manufacture method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100398037B1 (en) * | 2000-12-05 | 2003-09-19 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory |
-
2015
- 2015-07-23 CN CN201510437235.1A patent/CN107039443B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6706594B2 (en) * | 2001-07-13 | 2004-03-16 | Micron Technology, Inc. | Optimized flash memory cell |
| CN1917185A (en) * | 2005-08-15 | 2007-02-21 | 力晶半导体股份有限公司 | Frash memory, and manufacturing method |
| CN101241927A (en) * | 2008-03-13 | 2008-08-13 | 复旦大学 | A resistance memory based on diode selection and its making method |
| CN101685820A (en) * | 2008-09-23 | 2010-03-31 | 力晶半导体股份有限公司 | Semiconductor element, memory element and manufacture method thereof |
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