CN107039248A - The method for forming the SiC grooves with improved Step Coverage - Google Patents
The method for forming the SiC grooves with improved Step Coverage Download PDFInfo
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- CN107039248A CN107039248A CN201610847669.3A CN201610847669A CN107039248A CN 107039248 A CN107039248 A CN 107039248A CN 201610847669 A CN201610847669 A CN 201610847669A CN 107039248 A CN107039248 A CN 107039248A
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- groove
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- 238000000034 method Methods 0.000 title claims abstract description 45
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 41
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 41
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 41
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 41
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 41
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 15
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 13
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 description 20
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 17
- 230000008021 deposition Effects 0.000 description 15
- 238000010586 diagram Methods 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 7
- 239000007789 gas Substances 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- -1 Nitrogen ion Chemical class 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical compound [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- XZWYZXLIPXDOLR-UHFFFAOYSA-N metformin Chemical compound CN(C)C(=N)NC(N)=N XZWYZXLIPXDOLR-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0475—Changing the shape of the semiconductor body, e.g. forming recesses
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Inorganic Chemistry (AREA)
Abstract
According to an aspect of the present invention, a kind of method for the groove for forming the SiC power semiconductors with improved Step Coverage, including：By forming the second concentration layer injecting the first foreign ion on the epitaxial layer that is formed on high concentration semiconductor substrate layer；SiO is formed on second concentration layer2Layer；In the SiO2PR mask patterns are formed on layer, the PR mask patterns have the pattern that the formation for groove is designed；Using the PR mask patterns by etching the SiO2Layer forms SiO2Mask pattern；Remove the etching SiO2The PR mask patterns remained after layer；With the utilization SiO2Mask pattern includes the epitaxial layer of second concentration layer by dry etching and forms the groove.
Description
Technical field
The present invention relates to a kind of method for forming the groove with improved Step Coverage.
Background technology
Groove is usually formed to increase the cellar area of power semiconductor and reduce impedance.
Fig. 1 and Fig. 2 are the sectional views for illustrating the conventional method for forming groove on the surface of the semiconductor substrate.
Fig. 1 shows to form the hard mask pattern for forming groove on traditional epitaxial layer.
Reference picture 1, first, is formed for forming the hard of groove on the epitaxial layer 112 being formed in SiC substrate 111
Doped with the impurity of high concentration in mask pattern 113-1, its epitaxial layers 112.
Then, perform dry etching by using hard mask pattern 113-1 and form groove 120 so that epitaxial layer 112 has
There is desired depth.
Fig. 2 shows the groove 120 formed after dry etching.
After forming the trench 120, the hard mask pattern 113-2 remained after dry etching is removed, according to the purposes of groove,
Deposit the SiO of predetermined thickness2Or metal.
Reference picture 2, with energetic etch gas is introduced from hard mask pattern 113-2 upper verticals, epitaxial layer 112 is etched
For with desired depth.
Here, during dry etching, some etching gas rebound and hit the side wall of vertical wall from bottom, because
This reason, the central region of vertical wall is more etched so that the thickness ratio vertical wall of the central region of vertical wall it is upper
The pattern in portion is small.
In addition, using traditional dry etching, the border of the top edge of the vertical wall of groove is formed as angular shape, led
Cause bad fillet.
Due to these phenomenons, when in subsequent technique by depositing SiO on the surfaces of the trench2Or metal and form deposition
During film, thickness deviation can be produced between channel bottom 126, the side wall 127 of vertical wall and the top surface of vertical wall, cause deposition
It is in uneven thickness.Therefore, it is not possible to keep deposition film that there is substantially uniform thickness.
Fig. 3 is the SiO for showing to deposit in the groove etched using conventional etch method2The sectional view of film.
As shown in figure 3, working as SiO is deposited in the groove of conventional etch2During film, mesa top 121-3 becomes to be swelled and turned into
It is spherical, and thickness deviation is produced between side wall 121-1 and bottom 121-2, so as to cause bad Step Coverage.
Accordingly, it would be desirable to a kind of method of the formation groove of Step Coverage that can improve in semiconductor fabrication process.
The background technology of the present invention is disclosed in KR published patent the 1999-0036556th.
Citation
Patent document
(patent document 1) KR published patent the 1999-0036556th (power semiconductor and its manufacture method)
The content of the invention
Technical problem
The present invention is intended to provide a kind of method for the groove for forming semiconductor, this method can form deposition in the trench
During film, reduce the thickness deviation of deposition film and improve integrated step covering.
The present invention is also directed to a kind of method of the groove of formation SiC power semiconductors, and this method can formed
During groove, narrow upper width and smooth fillet are formed.
The purpose of the present invention is not limited to above-mentioned purpose, will be become by following description other objects of the present invention
Obtain obviously.
Technical scheme
According to an aspect of the present invention, a kind of formation has the groove of the SiC power semiconductors of improved Step Coverage
Method includes：By forming the injecting the first foreign ion on the epitaxial layer that is formed on high concentration semiconductor substrate layer
Two concentration layers；SiO is formed on second concentration layer2Layer；In the SiO2PR mask patterns, the PR are formed on layer
Mask pattern has the pattern that the formation for groove is designed；The SiO is etched by using the PR mask patterns2Layer is formed
SiO2Mask pattern；Remove the etching SiO2The PR mask patterns remained after layer；With the utilization SiO2Mask pattern passes through
Dry etching includes the epitaxial layer of second concentration layer and forms the groove.
Second concentration layer is characterized by the impurity than the epitaxial layer higher concentration.
In addition, second concentration layer is characterised by being formed as about the 5% to 20% of the depth of the groove.
Second concentration layer is further characterized in that about the 8% of the depth for being formed as the groove.
The concentration of impurity in the epitaxial layer can be 3.0 × 1015Cm-3, the concentration of the impurity in second concentration layer
Can be 1 × 1020Cm-3。
The thickness of second concentration layer can be 0.2 μm, and the depth of the depression of the groove can be 2.5 μm.
In the step of forming the groove, the vertical wall of the groove be formed as it is thinning towards its upside, it is described to hang down
Part under the upper end of straight wall can be dug as with bottleneck shape.
First foreign ion can be Nitrogen ion.
Beneficial effect
According to an embodiment of the invention, have difference dense by being etched at the upper and lower part of groove to be formed
The SiC epitaxial layer of degree, the vertical wall of the groove is formed as, and the top rim of the vertical wall thinning towards its upside
The angular shape on boundary can be trimmed to about, and to form smooth fillet, and can improve the platform of the deposition film formed in the trench
Jump.
Using the method for the formation groove according to embodiment of the present invention, the vertical wall for making groove by etch process is formed
To be thinning and smooth fillet is formed towards its top, the vertical position based on deposition film is reduced in subsequent technique
The thickness deviation with horizontal level is put, so as to allow to form uniform deposition film in the trench.
Using the method for the formation groove according to embodiment of the present invention, make the vertical of groove in the technique of etching groove
It is thinning that wall is formed towards its top, thus the sunken inside of groove has upper wider shape.
In addition, dug at part under the upper end of the vertical wall of the groove as with bottleneck shape, and
The angular shape on the top edge border of the vertical wall can be trimmed to about, to allow in the upper end of the vertical wall of the groove
Place forms smooth fillet.
Brief description of the drawings
Fig. 1 and Fig. 2 are the sectional views for illustrating the conventional method for forming groove on the surface of the semiconductor substrate.
Fig. 3 is to be illustrated in the SiO deposited in the groove etched using conventional etch method2The sectional view of film.
Chip of Fig. 4 diagrams with the epitaxial layer formed on semiconductor-based flaggy.
Fig. 5 diagrams perform ion implanting by side on said epitaxial layer there and form the second concentration on said epitaxial layer there
Layer.
Fig. 6 is illustrated in cvd silicon oxide on second concentration layer.
Fig. 7 diagrams wherein utilize PR mask patterns formation SiO2The structure of hard mask pattern.
Fig. 8 is illustrated in form SiO2Removed after hard mask pattern and be formed at SiO2PR mask artworks on hard mask pattern
The section of case.
Fig. 9 diagrams utilize SiO2Hard mask pattern is including the SiC epitaxial layer of second concentration layer by etch process
The middle section for forming groove.
Figure 10 illustrates the utilization SiO according to embodiment of the present invention2Hard mask pattern is formed wherein by etch process
The image of fluted epitaxial layer.
The SiO that Figure 11 diagrams are remained after the etch process2The removed section of mask pattern.
Figure 12 is illustrated in the example that subsequent deposition process is performed in the groove formed according to embodiment of the present invention.
Figure 13 is illustrated in the oxide-film deposited on the groove formed according to embodiment of the present invention and PR mask patterns.
Embodiment
Due to there may be various deformations of the invention and embodiment, therefore illustrate with reference to the accompanying drawings and describe specific
Embodiment.However, this, which is not intended to, limits the invention to specific embodiment, but it is understood as including this hair
All deformations, equivalent and the substitute covered in bright technological thought and technical scope.
Hereinafter, some embodiments be will be described in detail with reference to the accompanying drawings.Identical or corresponding element will be endowed identical
Reference marker, and any unnecessary description of unrelated with accompanying drawing number and identical or corresponding element will not be repeated again.In this hair
In bright entire disclosure, when it is determined that for some related routine techniques description can depart from the present invention when putting, will save
The detailed description slightly closed.
Chip of Fig. 4 diagrams with the epitaxial layer formed on semiconductor-based flaggy.
Reference picture 4, forms the epitaxial layer 12 grown with epitaxy method on SiC substrate 11, is mixed in its epitaxial layers 12
The miscellaneous impurity for having a high concentration.
Fig. 5 to Figure 11 is formation SiC power with improved Step Coverage half of the diagram according to embodiment of the present invention
The sectional view of the method for the groove of conductor.
Fig. 5 shows to form the second concentration layer 30 on epitaxial layer 12 by performing ion implanting.
According to the preferred embodiment of the present invention, epitaxial layer 12 is formed as with 9.5 μm of thickness and 3.0 × 1015Cm-3
Doping concentration.
In an embodiment of the invention, in order that concentration corresponding with depth is different, by epitaxial layer 12 it
It is upper perform the first impurity ion implanting and the second concentration layer 30 is formed on epitaxial layer 12.
According to an embodiment of the invention, by perform ion implanting and on the whole upper surface of epitaxial layer 12 shape
Into the second concentration layer 30, produced in the second concentration layer 30 positioned at upside and between the epitaxial layer 12 of downside based on depth
Concentration difference.
Due to the concentration difference, when trenches are etched, the second concentration layer 30 with higher concentration is with faster etch-rate
It is etched, and the epitaxial layer 12 with relatively low concentration is etched with slower etch-rate.
Due to the concentration difference, the vertical wall of groove is thinning towards upside, and the depression of groove has preferable isosceles ladder
The shape of shape, and the angular shape on the top edge border of vertical wall is trimmed to about, to form smooth fillet.
According to embodiment, although the use for the semiconductor that the thickness of the second concentration layer 30 is applied according to the second concentration layer 30
Way and electrical characteristics and it is different, but as the result of various experiments, preferably the second concentration layer 30 is formed as the depth of groove
About the 5% to 20% of degree.
In above-mentioned preferred scope, the depression of groove can have the shape of preferred isosceles trapezoid, and vertical
The top edge boundary of wall forms smooth fillet.
In a preferred embodiment of the invention, the second concentration layer 30 is about the 8% of the depth of groove.
If the thickness of the second concentration layer 30 is much smaller than the 8% of epitaxial layer 12, it may hang down after the etch process
The top edge boundary of straight wall forms angular shape.
If in addition, the thickness of the second concentration layer 30 is much larger than the 8% of epitaxial layer 12, on the top of the vertical wall of groove
The bottleneck shape that place is formed may be elongated, and the space at the top being recessed may become too wide, make the width of vertical wall
Narrow.In this case, it may be necessary to increase overall chip size, so as to kept between groove rule interval.
In the ion implantation technology according to the preferred embodiment of the present invention, will have 1 × 1020Cm-3Concentration nitrogen
Injection is to form thickness as 0.2 μm of the second concentration layer 30.
That is, the concentration of impurity is 1 × 10 in the second concentration layer 3020Cm-3。
Here, the projected depth of the depression of groove is 2.5 μm.
In another embodiment of the present invention, when epitaxial layer 12 is p-type region, it can be noted in ion implantation technology
Enter aluminium ion.
After the second concentration layer 30 is formed, SiO is performed on the second concentration layer 302Layer depositing operation, with by heavy
Product SiO2Form SiO2Layer 15.
SiO2Layer 15 is used to form SiO2Hard mask pattern 15-1, the SiO2Hard mask pattern 15-1 is used to form groove,
Then it this will be described.
In an embodiment of the invention, by carrying out SiO2Chemical vapor deposition, utilize SiO2Layer depositing operation
Form SiO2Layer 15.
Next, in SiO2PR mask patterns 14 are formed on layer 15.
In an embodiment of the invention, following steps formation PR mask patterns 14 are passed through：In SiO2On layer 15
Photoresist is coated, the pattern thought the formation of groove and designed coats the SiO of photoresist using ultraviolet exposure2Layer 15, then
Make the SiO of coating photoresist using etchant2The exposed portion development of layer 15.
Next, partly etching SiO by using PR mask patterns 142Layer 15, forms SiO2Hard mask pattern 15-1.
Fig. 7 diagrams wherein form SiO using PR mask patterns 142Hard mask pattern 15-1 structure.
In an embodiment of the invention, etching gas CHF is utilized by inductively coupled plasma method3Or CF4
Partly etch SiO2Layer 15.
Forming SiO2After hard mask pattern 15-1, removal is formed at SiO2PR masks on hard mask pattern 15-1
Pattern 14.
Fig. 8 is illustrated in form SiO2Removed after hard mask pattern 15-1 and be formed at SiO2On hard mask pattern 15-1
The section of PR mask patterns 14.
Next, utilizing SiO2Hard mask pattern 15-1, by etching include the second concentration layer 30 epitaxial layer 12 and shape
Into groove 20.
Fig. 9 diagrams utilize SiO2Hard mask pattern 15-1, is including the SiC extensions of the second concentration layer 30 by etch process
The section of groove 20 is formed in layer 12.
Figure 10 illustrates the utilization SiO according to embodiment of the present invention2Hard mask pattern is formed wherein by etch process
The image of fluted epitaxial layer 12.
In an embodiment of the invention, etching gas is utilized by transformer coupled plasma (TCP) method
SF6The step of performing etching groove, so as to include the epitaxial layer 12 of the second concentration layer 30 by etching and form groove 20.
Reference picture 9 and Figure 10, due to the concentration difference between the second concentration layer 30 and epitaxial layer 12, cause in etching groove
In step, the second concentration layer 30 with higher concentration is etched quickly, and the quilt of epitaxial layer 12 with relatively low concentration
More slowly etch.
In other words, the concentration of impurity is higher, and etch-rate is higher.
Therefore, as shown in figure 9, the vertical wall 25 of groove be formed towards its upside it is thinning, so as to allow the depression of groove
Shape with upper wider preferable isosceles trapezoid.
In addition, the part below the upper end 15-2 of the vertical wall of groove is dug by being etched with bottleneck shape 28, and
The angular shape on the top edge border of vertical wall is trimmed to about and forms smooth fillet.
Then, the SiO remained after etching step is removed2Mask pattern 15-2.
The SiO that Figure 11 diagrams are remained after the etch process2The removed section of mask pattern.
Reference picture 11, removes SiO2The vertical wall of the groove of mask pattern includes the bottleneck shape with narrow top
28。
Figure 12 is to show to be formed by performing subsequent deposition process in the groove formed according to embodiment of the present invention
The sectional view of deposition film.
Reference picture 12, according to the embodiment of the present invention, SiO is deposited as by subsequent technique in the trench2The knot of film
Really, it can be seen that compared with conventional deposition shape, the deposition film deposited has constant thickness, so that it is inclined to reduce thickness
Difference.
Especially, the deviation between the top of vertical wall and side wall is substantially reduced.
Therefore, because the groove formed according to the embodiment of the present invention has the vertical wall narrowed towards upside, and
With the fillet being smoothly formed, therefore upright position that can be based on deposition film and horizontal level reduce to be deposited on groove
The thickness deviation of deposition film, and deposition film can be formed more uniformly on groove.
Figure 13 is illustrated in the oxide-film deposited on the groove formed according to embodiment of the present invention and PR mask patterns.
In subsequent technique, following technique can be performed on the groove structure formed according to embodiment of the present invention：
SiO2Depositing operation, oxidation film of grid formation process, poiysilicon deposition process, metal (for example, Al, Ti as electrode or
Ni) depositing operation.
Reference picture 12,, can be in the top throughout vertical wall, vertical wall compared to conventional art when deposited oxide film
Deposition film is equably deposited on the bottom of the depression of side wall and groove, and can especially prevent from being swelled at the top of vertical wall as ball
Shape.
In addition, as shown in figure 13, in addition in the trench injection ion and in SiO2PR masks are formed selectively on film
In pattern 60-2 situation, the thickness of the 2nd PR mask patterns can keep permanent on the groove formed according to embodiment of the present invention
It is fixed, so as to be significantly reduced to the possibility defocused in photoetching process.
Further, since PR thickness deviation reduces, it can improve and not develop and misalignment issues.
Component description
11：Substrate
12：Epitaxial layer
14：PR mask patterns
15：SiO2Layer
15-1：SiO2Mask pattern
15-2：The upper end of groove
20：Groove
25：The vertical wall of groove
28：Bottleneck shape
30：Second concentration layer
50：Oxide-film
60：2nd PR mask patterns
Claims (8)
1. a kind of method for the groove for forming the SiC power semiconductors with improved Step Coverage, including：
By injecting the first foreign ion on the epitaxial layer that is formed on high concentration semiconductor substrate layer and to form second dense
Spend layer；
SiO is formed on second concentration layer2Layer；
In the SiO2PR mask patterns are formed on layer, the PR mask patterns have the pattern that the formation for groove is designed；
Using the PR mask patterns by etching the SiO2Layer forms SiO2Mask pattern；
Remove the etching SiO2The PR mask patterns remained after layer；With
Utilize the SiO2Mask pattern includes the epitaxial layer of second concentration layer by dry etching and forms the ditch
Groove.
2. according to the method described in claim 1, wherein second concentration layer is with more miscellaneous than the epitaxial layer higher concentration
Matter.
3. according to the method described in claim 1, wherein about the 5% of the depth for being formed as the groove of second concentration layer
To 20%.
4. method according to claim 2, wherein second concentration layer is formed as about the 8% of the depth of the groove.
5. according to the method described in claim 1, wherein the concentration of the impurity in the epitaxial layer is 3.0 × 1015Cm-3, it is described
The concentration of impurity in second concentration layer is 1 × 1020Cm-3。
6. according to the method described in claim 1, wherein the thickness of second concentration layer is 0.2 μm, and the groove
The depth of depression is 2.5 μm.
7. according to the method described in claim 1, wherein, formed the groove the step of in, the vertical wall shape of the groove
As thinning towards its upside, and part under the upper end of the vertical wall is dug as with bottleneck shape.
8. according to the method described in claim 1, wherein first foreign ion is Nitrogen ion.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2016-0010519 | 2016-01-28 | ||
| KR1020160010519A KR20170090542A (en) | 2016-01-28 | 2016-01-28 | Manufacturing method for trench of SiC having improved step-coverage |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107039248A true CN107039248A (en) | 2017-08-11 |
Family
ID=59532805
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610847669.3A Pending CN107039248A (en) | 2016-01-28 | 2016-09-23 | The method for forming the SiC grooves with improved Step Coverage |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR20170090542A (en) |
| CN (1) | CN107039248A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1722364A (en) * | 2004-02-09 | 2006-01-18 | 三星电子株式会社 | The inductor that has the groove structure of cavity and comprise groove structure |
| US20070057262A1 (en) * | 2005-09-12 | 2007-03-15 | Fuji Electric Holding Co., Ltd. | Semicoductor device and manufacturing method thereof |
| US20100006861A1 (en) * | 2008-07-08 | 2010-01-14 | Denso Corporation | Silicon carbide semiconductor device and manufacturing method of the same |
-
2016
- 2016-01-28 KR KR1020160010519A patent/KR20170090542A/en not_active Application Discontinuation
- 2016-09-23 CN CN201610847669.3A patent/CN107039248A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1722364A (en) * | 2004-02-09 | 2006-01-18 | 三星电子株式会社 | The inductor that has the groove structure of cavity and comprise groove structure |
| US20070057262A1 (en) * | 2005-09-12 | 2007-03-15 | Fuji Electric Holding Co., Ltd. | Semicoductor device and manufacturing method thereof |
| US20100006861A1 (en) * | 2008-07-08 | 2010-01-14 | Denso Corporation | Silicon carbide semiconductor device and manufacturing method of the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20170090542A (en) | 2017-08-08 |
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Application publication date: 20170811 |