CN107038122A - Time release of an interleave circuit and method - Google Patents
Time release of an interleave circuit and method Download PDFInfo
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- CN107038122A CN107038122A CN201610079459.4A CN201610079459A CN107038122A CN 107038122 A CN107038122 A CN 107038122A CN 201610079459 A CN201610079459 A CN 201610079459A CN 107038122 A CN107038122 A CN 107038122A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0607—Interleaved addressing
Abstract
The present invention discloses a kind of time de-interlace method and time release of an interleave circuit.Methods described is applied to the signal receiving end of a communication system, for carrying out time release of an interleave processing to an interleaving signal, and the interleaving signal interlocks block and one second time interleaving block comprising a very first time, and it is included：Reading the very first time from a memory interlocks a Part I unit of block；Discharge a Part I unit storage space corresponding in the memory；And from before the very first time to be interlocked to the memory block reading completely, a Part II unit of the second time interleaving block is write into the storage space.
Description
Technical field
The present invention is on time release of an interleave circuit and method, especially with respect to ranks (row-column) or block
(block) release of an interleave circuit and method.
Background technology
To avoid causing substantial amounts of bit-errors in the short time, lead to not the data that transmission is reduced using error correction,
Be frequently utilized that in communication system staggeredly processing be intended to transmission data break up so that be originally it is successional mistake so that become with
The mistake of machine, thus can by error correction processing, correct most mistake, and then reduce error rate.Time hands over
Fault reason (time-interleaving process) is that common one kind in communication system is interlocked processing, and it is in transmission end general
One data block is sequentially write in a memory line by line, then is sequentially read line by line from memory so that number
A time ecotone block is formed according to the data redistribution of block, because time interleaving processing is located in units of block
Reason, therefore also known as interleaves blocks are handled.And the receiving terminal of communication system carries out corresponding time release of an interleave processing again.
One time interleaving (time-interleaving, hereinafter referred to as TI) block includes NFECIndividual forward error correction
(forward error correction, hereinafter referred to as FEC) block, each FEC blocks include NcellIndividual unit (cell),
NFECAnd NcellDefined by relevant communication standards.Known time release of an interleave circuit usually requires to reserve 2 memory blocks,
Some operational phase it is one of for write-in data another for reading data, role exchange both during the next stage.It please join
Fig. 1 a and Fig. 1 b are read, it is the schematic diagram for the memory configuration for becoming known for time release of an interleave.Fig. 1 a and Fig. 1 b are respectively deposited comprising 2
Memory block 110 and 120, Nr (=N are configured to per block storagecell/ 5, N in this examplecell=20, therefore Nr=4) go and Nc
(=NFEC× 5, N in this exampleFEC=2, therefore Nc=10) row, that is, can store the data volume of a TI block per block storage
(a TI block includes N in this exampleFEC×Ncell=2 × 20=40 unit).Fig. 1 a state be memory block 110 just
Write a TI blocks A all units (a0~a39) well, be stored in originally all units of memory block 120 just by
Reading is finished.The next stage will read data from memory block 110, and the data newly entered then write memory block 120.Fig. 1 b
Configuration schematic diagram for memory block 110 with memory block 120 respectively after 20 times are read and write, by Fig. 1 a and Fig. 1 b
It can be found that the storage space that any time point all has the data volume for being equal to a TI block (that is, is equivalent to one and deposited
The size of memory block 110 or 120) idle state is in, this is because of either memory block 110 or memory block
120 are all designed in units of the data volume of a TI block, thus the service efficiency of reduction memory.
The content of the invention
In view of the deficiencies in the prior art a, purpose of the invention is to provide a kind of time release of an interleave circuit and method, with
Save memory.
The present invention discloses a kind of time de-interlace method, applied to the signal receiving end of a communication system, for handing over one
Wrong signal carries out time release of an interleave processing, and the interleaving signal interlocks block and one second time interleaving area comprising a very first time
Block, it is included：Reading the very first time from a memory interlocks a Part I unit of block；Discharge the Part I list
A member storage space corresponding in the memory；And read the very first time block that interlocks completely from the memory
Before, a Part II unit of the second time interleaving block is write into the storage space.
The present invention also discloses a kind of time release of an interleave circuit, applied to the signal receiving end of a communication system, for one
Interleaving signal carries out time release of an interleave processing, and the signal receiving end includes a memory, and the interleaving signal includes a very first time
Staggeredly block and one second time interleaving block, it is included：One reads address generator, for producing a reading address；One writes
Enter address generator, for producing a writing address；And a memory control unit, for being deposited according to the reading address from this
One storage space of reservoir reads the very first time and interlocked a Part I unit of block, and in read completely this first
Before time interleaving block, a Part II of one second time interleaving block is write in the storage space according to the writing address
Unit.
The time release of an interleave circuit of the present invention utilizes the memory sub-block for the data volume for being less than a TI block with method
For access unit, memory is set more can flexibly to use, so as to reduce demand of the time release of an interleave processing to memory.
Feature for the present invention, implementation and effect, are described in detail as follows with reference to accompanying drawing to embodiment herein.
Brief description of the drawings
The schematic diagram that Fig. 1 a~1b configures for the memory for time release of an interleave of prior art；
Fig. 2 is the functional block diagram of an embodiment of the time release of an interleave circuit of the present invention；
Fig. 3 is the flow chart of an embodiment of the time de-interlace method of the present invention；And
The schematic diagram that Fig. 4 a~4m configures for the present invention for the memory of time release of an interleave.
【Reference numeral explanation】
110th, 120 memory block
210 frequency release of an interleave circuits
200 time release of an interleave circuits
221 memories
222 memory control units
223 write address generators
224 read address generator
226 address corresponding tables
228 use state tables
230 unit release of an interleave circuits
410th, 420,430,440,450,460 memory sub-block
S310~S390 steps
Embodiment
Disclosed content include time release of an interleave circuit and method, be embodied as it is possible under the premise of, this area
Technical staff can select equivalent element or step to realize the present invention, that is, the present invention according to the disclosure of this specification
Implementation be not limited to after the embodiment chatted.
Fig. 2 is the functional block diagram of an embodiment of the time release of an interleave circuit of the present invention.Time release of an interleave circuit 200
Include memory 221, memory control unit 222, write address generator 223, reading address generator 224, address correspondence
Table 226 and use state table 228.Write address generator 223 and reading address generator 224 are according to address corresponding table 226
And/or use state table 228 produces writing address and reads address respectively, and memory control unit 222 is then according to write-in ground
TI blocks in intercrossed data are write and read memory 221 by location and reading address, to carry out time release of an interleave processing.Another
In one embodiment, time release of an interleave circuit of the invention can carry out time release of an interleave processing using an external memory.
Fig. 3 is the flow chart of an embodiment of the time de-interlace method of the present invention, below in conjunction with depositing for Fig. 4 a~Fig. 4 m
The schematic diagram of reservoir configuration, to illustrate the operation principle of time release of an interleave circuit 200.Step S310 determines memory sub-block
Size, in this embodiment, by taking the columns c=5 and line number r=2 of sub-block as an example, therefore each sub-block can store 2 rows
× 5 arrange totally 10 units.Then the size and the size of memory sub-block according to TI blocks, determine the need of memory sub-block
Seek number (step S320).The number k of sub-block can be determined according to following formula：
Continue Fig. 1 example (i.e. Ncell=20, NFEC=2), can obtain the required sub-block number of the present invention is k=(5
× 2/5+1) × (20/5/2)=3 × 2=6.As shown in fig. 4 a, memory 221 includes 6 size identical memory sub-blocks
410~460.In fact, equation (1) can be rewritten as：
Wherein (Nc/c) × (Nr/r) is memory block 110 or the equivalent sub-block of memory block 120 in Fig. 1
Number, therefore the processing of known release of an interleave needs 2 × (Nc/c) × (Nr/r)=2 × (10/5) × (4/2)=8 sub-block altogether, compared with
The present invention (Nc/c-1) × (Nr/r) individual sub-blocks more.As can be seen here, with (i.e. Nc and Nr phases for an equal amount of TI blocks
Together), when the sub-district block number that uses of the present invention it is more (that is, each sub-block is smaller, that is, r values or c values it is smaller), it is of the invention
The memory saved is more.
One use state table 228 (step S330) is next provided.Use state table 228 is used to refer to each memory
The use state of block, in one embodiment, use state table 228 is with k position, the corresponding sub-block in each position, with
Logical value 1/0 represents sub-block as in unused or use respectively.One address corresponding table 226 (step S340) is next provided.
The logical address of logical subfield block when address corresponding table 226 is to record accessing memory 221 and the entity of entity sub-block
The corresponding relation of address, write address generator 223 and reading address generator 224 can produce writing address and reading according to this
Address.Write address generator 223 and read address generator 224 first assume can to access altogether in operation 2 × (Nc/c) ×
(Nr/r) individual logical subfield block (or virtual sub-block), then correspond to by address corresponding table 226 the sub-district block address of entity.
Example is held, therefore the field number of address corresponding table 226 is equal to 2 × (Nc/c) × (Nr/r)=8, and each field must have foot
Enough digits indicate corresponding entity sub-block, and the digit needed for it isIn implementation, shape is used
State table 228 and address corresponding table 226 are stored in memory, for example, be stored in static RAM (SRAM).
The behaviour of the present invention is illustrated with the change order of the address corresponding table 226 shown by table 1 and use state table 228 below
Make flow.Fig. 4 a show that time release of an interleave circuit 200 just deposits a complete TI blocks A (unit a0~a39) write-in
Reservoir 221 and reading finish another TI block being previously stored in, now the 0th of corresponding table 1 time read-write operation (round=
0) use state table 228 can be obtained and (sub-block 410~460 is represented respectively from left to right, in this example for { 0,0,0,0,1,1 }
The state of sub-block 410~440 is in use, the state of sub-block 450~460 is unused) and address corresponding table 226 be
{ 0,1,2,3, x, x, x, x } (field values represent that 0, which represents sub-block 410,1, represents sub-block 420, with this with decade herein
Analogize).Note that the use state table 228 shown by table 1, address corresponding table 226 and respective figure is this read-write operation
Afterwards result (bottom line be when time operation change part), and listed by table 1 read-write operation order for simplify after expression, that is,
The operation for only illustrating one complete TI blocks B (unit b0~b39) of one complete TI blocks A of reading and write-in is suitable
Sequence, those skilled in the art can be extended to the operation of more TI blocks by the following description.In addition, write address generator
223 and read address generator 224 and actually include counter, count that (both divide according to pulse signal CLK1 and CLK2 respectively
The speed for writing and reading memory 221 with unit is relevant), and write address generator 223 and reading address generator 224
Judging unit is also each included, it produces write-in ground respectively according to count value, address corresponding table 226 and/or use state table 228
Location and reading address (step S350), also decide whether that use state table 228 and/or the (step of address corresponding table 226 need to be updated
S360).In more detail, in step S360, the judging unit foundation TI block sizes of write address generator 223 are (i.e.
Ncell、NFEC), subblock sizes (i.e. c values, r values) and count value can learn whether to be ready writing an empty sub-block at present,
If it is, the sub-block of sky is found from use state table 228 in step S370, and correspondence modification uses shape after finding
State table 228 and address corresponding table 226；On the other hand, the judging unit of address generator 224 is read according to TI block sizes, son
Block size and count value can learn last unit for whether reading a sub-block at present, if it is, in step
Use state table 228 is updated in rapid S370.In various embodiments, use state table 228 and/or address corresponding table are updated
226 action can be by memory control unit 222 is according to write address generator 223 and/or reads the defeated of address generator 224
Out perform.In fact, the read-write operation order (round) and the relation of count value (CNT) of table 1 are：Round=CNT mod
(Ncell×NFEC), though therefore explained below with round, but actually round is to represent count value.
Table 1：
It is exemplified below illustrating when address corresponding table 226 and/or use state table 228 are changed, the details of this operation
And the configuration scenario (Fig. 4 a~4m) of memory 221.
Round=1：According to TI block sizes, subblock sizes and count value, write address generator 223 is learnt at present
A new sub-block need to be write, and learns that sub-block 450 is sky from use state table 228, correspondence sub-block is then produced
The writing address of 450 address (C0, R0), on the other hand reads the address that address generator 224 produces correspondence sub-block 410
The reading address (step S350) of (C0, R0)；Step S360 is judged as YES afterwards, following (step S370), writing address production
The logical value of correspondence sub-block 450 in use state table 228 is changed to 0 by raw device 223 by 1, and will be right in address corresponding table 226
The value of the 5th logical subfield block address is answered to insert 4 (correspondence sub-blocks 450)；
Round=2：According to TI block sizes, subblock sizes and count value, address generator 224 and write-in ground are read
Location generator 223 produces the address for reading address and correspondence sub-block 450 of the address (C1, R0) of correspondence sub-block 410 respectively
The writing address (step S350) of (C0, R1), afterwards step S360 be judged as NO；
Round=3：According to TI block sizes, subblock sizes and count value, write address generator 223 is learnt at present
A new sub-block need to be write, and learns that sub-block 460 is sky from use state table 228, correspondence sub-block is then produced
The writing address of 460 address (C0, R0), on the other hand reads the address that address generator 224 produces correspondence sub-block 410
The reading address (step S350) of (C2, R0)；Step S360 judged results are yes, following (step S370), write-in ground afterwards
The logical value of correspondence sub-block 460 in use state table 228 is changed to 0 by location generator 223 by 1, and by address corresponding table 226
The value of the middle logical subfield block address of correspondence the 6th inserts 5 (correspondence sub-blocks 460)；
……
Round=6：According to TI block sizes, subblock sizes and count value, read address generator 224 and may decide that
Next logical subfield block to be read is 2, and according to address corresponding table 226, the correspondent entity sub-block 2 of logical subfield block 2 is (i.e.
Sub-block 430), the reading address of the address (C0, R0) of correspondence sub-block 430 is then produced, another aspect writing address is produced
Device 223 produces the writing address (step S350) of the address (C1, R1) of correspondence sub-block 450；Step S360 judged results are no；
……
Round=15：According to TI block sizes, subblock sizes and count value, read address generator 224 and learn this
Operate last unit a17 (i.e. address (C4, R1)) by sub-block 410 is read, on the other hand, write address generator
223 produce the writing address (step S350) of the address (C3, R0) of correspondence sub-block 460；Step S360 judged results are yes, are read
Take address generator 224 to make the mark of correspondence sub-block 410 in use state table 228 into 1 (step S370), that is, represent to deposit
Reservoir control unit 222 discharges sub-block 410；
……
Round=20：It is similar with round=15, read address generator 224 and learn that this time operation will read sub-block
430 last unit a37 (i.e. address (C4, R1)), on the other hand, write address generator 223 produce correspondence sub-block
The writing address (step S350) of 460 address (C4, R1)；Step S360 judged results are yes, and reading address generator 224 will
The mark of correspondence sub-block 430 makes 1 (step S370) into use state table 228, that is, represents that memory control unit 222 is released
Put sub-block 430；
Round=21：It is similar with round=1, read address generator 224 produce correspondence sub-block 420 address (C0,
R0 reading address), write address generator 223 produces the writing address (step of the address (C0, R0) of correspondence sub-block 410
S350)；Step S360 judged results are yes, following (step S370), and write address generator 223 is in use state table 228
The logical value of middle correspondence sub-block 410 is changed to 0 by 1, and by the correspondence of logical subfield block 7 to entity in address corresponding table 226
Sub-block 0 (i.e. sub-block 410)；
……
Round=23：It is similar with round=3, read address generator 224 produce correspondence sub-block 420 address (C2,
R0 reading address), write address generator 223 produces the writing address (step of the address (C0, R0) of correspondence sub-block 430
S350)；Step S360 judged results are yes, following (step S370), and write address generator 223 is in use state table 228
The logical value of middle correspondence sub-block 430 is changed to 0 by 1, and by the correspondence of logical subfield block 8 to entity in address corresponding table 226
Sub-block 2 (i.e. sub-block 430)；
……
Round=35：It is similar with round=15, read address generator 224 and learn that this time operation will read sub-block
420 last unit a19 (i.e. address (C4, R1)), write address generator 223 produces the address of correspondence sub-block 430
The writing address (step S350) of (C3, R0)；Step S360 judged results are yes, therefore by use state table in step S370
The mark of correspondence sub-block 420 makes 1 into 228；
……
Round=40：It is similar with round=35, read address generator 224 and learn that this time operation will read sub-block
440 last unit a39 (i.e. address (C4, R1)), write address generator 223 produces the address of correspondence sub-block 430
The writing address (step S350) of (C4, R1)；Step S360 judged results are yes, therefore by use state table in step S370
The mark of correspondence sub-block 440 makes 1 into 228.
So far TI blocks A reading and TI blocks B write-in program have been completed, has connect the lower flow for repeating the above to read and write it
His TI blocks.The detailed process for next reading TI blocks B and write-in TI blocks C can be deduced by table 2 and Fig. 4 l and Fig. 4 m,
Therefore repeat no more.Finally when all TI blocks are all disposed, that is, terminate the time release of an interleave flow (step of the present invention
S380, step S390).Above-mentioned TI blocks C is after TI blocks B is next on the time, TI blocks B on the time in being next to
After TI blocks A.
Table 2：
Above-mentioned memory sub-block can be designed as the same column access storage cell of memory 221 (referred to as
Tile), the access times to memory 221 can further be reduced.The present invention is applicable but is not limited to DVB-T2 (Digital
Video Broadcasting, DVB) and DVB-C2 transmission standard, according to its specification, a TI block is at most
2 can be included19+215Individual unit, therefore the N in following table can be calculatedFEC_TI_MAX=(219+215)/Ncell, line number and maximum number of column
Can be respectively according to Ncell- and NFEC_TI_MAXCalculate.
Table 3：
Comparison of the table 4 for the present invention and memory size needed for known method.Assuming that the size of a unit is 32, this
One memory subelement of invention is sized so as to r=c=16, that is, can store 256 units, therefore a storage
The size of device subelement is 256 × 32=8192=1KB.With NldpcExemplified by=64800 and Nr=6480, it is known that needed for method
The size of memory be 4,860KB, and the present invention memory 221 size be 2,835KB, add address corresponding table 226 and
Size ((2,835+58,320)/8/1024=7.5KB) shared by use state table 228 needs 2,842.5KB altogether, it is only necessary to known formula
58.5% or so memory of method, it is seen that the present invention effectively reduces the demand to memory really.
Table 4：
Although embodiments of the invention as described above, but those embodiments not be used for limit the present invention, this area skill
Art personnel can impose change according to the content expressed or implied of the present invention to the technical characteristic of the present invention, and all this kind change is equal
The scope of patent protection sought by the present invention may be belonged to, in other words, scope of patent protection of the invention must regard this specification
Claim is defined.
Claims (16)
1. a kind of time de-interlace method, applied to the signal receiving end of a communication system, during for being carried out to an interleaving signal
Between release of an interleave handle, the interleaving signal interlocks block and one second time interleaving block comprising a very first time, and it is included：
Reading the very first time from a memory interlocks a Part I unit of block；
Discharge a Part I unit storage space corresponding in the memory；And
From before the very first time to be interlocked to the memory block reading completely, by a Part II of the second time interleaving block
Unit writes the storage space.
2. the method as described in claim 1, wherein the second time interleaving block on the time close to the very first time in interlocking
Block.
3. method as claimed in claim 2, the wherein memory be used for the time release of an interleave handle size be less than this first
The summation of the data volume of time interleaving block and the second time interleaving block.
4. the method as described in claim 1, is also included：
Determine the size of a memory sub-block；And
The size of block of interlocking according to the very first time and the size of the memory sub-block, determine to carry out at the time release of an interleave
The number of memory sub-block required for reason.
5. the size of method as claimed in claim 4, the wherein storage space is equal to the size of the memory sub-block.
6. the same column that method as claimed in claim 4, the wherein size of the memory sub-block are equal to the memory is accessed
Storage cell.
7. method as claimed in claim 4, is also included：
A use state table is set up, the use state of those memory sub-blocks is used to refer to；
Wherein, by change, this makes the step of discharging the storage space of the Part I unit corresponding in the memory
Reached with state table.
8. method as claimed in claim 7, is also included：
An address corresponding table is set up, being used to refer to the very first time interlocks block and each sub-block of the second time interleaving block
With the corresponding relation of each memory sub-block of the memory；And
The step of in response to the Part II unit of the second time interleaving block is write into the storage space, accordingly change
The address corresponding table.
9. a kind of time release of an interleave circuit, applied to the signal receiving end of a communication system, during for being carried out to an interleaving signal
Between release of an interleave handle, the signal receiving end includes a memory, and the interleaving signal interlocks block and one the comprising a very first time
Two time interleaving blocks, it is included：
One reads address generator, for producing a reading address；
One write address generator, for producing a writing address；And
One memory control unit, for reading the very first time from a storage space of the memory according to the reading address
A staggeredly Part I unit of block, and interlocking in reading the very first time completely before block, according to the writing address in
The storage space writes a Part II unit of one second time interleaving block.
10. time release of an interleave circuit as claimed in claim 9, wherein the second time interleaving block on the time close to this
One time ecotone block.
11. time release of an interleave circuit as claimed in claim 10, the wherein memory are used for the big of time release of an interleave processing
Being less than the very first time interlocks the summation of block and the data volume of the second time interleaving block.
12. time release of an interleave circuit as claimed in claim 9, the wherein memory include multiple memory sub-blocks, it is used for
Time release of an interleave processing, the number of those memory sub-blocks and the size of the first or second time interleaving block and this deposit
The size of reservoir sub-block is relevant.
13. time release of an interleave circuit as claimed in claim 12, the wherein size of the storage space are equal to memory
The size of block.
14. time release of an interleave circuit as claimed in claim 12, the wherein size of the memory sub-block are equal to the memory
A same column access storage cell.
15. time release of an interleave circuit as claimed in claim 12, wherein the reading address generator are included according to one first arteries and veins
One first counter counted is rushed, the write address generator includes one second counter according to one second step-by-step counting, should
First pulse with from the memory read the very first time interlock block speed it is relevant, second pulse with by second time
Staggeredly block write the memory speed it is relevant, the time release of an interleave circuit is also included：
One storage element, for storing a use state table, is used to refer to the use state of those memory sub-blocks；
Wherein the reading address generator and the write address generator couple the storage element, the reading address generator foundation
The count value of first counter produces the reading address, the write address generator according to second counter count value and
The use state table produces the writing address, and the reading address generator and the write address generator are respectively according to first meter
The count value of number device and the count value of second counter decide whether to update the use state table.
16. time release of an interleave circuit as claimed in claim 15, the wherein storage element also store an address corresponding table, it is used for
Indicate that the very first time interlocks each sub-block of block and the second time interleaving block and each memory sub-district of the memory
The corresponding relation of block, the reading address generator also produces the reading address according to the address corresponding table, and the writing address is produced
Device updates the address corresponding table with reference to the use state table.
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