CN107026229B - Semiconductor packaging device - Google Patents

Semiconductor packaging device Download PDF

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Publication number
CN107026229B
CN107026229B CN201710054477.1A CN201710054477A CN107026229B CN 107026229 B CN107026229 B CN 107026229B CN 201710054477 A CN201710054477 A CN 201710054477A CN 107026229 B CN107026229 B CN 107026229B
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die pad
leads
electronic device
carrier
package
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CN201710054477.1A
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CN107026229A (en
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詹勋伟
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
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    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

The electronic device comprises a carrier and a plurality of electronic components. The carrier has a lead frame and a package body. The carrier has an open top surface, a closed bottom surface, and sidewalls extending between the open top surface and the closed bottom surface. The carrier has a circular cavity extending from the open top surface of the carrier toward the closed bottom surface. The lead frame has a die pad and a plurality of leads. The leads are physically isolated from the die pad by at least one gap. The package body partially encases the lead frame such that a portion of a top surface of the die pad and a portion of each lead are exposed from the package body. The exposed portions of the leads are disposed radially along the die pad. A plurality of electronic components is disposed on the die pad.

Description

Semiconductor packaging device
Technical Field
The present invention relates to semiconductor packages, and more particularly, to semiconductor packages having light emitting elements.
Background
Light Emitting Diodes (LEDs) or laser diodes are widely used in various applications. Semiconductor light emitting devices may include LED chips having one or more semiconductor layers. When excited, the semiconductor layer can emit coherent and/or non-coherent light. During fabrication, a large number of LED semiconductor dies can be fabricated on a semiconductor wafer that can be probed or tested to accurately identify specific color characteristics (e.g., color temperature) of each die. Then, the wafer can be cut into a plurality of chips. The LED chip is typically packaged to provide: external electrical connections, heat sinks, lenses or light guides, environmental protection, and/or other features. Methods of manufacturing LED chip packages include, for example, die attach, wire bonding, molding, testing, and other processes.
A part of the LED control circuit is used to generate a constant DC current and control a string of a given number of LEDs. If each LED is to be controlled individually, a large area circuit board is required to implement more complex circuitry. In some cases, a lead frame with a large number of leads may be used for the electrical connections.
In addition, in some light emitting devices, a plurality of LEDs and controllers are individually packaged and then mounted on a main board, which increases manufacturing costs and the total area of the light emitting device.
Disclosure of Invention
According to an embodiment of the present invention, an electronic device includes a carrier and a plurality of electronic components. The carrier has a lead frame and a package body. The carrier has an open top surface, a closed bottom surface, and sidewalls extending between the open top surface and the closed bottom surface. The carrier has a circular cavity extending from the open top surface of the carrier toward the closed bottom surface. The lead frame has a die pad and a plurality of leads. The leads are physically isolated from the die pad by at least one gap. The package body partially encases the lead frame such that a portion of a top surface of the die pad and a portion of each lead are exposed from the package body. The exposed portions of the leads are disposed radially along the die pad. A plurality of electronic components is disposed on the die pad.
According to an embodiment of the present invention, a carrier includes a leadframe and a package. The lead frame has a die pad and a plurality of leads. The leads are physically isolated from the die pad by at least one gap. The package body partially encases the lead frame such that a portion of a top surface of the die pad and a portion of each lead are exposed from the package body. The package has an open top surface, a closed bottom surface, and sidewalls extending between the open top surface and the closed bottom surface. The package body has a circular cavity extending from the open top surface toward the closed bottom surface of the package body. The exposed portions of the leads are disposed radially along the die pad.
According to an embodiment of the invention, the electronic module comprises a first carrier. The first carrier has a plurality of packages disposed thereon. Each package includes a second carrier. The second carrier has an open top surface, a closed bottom surface, and sidewalls extending between the open top surface and the closed bottom surface. The second carrier has a circular cavity extending from the open top surface of the carrier toward the closed bottom surface. The second carrier includes a leadframe, a package, and a plurality of electronic components. The lead frame has a die pad and a plurality of leads. The leads are physically isolated from the die pad by at least one gap. The package body partially encases the lead frame such that a portion of a top surface of the die pad and a portion of each lead are exposed from the package body. The exposed portions of the leads are arranged radially along the die pad. The plurality of electronic components is disposed on the die pad. An enclosure covers the package.
Drawings
Fig. 1A illustrates a perspective view of a semiconductor package device according to an embodiment of the present invention.
Fig. 1B illustrates a bottom view of a semiconductor package device according to an embodiment of the present invention.
Fig. 1C illustrates a schematic diagram of a semiconductor package device according to an embodiment of the invention.
Fig. 2 illustrates a top view of a semiconductor package device according to an embodiment of the present invention.
Fig. 3 illustrates a top view of a semiconductor package device according to an embodiment of the present invention.
Fig. 4 illustrates a schematic diagram of a semiconductor package device according to an embodiment of the present invention.
FIG. 5 illustrates a top view of an electronic device according to an embodiment of the invention.
Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements. The present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings.
Detailed Description
Fig. 1A illustrates a perspective view of a semiconductor package device 1 according to some embodiments of the present invention. The semiconductor package 1 comprises a carrier and a plurality of electronic components 13, 14.
The carrier 10 has an open top surface, a closed bottom surface, and sidewalls extending between the open top surface and the closed bottom surface. The carrier 10 has or defines a circular cavity 10a extending from an open top surface towards a closed bottom surface of the carrier 10. As shown in fig. 1A, the carrier 10 includes a lead frame 12 and a package 11.
The lead frame 12 is a premolded lead frame having a die pad 12a and a plurality of leads 12 b. The lead frame 12 may be composed of copper, a copper alloy, or other suitable material or alloy. In some embodiments, the leadframe 12 may include one or a combination of the following: iron/iron alloy, nickel/nickel alloy or other metal/metal alloys. In some embodiments, the lead frame 12 is coated with a silver layer.
The die pad 12a has a first region 12a1 and a second region 12a 2. In some embodiments, the first region 12a1 of the die pad is substantially arc-shaped or circular. For example, the first region 12a1 of the die pad 12a may be circular, oval, or other arc-shaped. In some embodiments, the first region 12a1 of the die pad 12a may be a portion of a circle, oval, or other arc. In some embodiments, the die pad 12a is a thermal pad (e.g., of a suitable material that is capable of withstanding thermal energy generated by electronic components 13, 14 placed thereon).
The leads 12b are arranged radially (or radially) along the die pad 12 a. For example, the leads 12b are arranged in a direction from the center of the die pad 12a toward the outer edge of the die pad 12 a. The leads 12b are separated from the die pad 12 a. That is, there is at least one gap between the leads 12b and the die pad 12 a. In some embodiments, the at least one gap is filled by the package body 11. In some embodiments, the distance between the edge of the die pad 12a and the end of each lead 12b or the end of at least two leads is substantially the same. In some embodiments, the gap has a width of about 0.15 micrometers (μm) to about 0.2 μm. In some embodiments, the edge of the die pad 12a is conformal (conformal) to the end of each lead 12 b. In some embodiments, the leadframe 12 has 13 leads. In other embodiments, the leadframe 12 may be selected to have any number of leads according to the requirements of the semiconductor package device.
The package body 11 is disposed on the lead frame 12 and covers a portion of the lead frame 12. For example: the package body 11 covers a portion of the second region 12a2 of the die pad 12a and a portion of each lead 12 b. In some embodiments, the package 11 includes an epoxy resin having a filler (filler) dispersed therein.
The package body 11 has a circular cavity 10a extending from a top surface of the package body 11 to a bottom surface of the package body 11. The cavity 10a exposes a portion of the die pad 12a and a portion of the leads 12 b. The sidewalls 11a of the cavity 10a may be made of a material including a reflective material. In some embodiments, the sidewall 11a of the cavity 10a may serve as a reflective surface. Since the electronic components 13 and 14 are integrated into the single semiconductor package device 1, it is necessary to miniaturize the semiconductor package device. The shape of the package body 11 contributes to reducing the overall size of the semiconductor package device 1. For example, the package body 11 may have a recess 11r to accommodate more components or expose more leads. In some embodiments, the groove 11r is formed in a sidewall of the package body 11.
An electronic component 13 (including 13a, 13b, 13c) is disposed on the second region 12a2 of the die pad 12 a. In some embodiments, the electronic components 13a, 13b, 13c are LEDs. The LEDs 13a, 13b, 13c may be disposed adjacent to each other. In some embodiments, such as for use in a three primary color (RGB) device, the LEDs 13a, 13b, 13c may be red, green, and blue LEDs, respectively (e.g., emitting red, green, and blue visible light spectra), and may be disposed adjacent to one another to enhance color mixing to avoid a blind zone.
The electronic component 14 is disposed on the first region 12a1 of the die pad 12 a. In some embodiments, the electronic component 14 is a controller. The electronic component 14 may be or include an Integrated Circuit (IC). The electronic component 14 may be a general purpose processor (general purpose processor), a microprocessor, a microcontroller, or other Programmable components (such as a Field Programmable Gate Array (FPGA) or other controllers such as an Application-specific integrated circuit (ASIC)).
The electronic component 14 is electrically connected to the LEDs 13a, 13b, 13c by wires 15 and is configured to control the LEDs 13a, 13b, 13c through at least one wire 15. In some embodiments, the electronic component 14 may be connected to the lead 12b by other wires 15. Connecting the LEDs 13a, 13b, 13c to the electronic component 14 and then connecting the electronic component to the lead 12b reduces the length of the wires, as compared to directly connecting the LEDs 13a, 13b, 13c to the lead 12 b. This prevents short-circuiting of the wires 15. In addition, the use of shorter length wires 15 also reduces manufacturing costs.
To individually or collectively control the LEDs, the carrier will either have or present a complex circuit, which will require a large number of leads for connection. In some embodiments, the carrier has a cavity that limits the number and layout of leads and prevents bonding of wires between the electronic component and the leads due to the different distances between the leads and the bonding pads of the electronic component. Fig. 1 discloses a circular cavity 10a in which leads 12b conform to the edges of a circular die pad 12a, thus helping to increase the number of leads available for the semiconductor package device 1. In addition, since the shape and size of each lead 12b exposed outside the package body 11 are substantially the same, it is possible to simplify the connection of wires between the electronic component 14 and the leads, thereby reducing the manufacturing cost and time.
Fig. 1B illustrates a bottom view of a semiconductor package device 1 according to some embodiments of the invention. As shown in fig. 1B, a portion of the die pad 12a and a portion of the lead 12B are covered by the package body 11. The exposed portions of the die pads 12a and leads 12b are substantially coplanar with the bottom surface of the package body 11.
Fig. 1C illustrates a schematic diagram of a semiconductor package device 1 according to some embodiments of the invention. As shown in fig. 1C, each lead 12b has a first portion covered or covered by the package body 11 and a second portion exposed outside the package body 11.
The width of each lead 12b decreases in a direction toward the die pad 12 a. The length of the second portion of each lead 12b is substantially the same even though the total length of each lead 12b may be different. In some embodiments, because the leads 12b have different lengths, a break 12b3 may be formed between the first portion 12b1 and the second portion 12b2, so that the exposed portions (e.g., the second portion 12b2) of the leads 12b have the same length.
Fig. 2 illustrates a schematic diagram of a semiconductor package device 2 according to some embodiments of the invention. The semiconductor package device 2 is similar to the semiconductor package device 1 shown in fig. 1C except that the lengths of the exposed portions of the leads are not exactly the same in the semiconductor package device 2. For example, the length of the exposed portion of lead 22b1 is less than the length of the exposed portion of lead 22b 2. In some embodiments, a portion of the leads (e.g., the leads 22b3) may be completely covered or covered by the package body 11. Thus, the distance between each lead and the die pad 12a is not exactly the same, which increases the difficulty of wire bonding the electronic component 14 to the lead. In contrast, since the shape and size of each lead 12b exposed outside the package body 11 in fig. 1C are substantially the same, it is possible to simplify the connection of the wires between the electronic component 14 and the leads 12b, thereby reducing the manufacturing cost and time.
Fig. 3 illustrates a schematic diagram of a semiconductor package device 3 according to some embodiments of the invention. The semiconductor package device 3 is similar to the semiconductor package device 1 shown in fig. 1C except for the following differences: in the semiconductor package device 3, the lengths of the exposed portions of the leads exposed outside the package body 31 are not exactly the same; the carrier 30 has a rectangular cavity 30a extending from its open top surface toward its closed bottom surface; and die pad 32a is rectangular. The rectangular cavity 30a limits the number and layout of leads and also prevents the connection of the leads between the electronic component and the leads due to the different distances between the leads and the connection pads of the electronic component. By contrast, by using the circular cavity 10a as shown in fig. 1C, the leads 12b may conform to the edge of the circular die pad 12a, which may increase the number of leads suitable for the semiconductor package device. In addition, as shown in fig. 3, the leads may have different distances from the die pad 32a, which may make wire bonding between the electronic component 34 and the leads difficult. In contrast, as shown in fig. 1C, since the shape and size of each lead 12b exposed outside the package body 11 are substantially the same, it is possible to simplify the connection of the wires 15 between the electronic component 14 and the leads 12b, thereby reducing the manufacturing cost and time.
Fig. 4 illustrates a schematic diagram of a semiconductor package device 4 according to some embodiments of the invention. The semiconductor package device 4 is similar to the semiconductor package device 1 shown in fig. 1C, and the semiconductor package device 4 has a lead frame 42 having a die pad 42a and a plurality of leads 42 b. In fig. 4, the first region 42a1 and the second region 42a2 of the die pad 42a are separated from each other. A gap exists between the first region 42a1 and the second region 42a2 of the die pad 42 a. The gap has a width of about 0.15 μm to about 0.2 μm.
The LEDs 13a, 13b, 13c are placed on the second area 42a2 of the die pad 42 a. The electronic component 14 is placed on the second region 42a1 of the die pad 42 a. By separating the first portion 42a1 and the second portion 42a2 of the die pad 42a, the thermal energy generated by the LEDs 13a, 13b, 13c is less likely to adversely affect the electronic component 14.
Fig. 5 illustrates a top view of an electronic device 5 according to some embodiments of the invention. In some embodiments, the electronic device 5 is an adjustable LED module. As shown in fig. 5, the electronic device 5 has a plurality of semiconductor packages 1 as shown in fig. 1A. In some embodiments, the electronic device 5 has a plurality of semiconductor package devices 2, 3, or 4 as shown in fig. 2-4, or a combination thereof (including a combination with the semiconductor package device 1). In some implementations, the electronic device 5 may have any number of semiconductor packages.
As used herein, the terms "substantially", "substantial", "about" and "about" are used to describe and account for minor variations. When used in conjunction with an event or circumstance, the terms can refer to the situation in which the event or circumstance occurs explicitly, as well as the situation in which the event or circumstance occurs in close proximity. For example, the term may refer to less than or equal to ± 10%, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1% or less than or equal to ± 0.05%. The term "substantially coplanar" may refer to two surfaces having a difference along the same plane within microns, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm. When the terms "substantially," "about," and "approximately" are used in reference to an event or circumstance, it can mean that the event or circumstance occurs exactly, or that the event or circumstance is close to an approximation.
In some embodiments, an element "on" another element may include an element directly on the other element (e.g., in physical contact with the other element), or may mean that there are other elements between the element and the other element.
Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such a range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.
While the invention has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the invention. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be a distinction between artistic renditions in the present invention and actual equipment. There may be other embodiments of the invention not specifically described. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present invention.

Claims (26)

1. An electronic device, comprising:
a carrier having an open top surface, a closed bottom surface, and sidewalls extending between the open top surface and the closed bottom surface, the carrier having a circular cavity extending from the open top surface of the carrier toward the closed bottom surface, the carrier comprising:
a lead frame having a die pad and a plurality of leads, the leads being physically isolated from the die pad by at least one gap;
a package body having sidewalls and partially encasing the lead frame such that a portion of a top surface of the die pad and a portion of each lead are exposed from the package body, wherein the exposed portions of the leads are arranged radially along the die pad; and
a plurality of electronic components disposed on the die pad and including a controller and a transmitter,
wherein a recess is formed in the sidewall of the package body and a portion of the die pad is exposed from the recess, an
The die pad includes a central portion on which the controller is disposed and an edge portion on which the transmitter is disposed.
2. The electronic device of claim 1, wherein the at least one gap is filled by the package.
3. The electronic device of claim 1, wherein edges of the die pad conform to ends of the leads.
4. The electronic device of claim 3, wherein a distance between an edge of the die pad and the end point of each lead is substantially the same.
5. The electronic device of claim 3, wherein an edge of the die pad is arcuate.
6. The electronic device of claim 1, wherein the width of the at least one gap is in a range of 0.15 microns to 0.2 microns.
7. The electronic device of claim 1, wherein the central portion and the edge portion are physically isolated from each other by a gap of the die pad.
8. The electronic device of claim 1, wherein sidewalls of the circular cavity of the carrier comprise a reflective material.
9. The electronic device of claim 1, wherein another portion of the die pad is covered by the package body.
10. An electronic device, comprising:
a controller;
a transmitter;
a lead frame having a die pad and a plurality of leads, the leads being physically isolated from the die pad by at least one gap; and
a package partially encasing the lead frame such that a portion of a top surface of the die pad and a portion of each lead are exposed from the package, the package having an open top surface, a closed bottom surface, and sidewalls extending between the open top surface and the closed bottom surface, the package having a circular cavity extending from the open top surface toward the closed bottom surface of the package, the exposed portions of the leads being radially disposed along the die pad,
wherein a recess is formed in at least one of the sidewalls of the package body and a portion of the die pad is exposed from the recess, an
The die pad includes a central portion on which the controller is disposed and an edge portion on which the transmitter is disposed.
11. The electronic device of claim 10, wherein the at least one gap is filled by the package.
12. The electronic device of claim 10 wherein edges of the die pad conform to the ends of the leads.
13. The electronic device of claim 12, wherein a distance between an edge of the die pad and the end point of each lead is substantially the same.
14. The electronic device of claim 12, wherein an edge of the die pad is arcuate.
15. The electronic device of claim 10, wherein the width of the at least one gap is in a range of 0.15 microns to 0.2 microns.
16. The electronic device of claim 10, wherein a sidewall of the circular cavity of the package comprises a reflective material.
17. The electronic device of claim 10, wherein another portion of the die pad is covered by the package body.
18. An electronic module, comprising:
a first carrier having a plurality of packages disposed thereon, each package comprising:
a second carrier having an open top surface, a closed bottom surface, and sidewalls extending between the open top surface and the closed bottom surface, the second carrier having a circular cavity extending from the open top surface of the carrier toward the closed bottom surface, the second carrier comprising:
a lead frame having a die pad and a plurality of leads, the leads being physically isolated from the die pad by at least one gap;
a package body having a sidewall and partially encasing the lead frame such that a portion of a top surface of the die pad and a portion of each lead are exposed from the package body, wherein the exposed portions of the leads are arranged radially along the die pad, and wherein a recess is formed in the sidewall of the package body and a portion of the die pad is exposed from the recess; and
a plurality of electronic components disposed on the die pad and including a controller and a transmitter; and
a cover covering the package,
wherein the die pad includes a central portion on which the controller is disposed and an edge portion on which the transmitter is disposed.
19. The electronic module of claim 18, wherein the at least one gap is filled by the package.
20. The electronic module of claim 18, wherein edges of the die pad conform to the ends of the leads.
21. The electronic module of claim 20 wherein the distance between the edge of the die pad and the end point of each lead is substantially the same.
22. The electronic module of claim 20 wherein the edge of the die pad is arcuate.
23. The electronic module of claim 18, wherein the width of the at least one gap is in the range of 0.15 microns to 0.2 microns.
24. The electronic module of claim 18, wherein the central portion and the edge portion are physically isolated from each other by a gap of the die pad.
25. The electronic module of claim 18, wherein sidewalls of the circular cavity of the second carrier comprise a reflective material.
26. The electronic module of claim 18, wherein another portion of the die pad is covered by the package body.
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6878562B2 (en) * 2017-02-21 2021-05-26 京セラ株式会社 Wiring boards, electronics and electronic modules
CN108615727A (en) * 2018-07-20 2018-10-02 深圳市天成照明有限公司 A kind of full-color integrated LED of built-in IC PLC technologies

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1684278A (en) * 2004-04-15 2005-10-19 联欣光电股份有限公司 Packaging structure of light emitting diode and its packaging method
CN101916820A (en) * 2010-06-25 2010-12-15 海洋王照明科技股份有限公司 Wiring base plate structure of LED signal lamp, light source assembly and LED signal lamp

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5754977A (en) 1996-03-06 1998-05-19 Intervoice Limited Partnership System and method for preventing enrollment of confusable patterns in a reference database
US8044418B2 (en) * 2006-07-13 2011-10-25 Cree, Inc. Leadframe-based packages for solid state light emitting devices
CN102117876B (en) * 2009-12-30 2013-02-27 展晶科技(深圳)有限公司 Semiconductor packaging structure
US8967827B2 (en) * 2010-04-26 2015-03-03 Panasonic Intellectual Property Management Co., Ltd. Lead frame, wiring board, light emitting unit, and illuminating apparatus
US9263374B2 (en) * 2010-09-28 2016-02-16 Dai Nippon Printing Co., Ltd. Semiconductor device and manufacturing method therefor
US8919975B2 (en) * 2011-11-09 2014-12-30 Cree, Inc. Lighting device providing improved color rendering
US9653656B2 (en) * 2012-03-16 2017-05-16 Advanced Semiconductor Engineering, Inc. LED packages and related methods
US9287475B2 (en) * 2012-07-20 2016-03-15 Cree, Inc. Solid state lighting component package with reflective polymer matrix layer
US9240528B2 (en) * 2013-10-03 2016-01-19 Cree, Inc. Solid state lighting apparatus with high scotopic/photopic (S/P) ratio
JP6413412B2 (en) * 2014-07-11 2018-10-31 日亜化学工業株式会社 Semiconductor light emitting device and manufacturing method thereof
US9681510B2 (en) * 2015-03-26 2017-06-13 Cree, Inc. Lighting device with operation responsive to geospatial position

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1684278A (en) * 2004-04-15 2005-10-19 联欣光电股份有限公司 Packaging structure of light emitting diode and its packaging method
CN101916820A (en) * 2010-06-25 2010-12-15 海洋王照明科技股份有限公司 Wiring base plate structure of LED signal lamp, light source assembly and LED signal lamp

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