CN107026160A - Integrated chip - Google Patents
Integrated chip Download PDFInfo
- Publication number
- CN107026160A CN107026160A CN201710061630.3A CN201710061630A CN107026160A CN 107026160 A CN107026160 A CN 107026160A CN 201710061630 A CN201710061630 A CN 201710061630A CN 107026160 A CN107026160 A CN 107026160A
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- China
- Prior art keywords
- dielectric medium
- electrode
- medium waveguide
- signal
- transmission
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
This disclosure has the integrated chip for being coupled to multiple band transmission element and receiving element through integrating dielectric medium waveguide on a kind of.In certain embodiments, integrated chip has the dielectric medium waveguide being arranged in the interlayer dielectric structure of surface.Multiple band transmission element with multiple phase modulation elements is configured to produce multiple modulated signals in different frequency bands.First side of multiple transmission electrodes along dielectric medium waveguide positions and is configured to a modulated signal in multiple modulated signals being coupled in dielectric medium waveguide respectively.
Description
Technical field
This disclosure relates to a kind of electronic technology, and in particular to a kind of integrated chip.
Background technology
Integrated optical waveguide is typically used as the component in integrated optical circuit, and integrated optical circuit integrates a variety of photon work(
Energy.Integrated optical waveguide is to constrain light and by light from integrated chip (integrated chip；IC first point on) is with most
Small decay is directed to the second point on IC.In general, integrated optical waveguide provide to visible spectrum (for example, approximate 850nm with
Between approximate 1650nm) in the function of signal that applies of optical wavelength.
The content of the invention
One embodiment of this disclosure is on a kind of integrated chip.Integrated chip is included and is arranged on substrate
Dielectric medium waveguide in the interlayer dielectric structure of side.Multiple band transmission element with multiple phase modulation elements is configured to production
Multiple modulated signals in raw different frequency bands.Multiple transmission electrodes are located at along the first side of dielectric medium waveguide and respectively through matching somebody with somebody
Put a modulated signal in multiple modulated signals being coupled in dielectric medium waveguide.
Below in conjunction with the drawings and specific embodiments, the present invention will be described in detail, but not as a limitation of the invention.
Brief description of the drawings
From the aspect described in detail below that this disclosure is best understood when being read with accompanying drawing.It should be noted that root
According to the standard practice in industry, various features are not drawn on scale.In fact, for the sake of discussing and understanding, can arbitrarily increase and add deduct
The size of few various features.
Figure 1A~Figure 1B illustrates some embodiments for including the integrated chip through integrating dielectric medium waveguide；
Fig. 2 illustrates some embodiments of the cross-sectional view comprising the integrated chip through integrating dielectric medium waveguide；
Fig. 3 illustrates some embodiments of the top view comprising the integrated chip through integrating dielectric medium waveguide, is situated between through integrating
Electric matter waveguide has one or more tapering transition zones；
Fig. 4 is illustrated comprising the multiple integrated chips through integrating dielectric medium waveguide for being configured to parallel transmission electromagnetic radiation
Top view some embodiments；
Fig. 5 A~Fig. 5 B, which illustrate to include, is arranged on last part technology (back-end-of-the-line；BEOL) metallization stack
Some embodiments of the interior integrated chip through integrating dielectric medium waveguide；
Fig. 6 illustrates some realities for including the integrated chip through integrating dielectric medium waveguide for being configured to transmit differential signal
Apply example；
Fig. 7 illustrates one of the integrated chip comprising the differential drive circuit and differential received circuit being arranged in silicon substrate
A little embodiments；
Fig. 8~Figure 10, which is illustrated, includes the one of the integrated chip through integrating dielectric medium waveguide for being coupled to differential coupling element
The 3-D view of a little Additional examples of composition；
Figure 11 illustrates some embodiments of the integrated chip comprising dielectric medium waveguide, and dielectric medium waveguide, which has, to be arranged on
Differential coupling element in BEOL metallization stacks；
Figure 12 illustrates the flow for some embodiments to form the method comprising the integrated chip through integrating dielectric medium waveguide
Figure；
Figure 13 illustrates to form the integrated chip through integrating dielectric medium waveguide comprising being arranged in BEOL metallization stacks
Method some embodiments flow chart；
Figure 14~Figure 19 illustrates the cross section that displaying forms the method comprising the integrated chip through integrating dielectric medium waveguide
Some embodiments of figure；
Figure 20 illustrates the one of the method to form the integrated chip comprising the dielectric medium waveguide for being coupled to differential coupling element
The flow chart of a little embodiments；
Figure 21~Figure 26 illustrates displaying and forms the integrated chip for including the dielectric medium waveguide for being coupled to differential coupling element
Method cross-sectional view some embodiments；
Figure 27 illustrates displaying with the whole of the multiple band transmission element and receiving element being coupled to through integrating dielectric medium waveguide
Some embodiments of the block diagram of box-like chip；
Figure 28 illustrates the example of some embodiments of the frequency spectrum in Figure 27 dielectric medium waveguide；
Figure 29 is illustrated with the integrated of the multiple band transmission element and receiving element being coupled to through integrating dielectric medium waveguide
The top view of some embodiments of chip；
Figure 30 A~Figure 30 B illustrate (orthogonal to shake with the multiband QAM through integrating dielectric medium waveguide is operationally coupled to
Width modulation) interface integrated chip some embodiments；
Figure 31 is illustrated with the integrated chip for being operationally coupled to the multiband QAM interfaces through integrating dielectric medium waveguide
Three-dimensional (3D) view some embodiments；And
Figure 32 illustrates to be formed comprising the whole of the multiple band transmission element and receiving element being coupled to through integrating dielectric medium waveguide
The flow chart of some embodiments of the method for box-like chip.
Wherein, reference
100：Integrated chip
102：Semiconductor substrate
104：Interlayer dielectric material
106：Dielectric medium waveguide
108：Drive circuit
110：Receiving circuit
112：First interconnection
114：First coupling element
116：Second interconnection
118：Second coupling element
120：3-D view
200：Integrated chip
202：Silicon substrate
204：Drive circuit
206：Receiving circuit
207：First metal transmission line
208：First coupling element
208a：First lower electrode
208b：First upper electrode
209a：First earth terminal
209b：Second earth terminal
210：Second coupling element
210a：Second lower electrode
210b：Second upper electrode
211：Second metal transmission line
212：Ground shield element
IN：Input signal
OUT：Output signal
G1：First grid region
D1：First drain region
S1：First source region
G2：Second grid region
D2：Second drain region
S2：Second source region
S1：First electric signal, the first transmitted signal component
S2：Second electric signal, the second transmitted signal component
300：Integrated chip
302：First coupling element
304：Second coupling element
306：Microstrip line
308：Microstrip line
310：Dielectric medium waveguide
312：First Transition region
314：Second transitional region
316：Direction
318：Direction
400：Integrated chip
402：Drive circuit
402a：Driving element
402b：Driving element
402c：Driving element
404a：Microstrip line
404b：Microstrip line
404c：Microstrip line
406：Coupling element
408a：Dielectric medium waveguide
408b：Dielectric medium waveguide
408c：Dielectric medium waveguide
410：Coupling element
412a：Microstrip line
412b：Microstrip line
412c：Microstrip line
414：Receiving circuit
414a：Receiving element
414b：Receiving element
414c：Receiving element
S1'：First electric signal
500：Integrated chip
502：Drive circuit
504：Receiving circuit
506：First ILD layer
508：Second ILD layer
510：3rd ILD layer
512：4th ILD layer
514：Through hole
518：5th ILD layer
520：First coupling element
520a：First lower electrode
520b：First upper electrode
522a：Second lower electrode
522b：Second upper electrode
522：Second coupling element
524：Shielding element
524a：Grounded metal line
524b：Grounded metal line
524c：Grounded metal line
524d：Grounded metal line
526：Integrated chip
M1：First metal line layer
M2：Second metal line layer
M3：3rd metal line layer
V0：First through hole layer
V1：Second via layer
V2：Second via layer
S：First source region, the second source region
D：First drain region, the second drain region
600：Integrated chip
602：Differential drive circuit
603a：Transmission line
603b：Transmission line
604：First transmission electrode
605：Differential transfer coupling element
606：Second transmission electrode
608：First receiving electrode
609：Differential received coupling element
610：Second receiving electrode
611a：First transmission line
611b：Second transmission line
612：Differential received circuit
OUT1：First output node
OUT2：Second output node
IN1：First input node
IN2：Second input node
SIN+：First input signal
SIN-：Second input signal
SOUT+、SOUT-：Output signal
S1'：First receives component of signal
S2’：Second receives component of signal
700：Integrated chip
702：Differential drive circuit
702a：First MOS electric crystals
702b：2nd MOS electric crystals
702c：RF chokes
702d：RF chokes
704：Differential received circuit
704a：3rd MOS electric crystals
704b：4th MOS electric crystals
704c：RF chokes
704d：RF chokes
VDD1：Bias
VDD2：Bias
VDD3：Bias
VDD4：Bias
G3：3rd area of grid
D3：3rd drain region
S3：3rd source region
G4：4th area of grid
D4：4th drain region
S4：4th source region
800：Integrated chip
802：Differential drive circuit
803a：Transmission line
803b：Transmission line
804：Transmission electrode
804a：Conical by its shape
804b：Conical by its shape
804c：Conical by its shape
805：Wire
806：Transmission electrode
806a：Conical by its shape
806b：Conical by its shape
806c：Conical by its shape
807：Wire
808：Receiving electrode
810：Receiving electrode
811a：First transmission line
811b：Second transmission line
812：Differential received circuit
900：Integrated chip
902：Transmission electrode
904：Transmission electrode
904a：Transmission electrode
904b：Transmission electrode
904c：Transmission electrode
906：Receiving electrode
908：Receiving electrode
908a：Receiving electrode
908b：Receiving electrode
908c：Receiving electrode
d：Edge Distance 1000：Integrated chip
1002：Differential drive circuit
1002a：Differential drive circuit
1002b：Differential drive circuit
1002c：Differential drive circuit
1002d：Differential drive circuit
1004a：Transmission electrode
1004b：Transmission electrode
1004c：Transmission electrode
1004d：Transmission electrode
1006a：Transmission electrode
1006b：Transmission electrode
1006c：Transmission electrode
1006d：Transmission electrode
1010：Differential received circuit
1010a：Differential received circuit
1010b：Differential received circuit
1010c：Differential received circuit
1010d：Differential received circuit
1012a：Receiving electrode
1012b：Receiving electrode
1012c：Receiving electrode
1012d：Receiving electrode
1014a：Receiving electrode
1014b：Receiving electrode
1014c：Receiving electrode
1014d：Receiving electrode
1100：Integrated chip
1102：Differential drive circuit
1102a：First MOS transistor
1102b：Second MOS transistor
1104：Differential received circuit
1104a：3rd MOS transistor
1104b：4th MOS transistor
520'：Differential transfer coupling element
520a'：First transmission electrode
520b'：Second transmission electrode
522'：Differential received coupling element
522a'：First receiving electrode
522b'：Second receiving electrode
1200：Method
1202：Operation
1204：Operation
1206：Operation
1300：Method
1302：Operation
1304：Operation
1306：Operation
1308：Operation
1310：Operation
1312：Operation
1314：Operation
1316：Operation
1318：Operation
1320：Operation
1322：Operation
1324：Operation
1326：Operation
1400：Cross-sectional view
1500：Cross-sectional view
1502：First etchant
1504：Opening
1506：Cross-sectional view
1508：First metal material
1600：Cross-sectional view
1602：Second etchant
1604：Via openings
1606：Shielding element opening
1608：Cross-sectional view
1610：Second metal material
1700：Cross-sectional view
1702：3rd etchant
1704：Opening
1706：Cross-sectional view
1708：3rd metal material
1800：Cross-sectional view
1802：4th etchant
1804：Dielectric medium waveguide openings
1806：Cross-sectional view
1808：Dielectric material
1810：Cross-sectional view
1812：5th etchant
1814：Through hole
1816：Cross-sectional view
1818：4th metal material
1900：Cross-sectional view
1902：6th etchant
1904：Opening
1906：Cross-sectional view
1908：Fifth metal material
2000：Method
2002：Operation
2004：Operation
2006：Operation
2008：Operation
2010：Operation
2012：Operation
2014：Operation
2016：Operation
2018：Operation
2020：Operation
2100：Cross-sectional view
2200：Cross-sectional view
2202：First etchant
2204：Opening
2206：Cross-sectional view
2208：First metal material
2300：Cross-sectional view
2302：Second etchant
2304：Via openings
2306：Shielding element opening
2308：Cross-sectional view
2310：Second metal material
2400：Cross-sectional view
2402：3rd etchant
2404：Opening
2406：Cross-sectional view
2408：3rd metal material
2500：Cross-sectional view
2502：4th etchant
2504：Dielectric medium waveguide openings
2506：Cross-sectional view
2508：Dielectric material
2510：Cross-sectional view
2512：5th etchant
2514：Through hole
2516：Cross-sectional view
2518：4th metal material
2600：Cross-sectional view
2602：6th etchant
2604：Opening
2606：Cross-sectional view
2608：Fifth metal material
2700：Integrated chip
2702：Multiple band transmission element
2704a：Phase modulation element
2704b：Phase modulation element
2704c：Phase modulation element
2706：First coupling element
2706a：Transmission electrode
2706b：Transmission electrode
2708：Second coupling element
2708a：Receiving electrode
2708b：Receiving electrode
2710：Multi-band reception element
2712a：Restitution element
2712b：Restitution element
2712c：Restitution element
2800：Frequency spectrum
2802：First frequency scope
2804：Second frequency scope
2806：3rd frequency range
2900：Integrated chip
2902：Transmission electrode
2902a：Transmission electrode
2902b：Transmission electrode
2902c：Transmission electrode 2904：Conductive contact
2906：Metal interconnecting wires
2908：Metal throuth hole
2910：Second coupling element
2910a：Receiving electrode
2910b：Receiving electrode
2910c：Receiving electrode
Smod1、Smod2、Smod3：Modulated signal
CLK1、CLK2、CLK3：Clock signal
D1：First data-signal
D2：Second data-signal
D3：3rd data-signal
3000：Integrated chip
3002：Multiband QAM transmitter elements
3004a：QAM varying elements
3004b：QAM varying elements
3004c：QAM varying elements
3006：Baseband processor
3008：Numerical digit analogy converter
3010：Up-conversion frequency mixer
3012a：Local oscillator
3012b：Local oscillator
3012c：Local oscillator
3014：Quadrature divider
3016：Adder
3018：Amplifier
3020：Control unit
3022：Multiband QAM receiving elements
3024a：QAM restitution elements
3024b：QAM restitution elements
3024c：QAM restitution elements
3026：Separator
3028：Down conversion mixers
3030：ADC
3032a：Local oscillator
3032b：Local oscillator
3032c：Local oscillator
3034：Quadrature divider
3036：Digital signal processor
3038：Stellar map
I：Equivalent fundamental frequency signal
Q：Equivalent fundamental frequency signal
SO1、SO2、SO3：Signal
SINx+、SIN1+、SIN2+、SIN3+：Difference modulation input signal
SOUTx+、SOUT1+、SOUT2+、SOUT3+：Difference modulation output signal
D1、D2、D3、D4、D5、D6：Data
D7、D8、D9、D10、D11、D12：Data
3100：Integrated chip
3102：Multiple band transmission element
3104a：First QAM varying elements
3104b：2nd QAM varying elements
3104c：3rd QAM varying elements
3106a：Top transmission electrode
3106b：Top transmission electrode
3106c：Top transmission electrode
3106d：Top transmission electrode
3106e：Top transmission electrode
3108a：Lower transfer electrode
3108b：Lower transfer electrode
3108c：Lower transfer electrode
3108d：Lower transfer electrode
3108e：Lower transfer electrode
3110：Differential drive circuit
3112a：Top receiving electrode
3112b：Top receiving electrode
3112c：Top receiving electrode
3112d：Top receiving electrode
3112e：Top receiving electrode
3114a：Bottom receiving electrode
3114b：Bottom receiving electrode
3114c：Bottom receiving electrode
3114d：Bottom receiving electrode
3114e：Bottom receiving electrode
3116：Differential drive circuit
3118：Multi-band reception element
3120a：First QAM restitution elements
3120b：2nd QAM restitution elements
3120c：3rd QAM restitution elements
3200：Method
3202：Operation
3204：Operation
3206：Operation
3208：Operation
3210：Operation
3212：Operation
3214：Operation
3216：Operation
3218：Operation
3220：Operation
h：Highly
S：Space
w：Width
Embodiment
Content disclosed below provides many different embodiments or examples for implementing the different characteristic for providing target.Under
The particular instance of text description component and arrangement, to simplify this disclosure.This certain a little content are only example and are not intended to limit.
For example, fisrt feature is formed above second feature or is formed in second feature and may include first in the description that follows
Feature and second feature directly contact the embodiment of formation, and also may include that additional features can be formed at fisrt feature and the second spy
With so that the embodiment that fisrt feature and second feature can be not directly contacted between levying.In addition, this disclosure repeat it is various
Component symbol and/or letter in example.This repeats system for simple and clear purpose and substantially regulation is not discussed
Various embodiments and/or configuration between relation.
In addition, for ease of description, herein can be used for example " below ", " in lower section ", " bottom ", " up ", " on
Portion " and the space relative terms of similar terms, with describe in all figures a depicted element or a feature with other one or
The relation of multiple element or one or more features.In addition to orientation shown in all figures, this little space relative terms is intended to cover make
The different azimuth of element in or in operation.Equipment can in another manner be oriented and (is rotated by 90 ° or in other orientation), and can
Equally space relative descriptors used herein are correspondingly explained.
Integrated optical waveguide is generally used for integrated optical circuit.In general, integrated optical waveguide is by normal with high dielectric
Several optical medium (that is, core) composition, this optical medium with high-k is by Jie with compared with low-k
Matter is surrounded.Due to the difference in dielectric constant between core and surrounding medium, injected by total internal reflection (for example, using lens, light
Grid coupler or prism coupler) visible ray into the end of integrated optical waveguide is directed to along a length of waveguide.
Because integrated optical waveguide be limited to transmit electromagnetic spectrum visible section in electromagnetic radiation (for example, frequency magnitude
For it is approximate 1015), so integrated optical waveguide faces a number of shortcoming.For example, because silicon is not to produce photon
Direct gap semi-conducting material, therefore the circuit system interaction that integrated optical waveguide can not directly with being arranged in silicon substrate.This
Outside, the frequency range that can be transmitted by integrated optical waveguide is limited.Due to this little shortcoming, so the non-integration usually using metal transmission line
Data are shifted in optical waveguide on a silicon substrate.However, at higher frequencies, metal transmission line undergoes higher damage in relatively large distance
Mistake rate.
Therefore, this disclosure system is on the integrated chip comprising coupling element, and this coupling element is configured to have
Have visible spectrum outer frequency electromagnetic radiation from silicon substrate coupled to covering silicon substrate through integrate dielectric medium waveguide in.One
In a little embodiments, integrated chip includes the interlayer dielectric (inter-level for being arranged on covering semiconductor substrate
dielectric；ILD) the dielectric medium waveguide in material.First coupling element is configured to be arranged in semiconductor substrate
The first electric signal produced by drive circuit is coupled to the first end of dielectric medium waveguide as with frequency outside visible spectrum
Electromagnetic radiation.Second coupling element is configured to electromagnetic radiation being coupled to the second telecommunications from the second end of dielectric medium waveguide
Number.Have by by the electromagnetic radiation with frequency outside visible spectrum coupled to dielectric medium waveguide and from dielectric medium waveguide coupling
The electromagnetic radiation of frequency outside visible spectrum, disclosed integrated chip can overcome a number of of optics integrated waveguide
Shortcoming.
Figure 1A illustrates the one of the block diagram of cross-sectional view of the displaying comprising the integrated chip 100 through integrating dielectric medium waveguide
A little embodiments.
Integrated chip 100 includes semiconductor substrate 102.In various embodiments, semiconductor substrate 102 can be comprising for example
Any kind of semiconductor bodies of one or more crystal grain on semiconductor crystal wafer or wafer, and any other type are partly led
Body and/or the epitaxial layer formed on the semiconductor and/or the epitaxial layer associated with semiconductor.In certain embodiments, partly lead
Structure base board 102 can include indirect gap material, for example：Silicon.
Side sets interlayer dielectric (ILD) material 104 on semiconductor substrate 102.In various embodiments, ILD materials 104
One or more dielectric layers can be included.For example, ILD materials 104 can include dielectric layer with low dielectric constant, ultralow dielectric
(ultra-low k；ULK) dielectric layer and/or silica (SiO2) one or more in layer.Set and be situated between in ILD materials 104
Electric matter waveguide 106.Dielectric medium waveguide 106 is normal comprising the dielectric that dielectric constant (that is, capacitivity) is more than surrounding ILD materials 104
Several dielectric materials.
Drive circuit 108 and receiving circuit 110 are set in semiconductor substrate 102.Drive circuit 108 is by the first interconnection
112 (for example, transmission lines) are coupled to the first coupling element 114.Drive circuit 108 is configured to produce the first electric signal, first
Electric signal is coupled in dielectric medium waveguide 106 by the first coupling element 114 and is used as electromagnetic radiation.In certain embodiments,
One coupling element 114 can include metal Coupling element (for example, metal transmission line or microstrip line).In certain embodiments, electromagnetism
Radiation is by with the frequency outside visible spectrum.
Dielectric medium waveguide 106 is configured to electromagnetic radiation being sent to the second coupling along a length of dielectric medium waveguide 106
Close element 118.Second coupling element 118 is configured to couple the electromagnetic radiation from dielectric medium waveguide 106 as by second
The second electric signal that 116 (for example, transmission lines) of interconnection are provided to receiving circuit 110.In certain embodiments, the second coupling element
118 can include metal Coupling element (for example, metal transmission line or microstrip line).By the first coupling element 114 and second of use
Coupling element 118 couples a signal in dielectric medium waveguide 106 and is coupled out dielectric medium waveguide 106, and integrated chip 100 can
Transmit the electromagnetic radiation in wider frequency range, enable whereby dielectric medium waveguide 106 be used to comprising direct gap material and
Data-signal is shifted on the substrate of indirect gap material.
Figure 1B illustrates some embodiments of the 3-D view 120 comprising the integrated chip through integrating dielectric medium waveguide.
As shown in 3-D view 120, dielectric medium waveguide 106 includes the tabular ripple for being arranged on the top of semiconductor substrate 102
Lead.In certain embodiments, dielectric medium waveguide 106 can have the cross section of the substantial rectangular comprising height h and width w.
In some embodiments, height h can be at approximate 100nm between approximate 2 μm.In some other embodiments,
Height h can be at approximate 100nm between approximate 20 μm.In certain embodiments, width w can be at approximate 5 times
Height h between approximate 15 times of height h.In some other embodiments, width w can be at approximate 5 times of height h
Between approximate 50 times of height h.In certain embodiments, dielectric medium waveguide 106 can have multiple sloped sidewalls, incline
Oblique side wall provides the upside-down trapezoid cross section (having the increased width with height increase) of dielectric medium waveguide 106.
In certain embodiments, dielectric medium waveguide 106 can include more than or equal to approximate 4 dielectric constant (that is, electric capacity
Rate), and the dielectric constant of ILD materials 104 is smaller than 4.Dielectric medium waveguide 106 with larger dielectric constant to be introduced to Jie
Electromagnetic radiation in electric matter waveguide 106 is accordingly totally internally reflected constraint in dielectric medium waveguide 106, so as to by the self-driven electricity of electromagnetic radiation
Road 108 is directed to receiving circuit 110.In certain embodiments, dielectric medium waveguide 106 can include silicon nitride (SiN) or carborundum
(SiC).In certain embodiments, ILD materials 104 can include silica (SiO2).In other embodiments, ILD materials 104
Low dielectric constant dielectric materials can be included, for example, silica, the silica of doped carbon, the porous silica of doping fluorine
Or similar material.
Fig. 2 illustrates some embodiments of the cross-sectional view comprising the integrated chip 200 through integrating dielectric medium waveguide.
Integrated chip 200 includes silicon substrate 202, and silicon substrate 202 includes drive circuit 204 and receiving circuit 206.Driving
Circuit 204 include the first MOS transistor, the first MOS transistor have be coupled to input signal IN the first source region (S1),
First drain region (D1) and first grid region (G1).Receiving circuit 206 includes the second MOS transistor, the second MOS transistor
With the second source region (S2), the second drain region (D2) and the second grid region for being coupled to the second coupling element 210
(G2)。
During operation, drive circuit 204 is configured to the first drain region (D1) place and produced based on input signal IN
First electric signal S1.Because silicon is not direct gap material, therefore the frequency of the first electric signal S1 produced by drive circuit 204 is not
In visible spectrum (because silicon is indirect gap material, therefore the release during electrons and holes are combined (recombination)
Energy is converted mainly into phonon, opposite with the direct gap material for producing the photon in spectrum).First electric signal S1 makes on first
Portion electrode 208b is produced from the first upper electrode 208b and extends out to the first lower electrode 208a's through dielectric medium waveguide 106
Electric field.Electric field makes the electromagnetic radiation corresponding to the first electric signal S1 be coupled in dielectric medium waveguide 106.
Coupled electromagnetic radiation is directed to the second coupling element 210 by dielectric medium waveguide 106.Second coupling element 210 is passed through
Configuration will be provided to reception so that electromagnetic radiation is coupled into the second electric signal S2, the second electric signal S2 from dielectric medium waveguide 106
The second grid region (G2) of circuit 206 and it is equivalent to the first electric signal S1.
Although the first electric signal S1 and the second electric signal S2 can have the frequency of the frequency less than visible spectrum, due to electricity
The frequency range that magnetic radiation can be transmitted by dielectric medium waveguide 106 is wider, therefore the first electric signal S1 and the second electric signal S2 can provide larger
Data transfer rate.For example, dielectric medium waveguide 106 can provide many frequency ranges more ten times greater than the frequency range of visible spectrum, from
And cause the data transfer rate of dielectric medium waveguide 106 can be more than 10 gigabits/second.This data transfer rate can be passed in experience
Ultrahigh speed (ultra-high- is provided on a silicon substrate and/or in the encapsulation containing silicon substrate under the high-frequency of the high loss of defeated line
speed；UHS) interconnect.
In certain embodiments, the first coupling element 208 can include the be arranged on the opposite side of dielectric medium waveguide 106
A pair of metal structures (for example, micro-strip).For example, the first coupling element 208 can include the bottom table along dielectric medium waveguide 106
The first lower electrode 208a (for example, in first metal interconnecting layer) that face is set and along the top surface of dielectric medium waveguide 106
The the first upper electrode 208b (for example, in second metal interconnecting layer) set.First lower electrode 208a is connected to first and connect
Ground terminal 209a, and the first upper electrode 208b is connected to drive circuit 204 by the first metal transmission line 207.First metal is passed
Defeated line 207 provides the upper electrode 208b of signal driving circuit 204 to the first wide transmission of wideband.In certain embodiments,
One upper electrode 208b can be included in the first metal transmission line 207.
Second coupling element 210 can include second pair of metal structure being arranged on the opposite side of dielectric medium waveguide 106.Lift
For example, the second coupling element 210 can include the second lower electrode 210a set along the basal surface of dielectric medium waveguide 106
(for example, in first metal interconnecting layer) and along dielectric medium waveguide 106 top surface set the second upper electrode 210b (examples
Such as, in the second metal interconnecting layer).Second lower electrode 210a is connected to the second earth terminal 209b, and the second upper electrode
210b is connected to receiving circuit 206 by the second metal transmission line 211.First pair of metal structure and second pair of metal structure are lateral
Separated space S, so that lower electrode 208a and lower electrode 210a and upper electrode 208b and upper electrode 210b is along dielectric
One length of matter waveguide 106 is discontinuous.In certain embodiments, the magnitude of space S can be micron to tens of milliseconds.
In certain embodiments, ground shield element 212 is vertically positioned between dielectric medium waveguide 106 and silicon substrate 202.
Ground shield element 212 is configured to shield dielectric medium waveguide 106 from dry caused by the signal of generation in silicon substrate 202
Disturb, vice versa.The interference caused by shielding dielectric medium waveguide 106 from the signal of generation in silicon substrate 202, from silicon substrate
The noise of plate 202 will be not coupled into dielectric medium waveguide 106, and the efficiency of dielectric medium waveguide 106 is improved whereby.
Fig. 3 illustrates some embodiments of the top view comprising the integrated chip 300 through integrating dielectric medium waveguide, through integrating
Dielectric medium waveguide has one or more tapering transition zones 312 and/or 314.
Integrated chip 300 includes the first coupling element 302 and the second coupling element 304, the first coupling element 302 and the
Two coupling elements 304 are respectively comprising the microstrip line 306 and microstrip line 308 for being arranged on the top of dielectric medium waveguide 310.Microstrip line 306
And microstrip line 308 is configured to energy coupling described above into dielectric medium waveguide 310 and is coupled out dielectric medium waveguide
310。
In certain embodiments, dielectric medium waveguide 310 can include one or more tapered distal ends, this one or more tapered distal end
With being gradually reduced in the transitional region of certain length (along direction 318) (for example, from the first width to the second narrower width
Degree) width w (along direction 316).For example, dielectric medium waveguide 310 is included to have and reduced in First Transition region 312
Width the first tapered distal end and the second tapered distal end with the width reduced in the second transitional region 314.
The tapered distal end of dielectric medium waveguide 106 is configured to by reduction microstrip line 306 and/or microstrip line 308 and dielectric
Radiation reflective between matter waveguide 310 increases electromagnetic radiation in microstrip line 306 and/or microstrip line 308 and dielectric medium waveguide 310
Between the efficiency that couples.For example, tapering transition zone changes the electromagnetic radiation angle interactive with the side wall of dielectric medium waveguide 106
Degree, increases coupling of the electromagnetic radiation between microstrip line 306 and/or microstrip line 308 and dielectric medium waveguide 310 (due to complete whereby
Internal reflection is the function that the angle on surface is incided in electromagnetic radiation).
In certain embodiments, microstrip line 306 and microstrip line 308 also or can alternatively have tapered width, to enter one
Coupling efficiency between step the first coupling element 302 of increase and the second coupling element 304 and dielectric medium waveguide 310.It is a little real herein
Apply in example, microstrip line 306 and microstrip line 308 have to be reduced (for example, wide from first in transitional region 312 and transitional region 314
Spend to the second narrower width) width.In certain embodiments, the tapered width of microstrip line 306 and microstrip line 308 can be in length
Above different from the tapered width of dielectric medium waveguide 106 (that is, with various sizes of transitional region).
Fig. 4 is illustrated comprising the multiple integrated chips through integrating dielectric medium waveguide for being configured to parallel transmission electromagnetic radiation
Some embodiments of 400 top view.
Integrated chip 400 includes the multiple dielectric medium waveguides being arranged between drive circuit 402 and receiving circuit 414
408a~408c.In certain embodiments, multiple dielectric medium waveguide 408a~408c can be arranged parallel to each other with entity Shangdi.
In some embodiments, multiple dielectric medium waveguide 408a~408c can adjoin one another.In other embodiments, multiple dielectric medium waveguides
408a~408c can be spatially separated from each other.
Drive circuit 402 includes the multiple single driving element 402a for being configured to produce the first electric signal S1'
~402c.First electric signal S1' is to be supplied to microstrip line 404a~404c in a parallel manner, and microstrip line 404a~404c is by
One electric signal S1' is coupled in multiple dielectric medium waveguide 408a~408c of parallel transmission signal and is used as electromagnetic radiation.Due to
One electric signal S1' is to transmit in a parallel manner, therefore each in multiple dielectric medium waveguide 408a~408c is transmittable smaller
Amplitude signal, further reduces the loss (example of micro-strip 404a~between 404c and multiple dielectric medium waveguide 408a~408c whereby
Such as, the smaller amplitude signal received by multiple driving element 402a~402c outputs and by multiple receiving element 414a~414c
S1' will be such that coupling element 406 and coupling element 410 undergoes compared with small loss).
Fig. 5 A are illustrated comprising the integration through integrating dielectric medium waveguide being arranged in last part technology (BEOL) metallization stack
Some embodiments of the cross-sectional view of formula chip 500.
Integrated chip 500 includes the drive circuit 502 and receiving circuit 504 being arranged in silicon substrate 202.Drive circuit
502 include the first MOS transistor, and the first MOS transistor has to be separated by first passage region with the first drain region (D)
The first source region (S).First grid region overlay first passage region.Receiving circuit 504 includes the second MOS transistor,
Second MOS transistor has the second source region (S) separated by second channel region with the second drain region (D).The
Two area of grid covering second channel region.
BEOL metallization stacks include the multiple metal interconnecting layers being arranged in the ILD materials of covering silicon substrate 202.One
In a little embodiments, BEOL metallization stacks can metal line layer M1~M3 (being configured to provide laterally attached) and via layer V0~
Between V2 (being configured to provide vertical connection) alternately.In certain embodiments, first through hole layer V0 can include tungsten (W), and remain
Remaining metal interconnecting layer V1~V2 and M1~M3 can include copper (Cu) and/or aluminium (Al).
First coupling element 520 includes the first lower electrode 520a for being arranged in the second metal line layer M2 and is arranged on the
The first upper electrode 520b in three metal line layer M3.First lower electrode 520a be grounded, and the first upper electrode 520b by
Multiple metal interconnecting layers (V2, M2, V1, M1 and V0) are coupled to the first drain region of the first MOS transistor.Second coupling element
522 include the second lower electrode 522a being arranged in the second metal line layer M2 and be arranged on the 3rd metal line layer M3 second
Upper electrode 522b.Second lower electrode 522a be grounded, and the second upper electrode 522b by multiple metal interconnecting layers (V2, M2,
V1, M1 and V0) it is coupled to the second grid region of the second MOS transistor.In certain embodiments, dielectric medium waveguide 514 is included
The dielectric material in the second via layer V2 is arranged on, the second via layer V2 is vertically disposed at the second metal line layer M2 and the 3rd gold medal
Between category line layer M3.
In certain embodiments, shielding element 524 is vertically arranged between dielectric medium waveguide 514 and silicon substrate 202.Screen
Cover multiple grounded metal line 524a~524d that element 524 includes parallel arrangement.In certain embodiments, multiple grounded metal lines
524a~524d is arranged on the first metal line layer M1.Shielding element 524 is configured to shielding dielectric medium waveguide 514 from damaging
The silicon substrate 202 of evil property influences, the loss of signal for preventing dielectric medium waveguide 514 from being transmitted whereby.
Although Fig. 5 A illustrate dielectric medium waveguide 514 and are being vertically disposed at positioned at the second metal line layer M2 and the 3rd metal wire
On the second via layer V1 between the first coupling element 520 and the second coupling element 522 on layer M3, but it will be appreciated that disclosed
This little position that is not limited in BEOL metallization stacks of dielectric medium waveguide 514.On the contrary, the coupling of dielectric medium waveguide 514 and first
The coupling element 522 of element 520 and second is closed to may be provided at the diverse location in BEOL metallization stacks.
Fig. 5 B are illustrated comprising the integrated chip 526 through integrating dielectric medium waveguide being arranged in BEOL metallization stacks
The 3-D view of some alternate embodiments.Integrated chip 526 include from opposite side extend to the lower section of dielectric medium waveguide 514 and
The lower electrode 520a and lower electrode 522a of top position and upper electrode 520b and upper electrode 522b.
Fig. 6 illustrates the three-dimensional (3D) with the integrated chip 600 for being configured to the dielectric medium waveguide for transmitting differential signal
Some embodiments of view.The certain amount performance advantages better than single-ended signal can be provided using differential signal.For example,
Compared with single-ended signal, differential signal anti-interference (for example, interference from external circuit) is more sane and produces less even number
Harmonic wave.
Integrated chip 600 includes the differential drive circuit 602 and differential received circuit 612 being arranged in silicon substrate 202.
Differential drive circuit 602 is configured to receive the first input signal SIN+And the second complementary input signal SIN-(that is, second is defeated
Enter signal SIN-With the first input signal SIN+Symmetrically) and based on the first input signal SIN+And the second complementary input signal SIN-Production
Raw differential signal, this differential signal has the first output node OUT1The first transmitted signal component S at place1And second output node
OUT2The second complementary transmitted signal component S at place2(that is, secondary signal has the first transmitted signal component S1Complementary).
By transmission line 603a and transmission line 603b the first transmitted signal component S is provided to differential transfer coupling element 6051
And the second complementary transmitted signal component S2.Differential transfer coupling element 605 includes the first transmission electrode 604 and the second transmission electricity
Pole 606.First transmission electrode 604 and the second transmission electrode 606 be on dielectric medium waveguide 106 it is symmetrical (that is, electrode mirror image
Shape/pattern) conductive structure (for example, metal structure).First transmission electrode 604 positions along dielectric medium waveguide 106
Side and be configured to self difference drive circuit 602 receive the first transmitted signal component S1.Second transmission electrode 606 position along
Second side of dielectric medium waveguide 106 and be configured to self difference drive circuit 602 receive complementation the second transmitted signal component S2。
Dielectric medium waveguide 106 is configured to the first signal S1And the second transmission signal S2Transmit to differential received and couple member
Part 609, differential received coupling element 609 includes the first receiving electrode 608 and second positioned at the opposite side of dielectric medium waveguide 106
Receiving electrode 610.First receiving electrode 608 and the second receiving electrode 610 on dielectric medium waveguide 106 it is symmetrical (that is, electrode mirror
Shape/pattern of picture).First receiving electrode 608 and the second receiving electrode 610 are configured to extract the from dielectric medium waveguide 106
One receives component of signal S1' and the second reception component of signal S2'.By the first transmission line 611a to the of differential received circuit 612
One input node IN1There is provided first and receive component of signal S1'.By the second transmission line 611b to the second of differential received circuit 612
Input node IN2There is provided second and receive component of signal S2'.Differential received circuit 612 is configured to from received component of signal
Produce output signal SOUT+And SOUT-, differential signal is transmitted in dielectric medium waveguide 106 whereby.
Fig. 7 illustrates the integration for including the differential drive circuit 702 and differential received circuit 704 being arranged in silicon substrate 202
Some embodiments of the cross-sectional view of formula chip 700.
Differential drive circuit 702, which is configured to produce, has the first transmitted signal component S1And the second complementary transmission signal
Component S2Differential signal.In certain embodiments, differential drive circuit is brilliant comprising the first MOS transistor 702a and the 2nd MOS
Body pipe 702b.First MOS transistor 702a includes the first source region (S for being connected to earth terminal1), be connected to the first output section
Put and be connected to drain bias VDD1First drain region (the D of (via RF choke 702c)1), and it is connected to the first input letter
Number SIN+And it is connected to grid bias VDD2First grid region (the G of (via RF choke 702d)1).Second MOS transistor
702b includes the second source region (S for being connected to earth terminal2), be connected to the second output node and be connected to drain bias VDD1
Second drain region (the D of (via RF choke 702c)2), and it is connected to the second input signal SIN-And it is connected to grid bias
VDD2Second grid region (the G of (via RF choke 702d)2)。
During operation, as the second input signal SIN-First input signal S when closing the second MOS transistor 702bIN+Will
Open the first MOS transistor 702a, or vice versa it is as the same.When opening the first MOS transistor 702a, the first MOS transistor 702a
The first transmitted signal component S will be driven1It is low, and the second MOS transistor 702b closed will drive the second complementary transmission signal
Component S2It is high.Because silicon is not direct gap material, therefore the first transmitted signal component S produced by differential drive circuit 7021And
Second transmitted signal component S2Frequency not in visible spectrum (because silicon is indirect gap material, therefore multiple in electrons and holes
The energy discharged during conjunction is converted mainly into phonon, opposite with the direct gap material for producing the photon in spectrum).First transmission
Component of signal S1And the second transmitted signal component S2Differential transfer coupling element 605 is produced to be coupled in dielectric medium waveguide 106
Electric field.
Coupled electromagnetic radiation is directed to the first receiving electrode 608 and the second receiving electrode by dielectric medium waveguide 106
610 differential received coupling element 609.Differential received coupling element 609 is configured to electromagnetic radiation from dielectric medium waveguide 106
Coupled to being equivalent to the first transmitted signal component S1And the second transmitted signal component S2First receive component of signal S1' and second
Receive component of signal S2'.First, which is provided, to differential received circuit 704 receives component of signal S1' and the second reception component of signal S2’。
In certain embodiments, differential received circuit 704 includes the 3rd MOS transistor 704a and the 4th MOS transistor 704b.3rd
MOS transistor 704a includes the 3rd source region (S for being connected to earth terminal3), be connected to the first receiving electrode 608 and be connected to
Grid bias VDD33rd area of grid (the G of (via RF choke 704c)3), and it is connected to drain bias VDD4(gripped via RF
Stream device 704d) and be configured to provide the first output signal SOUT+The 3rd drain region (D3).4th MOS transistor 704b bags
Containing the 4th source region (S for being connected to earth terminal4), be connected to the second receiving electrode 610 and be connected to grid bias VDD3(warp
By RF choke 704c) the 4th area of grid (G4), and it is connected to drain bias VDD4(via RF choke 704d) and through matching somebody with somebody
Put to provide the second output signal SOUT-The 4th drain region (D4)。
Although MOS transistor 704a~704d is schematically shown as one-transistor element, it will be appreciated that, MOS transistor can be included
The array of transistor, the array of transistor includes multiple transistor units (for example, FinFET elements) of parallel arrangement.Citing and
Speech, the first MOS transistor 702a can include hundreds of transistor units.Furthermore, it will be understood that, depicted differential driving electricity in Fig. 7
Road 702 and the non-limiting examples that differential received circuit 704 is the difference channel that can be used to send and/or receive differential signal.
In other embodiments, the known alternative difference channel applied for high-speed cmos of general technology person can be used to produce or connect
Astigmat sub-signal.
Fig. 8 illustrates some for including the integrated chip 800 through integrating dielectric medium waveguide for being coupled to differential coupling element
The 3-D view of embodiment.
Integrated chip 800 includes differential transfer coupling element, and differential transfer coupling element is included along dielectric medium waveguide
More than first transmission electrode 804 that 106 lower surface is set and set along the upper surface of dielectric medium waveguide 106 more than second
Transmission electrode 806.More than first transmission electrode 804 includes the multiple conical by its shape 804a~804c interconnected by wire 805.Second
Multiple transmission electrodes 806 include the multiple conical by its shape 806a~806c interconnected by wire 807.In certain embodiments, it is multiple
Conical by its shape 804a~804c and 806a~806c can include triangular shaped.More than first transmission electrode 804 is on more than second
Individual transmission electrode 806 is symmetrical, using cause shape/pattern of more than first transmission electrode 804 and more than second transmission electrode 806 as
Mirror image.
More than first transmission electrode 804 (via transmission line 803a) is coupled to the first output of differential drive circuit 802, poor
The first output of drive circuit 802 is divided to be configured to each transmission letter of offer first into more than first transmission electrode 804
Number component S1.More than second transmission electrode 806 (via transmission line 803b) is coupled to the second output of differential drive circuit 802,
Each offer second that second output of differential drive circuit 802 is configured into more than second transmission electrode 806 is transmitted
Component of signal S2.Due to the first transmitted signal component S1And the second transmitted signal component S2Drive transmission electrode 804 and transmission electrode
Each in 806, therefore the output of the electromagnetic signal of each electrode come in self-electrode will be relevant, whereby in dielectric medium waveguide 106
The intensity of interior constructive interference and the improvement electromagnetic signal of transmission in dielectric medium waveguide 106.
Integrated chip 800 further includes differential received coupling element, and differential received coupling element is included along dielectric
More than first receiving electrode 808 that the lower surface of matter waveguide 106 is set and set along the upper surface of dielectric medium waveguide 106 the
More than two receiving electrode 810.More than first receiving electrode 808 and more than second receiving electrode 810 include multiple conical by its shape.The
The first input that more than one receiving electrode 808 is configured to differential received circuit 812 provides first and receives component of signal S1',
And the second input that more than second receiving electrode 810 is configured to differential received circuit 812 provides the second reception component of signal
S2'。
Fig. 9 illustrates some for including the integrated chip 900 through integrating dielectric medium waveguide for being coupled to differential coupling element
The 3-D view of embodiment.
Integrated chip 900 includes differential transfer coupling element, and differential transfer coupling element is included along dielectric medium waveguide
More than first transmission electrode 902 that 106 lower surface is set and set along the upper surface of dielectric medium waveguide 106 more than second
Transmission electrode 904.More than first transmission electrode 902 and more than second transmission electrode 904 are included respectively has various sizes of electricity
Pole.For example, transmission electrode 902b extends to the Edge Distance d beyond transmission electrode 902a and transmission electrode 902c.It is different
The different sizes of transmission electrode 904 allow electrode to concentrate on radiation at the diverse location in dielectric medium waveguide 106.Citing and
Speech, transmission electrode 902b large-size by make radiation concentrate on dielectric medium waveguide 106 center (that is, dielectric medium waveguide 106
The amplitude of interior radiation will be bigger than the edge of waveguide in the center of waveguide).
Integrated chip 900 further includes differential received coupling element, and differential received coupling element is included along dielectric
More than first receiving electrode 906 that the lower surface of matter waveguide 106 is set and set along the upper surface of dielectric medium waveguide 106 the
More than two receiving electrode 908.More than first receiving electrode 906 and more than second receiving electrode 908 are included respectively has different chis
Very little electrode.
Figure 10 illustrates some realities for including the integrated chip through integrating dielectric medium waveguide for being coupled to differential coupling element
Apply the 3-D view of example.
Integrated chip 1000 includes differential drive circuit 1002 and differential received circuit 1010.Differential drive circuit 1002
It is connected to more than first transmission electrode 1004 for being arranged on the lower section of dielectric medium waveguide 106 and is arranged on the top of dielectric medium waveguide 106
More than second transmission electrode 1006.More than first transmission electrode 1004 is electrically decoupled, and more than second transmission electrode
1006 electrically decouple.
Differential drive circuit 1002 includes multiple single differential drive circuit 1002a~1002d.In some embodiments
In, each in multiple single differential drive circuit 1002a~1002d can include the list of the transistor unit of parallel arrangement
Only array.Single differential drive circuit 1002a~1002d is configured to drive one in more than first transmission electrode 1004
A transmission electrode 1006 in transmission electrode 1004 and more than second transmission electrode 1006, to cause more than first transmission electrode
1004 or more than second transmission electrode 1006 in each driven by single drive circuit.For example, implement at some
In example, single differential drive circuit 1002a~1002d includes the first transistor and second transistor element respectively, and first is brilliant
Body pipe has one for being coupled to the first input signal SIN+ first grid and being coupled in more than first transmission electrode 1004
First drain electrode of transmission electrode 1004, second transistor element has the second grid and coupling for being coupled to the second input signal SIN-
Second drain electrode of a transmission electrode 1006 being connected in more than second transmission electrode 1006.
Similarly, differential received circuit 1010 includes multiple single differential received circuit 1010a~1010d.Individually
Differential received circuit 1010a~1010d be configured to from a receiving electrode 1012 in more than first receiving electrode 1012 and
A receiving electrode 1014 in more than second receiving electrode 1014 receives differential signal.For example, in certain embodiments,
Single differential received circuit 1010a~1010d includes first crystal tube elements and second transistor element, first crystal respectively
Tube elements have the first grid of a receiving electrode 1012 being coupled in more than first receiving electrode 1012 and are coupled to the
One output signal SOUT+The first drain electrode, second transistor element, which has, is coupled to one in more than second transmission electrode 1006
The second grid of transmission electrode 1006 and it is coupled to the second output signal SOUT-Second drain electrode.
Figure 11 illustrates the 3-D view of some embodiments of the integrated chip 1100 comprising dielectric medium waveguide, dielectric medium ripple
Lead with the differential coupling element being arranged in BEOL metallization stacks.
Integrated chip 1100 includes the differential drive circuit 1102 and differential received circuit being arranged in silicon substrate 202
1104.Differential drive circuit 1102 has logical by first comprising the first MOS transistor 1102a, the first MOS transistor 1102a
Road region and with the first drain region (D1) separation the first source region (S1).First grid region (G1) covering first passage
Region.Differential drive circuit 1102 further comprising the second MOS transistor 1102b, the second MOS transistor 1102b have by
Second channel region and with the second drain region (D2) separation the second source region (S2).Second grid region (G2) covering the
Two passage areas.Differential received circuit 1104 include the 3rd MOS transistor 1104a, the 3rd MOS transistor 1104a have by
Third channel region and the 3rd drain region (D3) separation the 3rd source region (S3).3rd area of grid (G3) covering the 3rd
Passage area.Differential received circuit 1104 further includes the 4th MOS transistor 1104b, and the 4th MOS transistor 1104b has
By fourth lane region and the 4th drain region (D4) separation the 4th source region (S4).4th area of grid (G4) covering
Fourth lane region.
Differential transfer coupling element 520' includes the first transmission electrode 520a' being arranged in the second metal line layer M2 and set
Put the second transmission electrode 520b' in the 3rd metal line layer M3.First transmission electrode 520a' is by multiple metal interconnecting layers
(V2, M2, V1, M1 and V0) is coupled to the first MOS transistor 1102a the first drain region (D1), and the first upper electrode
520b' is coupled to the second MOS transistor 1102b the second drain region by multiple metal interconnecting layers (V2, M2, V1, M1 and V0)
Domain (D2)。
Differential received coupling element 522' includes the first receiving electrode 522a' being arranged in the second metal line layer M2 and set
Put the second receiving electrode 522b' on the 3rd metal line layer M3.First receiving electrode 522a' is by multiple metal interconnecting layers
(V2, M2, V1, M1 and V0) is coupled to the 3rd MOS transistor 1104a the 3rd area of grid (G3), and the second receiving electrode
522b' is coupled to the 4th area of grid of the 4th MOS transistor by multiple metal interconnecting layers (V2, M2, V1, M1 and V0)
(G4)。
Figure 12 illustrates some embodiments to form the method 1200 comprising the integrated chip through integrating dielectric medium waveguide
Flow chart.
Although disclosed method (for example, method 1200, method 1300 and method 2000) is illustrated and is described as herein
Sequence of operations or event, but it will be appreciated that, this depicted a little operation or the order of event should not be illustrated as limited significance.Citing
For, in addition to that a little order for illustrating and/or describing herein, certain operations can in different order be sent out with other operations or event
Give birth to and/or occur simultaneously.In addition, the operation that simultaneously not all is illustrated is for implementing one or more aspects described herein or embodiment
To be required.In addition, one or more operations in operation depicted in this paper can be in one or more individually operations and/or in the stage
Perform.
There is provided the semiconductor substrate for including drive circuit and receiving circuit at 1202.In certain embodiments, semiconductor
Substrate can include indirect gap semiconductor material, for example：Silicon.
At 1204, dielectric medium ripple is formed at the position that (interlayer dielectric) the ILD materials for covering semiconductor substrate are surrounded
Lead.
At 1206, the first coupling element and the second coupling element are formed on the opposing end portions of dielectric medium waveguide.First
Coupling element and the second coupling element include the metal structure being arranged on the opposite side of dielectric medium waveguide, this little metal structure warp
Configure using respectively by the first electric signal driving circuit be coupled to dielectric medium waveguide as visible spectrum outside electromagnetic radiation and
Electromagnetic radiation is coupled to the second electric signal provided to receiving circuit from dielectric medium waveguide.
Figure 13 illustrate to be formed comprising be arranged in last part technology (BEOL) metallization stack through integrating dielectric medium waveguide
The flow chart of some embodiments of the method 1300 of integrated chip.
There is provided the silicon substrate for including drive circuit and receiving circuit at 1302.In certain embodiments, drive circuit and
Receiving circuit includes the MOS transistor being arranged in silicon substrate.
At 1304, first (interlayer dielectric) ILD layer of covering silicon substrate is patterned to more than first opening.
At 1306, the first metal material is formed in more than first openings, to form contact drive circuit and receive electricity
The first through hole layer on road.
At 1308, the second ILD layer of the first ILD layer of covering be patterned to comprising multiple shielding element openings and
More than the second of more than first metal wire trench opening.
At 1310, the second metal material is formed in multiple shielding element openings and more than first metal wire trench.
Multiple grounded metals that the formation of the second metal material includes the parallel arrangement in the second ILD layer are formed in multiple shielding element openings
The shielding element of line.
At 1312, the 3rd ILD layer of the second ILD layer of covering is patterned to more than the 3rd opening.More than 3rd
Opening includes the first lower electrode opening and the second lower electrode opening.First lower electrode opening and the second lower electrode opening
With it is laterally separated each other.
At 1314, in the first lower electrode opening and the second lower electrode opening formed the 3rd metal material, with
The first lower electrode and the second lower electrode are formed in 3rd ILD layer.
At 1316, the 4th ILD layer of the 3rd ILD layer of covering is patterned to dielectric medium waveguide openings.Dielectric medium
Waveguide openings, which have, to be exposed the first end of the first lower electrode to the open air and exposes the second end of the second lower electrode to the open air.
At 1318, dielectric material is formed in dielectric medium waveguide openings, to form dielectric medium ripple in the 4th ILD layer
Lead.The dielectric constant of dielectric material is bigger than the dielectric constant of ILD layer around.
At 1320, the 4th ILD layer is patterned with more than second through hole of formation in the 4th ILD layer.
At 1322, the 4th metal material is formed in more than second through hole.
At 1324, the 5th ILD layer of the 4th ILD layer of covering is patterned to the first upper electrode opening and second
Upper electrode opening.First upper electrode opening and the second upper electrode opening with it is laterally separated each other and expose dielectric medium waveguide to the open air
Opposing end portions.
At 1326, in the first upper electrode opening and the second upper electrode opening formed fifth metal material, with
The first upper electrode and the second upper electrode are formed in 5th ILD layer.
Figure 14~Figure 19 illustrates the cross section that displaying forms the method comprising the integrated chip through integrating dielectric medium waveguide
Some embodiments of figure.Although describing Figure 14~Figure 19 on method 1300, it will be appreciated that, the knot disclosed in Figure 14~Figure 19
Structure not limited to this method, on the contrary can be independently as the structure unrelated with the method.
Figure 14 illustrates some embodiments of the cross-sectional view 1400 of the integrated chip corresponding to operation 1302.
There is provided silicon substrate 202 as shown in cross-sectional view 1400.Silicon substrate 202 includes drive circuit 502 and receiving circuit
504.In certain embodiments, drive circuit 502 and receiving circuit 504 include the MOS transistor being arranged in silicon substrate 202.
Figure 15 illustrates the cross-sectional view 1500 and cross-sectional view 1506 of the integrated chip corresponding to operation 1304~1306.
As shown in cross-sectional view 1500, the first ILD layer 506 is formed in the top of silicon substrate 202.First ILD layer 506 can be wrapped
Containing the dielectric layer with low dielectric constant deposited by gas phase deposition technology (for example, physical vapour deposition (PVD), chemical vapor deposition etc.).
In some embodiments, the dielectric constant of the first ILD layer 506 is smaller than 3.9.
First ILD layer 506 is optionally exposed to the first etchant 1502.First etchant 1502 is configured to selectivity
Ground etches more than first openings 1504 that the first ILD layer 506 extends through the first ILD layer 506 with formation.More than first opening
1504 expose the drain electrode of drive circuit 502 and receiving circuit 504 to the open air.In certain embodiments, the first etchant 1502 can be comprising dry
Formula etchant, dry etch has bag fluorine containing species (for example, CF4, CHF3, C4F8 etc.) etch chemistries.At some
In embodiment, etch chemistries can further include such as oxygen or hydrogen.In other embodiments, the first etchant 1502 can be wrapped
Containing wet etchant, wet etchant includes hydrofluoric acid (HF).
As shown in cross-sectional view 1506, the first metal material 1508 is formed in more than first openings 1504.At some
, can be by gas phase deposition technology the first metal material 1508 of formation in embodiment.In certain embodiments, the first metal material
1508 can include tungsten (W).In certain embodiments, diffused barrier layer (not illustrating) can be before the first metal material 1508 be formed
Deposition is into more than first openings 1504.In various embodiments, diffused barrier layer can include titanium nitride (TiN), tantalum nitride
(TaN), hafnium nitride (HfN) etc..
Figure 16 illustrates the cross-sectional view 1600 and cross-sectional view 1608 of the integrated chip corresponding to operation 1308~1310.
As shown in cross-sectional view 1600, the formation the in the top of the first ILD layer 506 (for example, by gas phase deposition technology)
Two ILD layers 508 (for example, dielectric layer with low dielectric constant).Second ILD layer 508 is optionally exposed to the (example of the second etchant 1602
Such as, CF4, CHF3, C4F8, HF etc.), the second etchant 1602 is configured to be etched selectively to the second ILD layer 508 to form
More than two opening, more than second opening includes more than first via openings 1604 and laterally disposed from multiple via openings 1604
Multiple shielding element openings 1606.Multiple shielding element openings 1606 include the metal valley extended parallel to each other.
As shown in cross-sectional view 1608, the shape in more than first via openings 1604 and multiple shielding element openings 1606
Into the second metal material 1610.In certain embodiments, depositing operation can be used in more than first via openings 1604 and multiple
Crystal seed layer is formed in shielding element opening 1606.Follow-up shikishima plating process (for example, electroplating technology, electroless-plating technique) can be used to shape
More than first via openings 1604 and the thickness of multiple shielding element openings 1606 are extremely filled into the second metal material.In some realities
Apply in example, the second metal material 1610 can include copper (Cu).Cmp (chemical mechanical
polishing；CMP) technique can be used to remove the second excessive metal material 1610 from the top surface of the second ILD layer 508.
Figure 17 illustrates the cross-sectional view 1700 and cross-sectional view 1702 of the integrated chip corresponding to operation 1312~1314.
As shown in cross-sectional view 1700, the 3rd ILD layer 510 is formed to the second ILD layer 508.3rd ILD layer 510 is selected
The 3rd etchant 1702 (for example, CF4, CHF3, C4F8, HF etc.) is exposed to selecting property, the 3rd etchant 1702 is configured to erosion
The 3rd ILD layer 510 is carved to form more than the 3rd opening 1704.In certain embodiments, more than the 3rd opening 1704 includes through hole
And the metal wire trench of covering.The basal surface of through hole from the 3rd ILD layer 510 extends perpendicularly to the basal surface of metal valley, gold
Category groove extends to the top surface of the 3rd ILD layer 510.
As shown in cross-sectional view 1706, the 3rd metal material 1708 is formed in more than the 3rd opening 1704, to be formed
Second via layer V1 and the second metal line layer M2 of covering.Second metal line layer M2 is included under the first lower electrode 520a and second
Portion electrode 522a.First lower electrode 520a is laterally separated by the 3rd ILD layer 510 and the second lower electrode 522a.At some
In embodiment, the 3rd metal material 1708 (for example, copper) can be by above-described depositing operation, follow-up shikishima plating process and CMP
Process deposits.
Although Figure 17 is illustrated using dual-damascene technics formation the second via layer V1 and the second metal line layer M2, general technology
It is individual to will be appreciated that in an alternative embodiment, list mosaic technology formation the second via layer V1 and the second metal line layer M2 can be used.
In this little embodiment, the through hole that the chosen property etching of the first dielectric layer is subsequently filled with being formed.Then on the first dielectric layer
It is square into the second dielectric layer.The chosen property of second dielectric layer etches to form metal valley.
Figure 18 illustrates the cross-sectional view 1800 and cross-sectional view 1802 of the integrated chip corresponding to operation 1316~1322
Some embodiments.
As shown in cross-sectional view 1800, the 4th ILD layer 512 is formed in the top of the 3rd ILD layer 510.4th ILD layer 512
The 4th etchant 1802 (for example, CF4, CHF3, C4F8, HF etc.) is optionally exposed to, the 4th etchant 1802 is configured to
The 4th ILD layer 512 is etched to form dielectric medium waveguide openings 1804.Dielectric medium waveguide openings 1804 are included from the first bottom of covering
Electrode 520a first position extends laterally to the oblong openings of the second lower electrode 522a of the covering second place.
As shown in cross-sectional view 1806, dielectric material 1808 is formed in dielectric medium waveguide openings 1804.Dielectric material
The 1808 projecting ILD layers of the dielectric constant included (for example, ILD layer 510 and ILD layer 512).In certain embodiments, it can borrow
Dielectric material 1808 is formed to filling dielectric medium waveguide openings 1804 by gas phase deposition technology (for example, PVD, CVD, PE-CVD etc.)
Thickness.Cmp (CMP) technique can be used to remove excessive dielectric material from the top surface of the 4th ILD layer 512
1808。
As shown in cross-sectional view 1810, the 4th ILD layer 512 be optionally exposed to the 5th etchant 1812 (for example,
CF4, CHF3, C4F8, HF etc.), the 5th etchant 1812 is configured to the 4th ILD layer 512 of etching to form more than second through hole
514.More than second through hole 1814 include be arranged on above lower metal layer substantially round via openings (that is, through hole
1814 is main above lower floor second metal layer M2, to provide between the through hole subsequently formed and lower floor second metal layer M2
Contact).More than second through hole 1814 and dielectric medium waveguide openings 1804 it is laterally separated (that is, with more than second through hole 1814
Dielectric medium waveguide openings 1804 are set in identical perpendicular layers).
As shown in cross-sectional view 1816, the 4th metal material 1818 is formed in more than second through hole 1814.At some
In embodiment, the 4th metal material 1818 (for example, copper) can be by above-described depositing operation, follow-up shikishima plating process and CMP
Process deposits.
Figure 19 illustrates the cross-sectional view 1900 and cross-sectional view 1906 of the integrated chip corresponding to operation 1324~1326
Some embodiments.
As shown in cross-sectional view 1900, the 5th ILD layer 518 is formed in the top of the 4th ILD layer 512.5th ILD layer 518
The 6th etchant 1902 (for example, CF4, CHF3, C4F8, HF etc.) is optionally exposed to, the 6th etchant 1902 is configured to
The 5th ILD layer 518 is etched to form more than the 4th openings 1904 comprising the metal valley for extending through the 5th ILD layer 518.
As shown in cross-sectional view 1906, fifth metal material 1908 is formed in more than the 4th opening 1904.At some
In embodiment, fifth metal material 1908 (for example, copper) can be by above-described depositing operation, follow-up shikishima plating process and CMP
Process deposits.Fifth metal material 1908 forms the first upper electrode 520b and the second upper electrode in the 3rd metal line layer M3
522b.First upper electrode 520b is laterally separated by the 5th ILD layer 518 and the second upper electrode 522b.
Figure 20 illustrates the method 2000 to form the integrated chip comprising the dielectric medium waveguide for being coupled to differential coupling element
Some embodiments flow chart.
At 2002, differential drive circuit is formed in silicon substrate.Differential drive circuit, which has, is configured to offer first
First output node of transmitted signal component and the second output node for being configured to provide the second complementary transmitted signal component.
In certain embodiments, differential drive circuit includes the MOS transistor being arranged in silicon substrate.
At 2004, differential received circuit is formed in silicon substrate.Differential received circuit, which has, is configured to reception first
Receive the first input node of component of signal and be configured to receive the second input node that complementary second receives component of signal.
In certain embodiments, differential received circuit includes the MOS transistor being arranged in silicon substrate.
At 2006, the first metal material is formed in more than first openings in the first ILD layer, to form contact difference
The first output node and the second output node of drive circuit are saved with the first input node of differential received circuit and the second input
The first through hole layer of point.
At 2008, more than the second shielding element opening and first formed in the second ILD layer for covering the first ILD layer
The second metal material is formed in multiple metal wire trenchs.The formation of the second metal material is formed in multiple shielding element openings to include
The shielding element of multiple grounded metal lines of parallel arrangement in second ILD layer.
At 2010, the 3rd metal material is formed in the lower electrode opening in the 3rd ILD layer, the is coupled to be formed
First transmission electrode of one output node and the first receiving electrode for being coupled to the first input node.
At 2012, the 4th ILD layer of the 3rd ILD layer of covering is patterned to dielectric medium waveguide openings.Dielectric medium
Waveguide openings, which have, to be exposed the first end of the first transmission electrode to the open air and exposes the second end of the first receiving electrode to the open air.
At 2014, dielectric material is formed in dielectric medium waveguide openings, to form dielectric medium ripple in the 4th ILD layer
Lead.The dielectric constant of dielectric material is bigger than the dielectric constant of ILD layer around.
At 2016, the 4th ILD layer is patterned with more than second through hole of formation in the 4th ILD layer.
At 2018, the 4th metal material is formed in more than second through hole.
At 2020, fifth metal material is formed in the upper electrode opening in the 5th ILD layer for covering the 4th ILD layer
Material, is coupled to the second transmission electrode of the second output node with formation and is coupled to the second receiving electrode of the second input node.
Second transmission electrode and the second receiving electrode with it is laterally separated each other.
Figure 21~Figure 26 illustrates displaying and formed comprising the integration through integrating dielectric medium waveguide for being coupled to differential coupling element
Some embodiments of the cross-sectional view of the method for formula chip.Although describing Figure 21~Figure 26 on method 2000, it will be appreciated that, figure
Structure not limited to this method disclosed in 21~Figure 26, on the contrary can be independently as the structure unrelated with the method.
Figure 21 illustrates some embodiments of the cross-sectional view 2100 of the integrated chip corresponding to operation 2002~2004.
There is provided silicon substrate 202 as shown in cross-sectional view 2100.Differential drive circuit 1102 is formed in silicon substrate 202
And differential received circuit 1104.In certain embodiments, differential drive circuit 1102 can comprising the first MOS transistor 1102a and
Second MOS transistor 1102b, and differential received circuit 1104 can include the first MOS transistor 1104a and the second MOS transistor
1104b.In certain embodiments, source region can be formed into silicon substrate 202 by optionally implant dopant species
And drain region and grid structure is formed above the passage area between source region and drain region using lithography technology,
To form MOS transistor.
Figure 22 illustrates the cross-sectional view 2200 and cross-sectional view 2206 of the integrated chip corresponding to operation 2006.
As shown in cross-sectional view 2200, the first ILD layer 506 is formed in the top of silicon substrate 202.First ILD layer 506 can be wrapped
Containing the dielectric layer with low dielectric constant deposited by gas phase deposition technology (for example, physical vapour deposition (PVD), chemical vapor deposition etc.).The
One ILD layer 506 is optionally exposed to the first etchant 2202.First etchant 2202 is configured to be etched selectively to first
ILD layer 506 extends through more than first openings 2204 of the first ILD layer 506 to be formed.More than first opening 2204 exposes driving to the open air
The drain electrode of circuit 502 and receiving circuit 504.In various embodiments, the first etchant 2202 can include dry etch or wet
Formula etchant.
As shown in cross-sectional view 2206, the first metal material 2208 is formed in more than first openings 2204.At some
, can be by gas phase deposition technology the first metal material 2208 of formation in embodiment.In certain embodiments, the first metal material
2208 can include tungsten (W).In certain embodiments, diffused barrier layer (not illustrating) can be before the first metal material 2208 be formed
Deposition is into more than first openings 2204.In various embodiments, diffused barrier layer can include titanium nitride (TiN), tantalum nitride
(TaN), hafnium nitride (HfN) etc..
Figure 23 illustrates the cross-sectional view 2300 and cross-sectional view 2308 of the integrated chip corresponding to operation 2008.
As shown in cross-sectional view 2300, the formation the in the top of the first ILD layer 506 (for example, by gas phase deposition technology)
Two ILD layers 508 (for example, dielectric layer with low dielectric constant).Second ILD layer 508 is optionally exposed to the (example of the second etchant 2302
Such as, CF4, CHF3, C4F8, HF etc.), the second etchant 2302 is configured to be etched selectively to the second ILD layer 508 to form
More than two opening, more than second opening includes more than first via openings 2304 and laterally disposed from multiple via openings 2304
Multiple shielding element openings 2306.Multiple shielding element openings 2306 include the metal valley extended parallel to each other.
As shown in cross-sectional view 2308, the shape in more than first via openings 2304 and multiple shielding element openings 2306
Into the second metal material 2310.In certain embodiments, depositing operation can be used in more than first via openings 2304 and multiple
Crystal seed layer is formed in shielding element opening 2306.Follow-up shikishima plating process (for example, electroplating technology, electroless-plating technique) can be used to shape
More than first via openings 2304 and the thickness of multiple shielding element openings 2306 are extremely filled into the second metal material.In some realities
Apply in example, the second metal material 2310 can include copper (Cu).Cmp (CMP) technique can be used to from the second ILD layer 508
Top surface remove the second excessive metal material 2310.
Figure 24 illustrates the cross-sectional view 2400 and cross-sectional view 2402 of the integrated chip corresponding to operation 2010.
As shown in cross-sectional view 2400, the 3rd ILD layer 510 is formed to the second ILD layer 508.3rd ILD layer 510 is selected
The 3rd etchant 2402 (for example, CF4, CHF3, C4F8, HF etc.) is exposed to selecting property, the 3rd etchant 2402 is configured to erosion
The 3rd ILD layer 510 is carved to form more than the 3rd opening 2404.In certain embodiments, more than the 3rd opening 2404 includes through hole
And the metal wire trench of covering.The basal surface of through hole from the 3rd ILD layer 510 extends perpendicularly to the basal surface of metal valley, gold
Category groove extends to the top surface of the 3rd ILD layer 510.
As shown in cross-sectional view 2406, the 3rd metal material 2408 is formed in more than the 3rd opening 2404, to be formed
Second via layer V1 and the second metal line layer M2 of covering.Second metal line layer M2 includes the first transmission electrode 520a' and first
Receiving electrode 522a'.First transmission electrode 520a' is laterally separated by the 3rd ILD layer 510 and the first receiving electrode 522a'.
In some embodiments, the 3rd metal material 2408 (for example, copper) can by above-described depositing operation, follow-up shikishima plating process and
CMP is deposited.
Although Figure 24 is illustrated using dual-damascene technics formation the second via layer V1 and the second metal line layer M2, general technology
Person will be appreciated that in an alternative embodiment, and list mosaic technology formation the second via layer V1 and the second metal line layer M2 can be used.
In this little embodiment, the through hole that the chosen property etching of the first dielectric layer is subsequently filled with being formed.Then on the first dielectric layer
It is square into the second dielectric layer.The chosen property of second dielectric layer etches to form metal valley.
Figure 25 illustrates the cross-sectional view 2500 and cross-sectional view 2502 of the integrated chip corresponding to operation 2012~2018
Some embodiments.
As shown in cross-sectional view 2500, the 4th ILD layer 512 is formed in the top of the 3rd ILD layer 510.4th ILD layer 512
The 4th etchant 2502 (for example, CF4, CHF3, C4F8, HF etc.) is optionally exposed to, the 4th etchant 2502 is configured to
The 4th ILD layer 512 is etched to form dielectric medium waveguide openings 2504.Dielectric medium waveguide openings 2504 are included to be transmitted from covering first
Electrode 520a' first position extends laterally to the oblong openings of the first receiving electrode 522a' of the covering second place.
As shown in cross-sectional view 2506, dielectric material 2508 is formed in dielectric medium waveguide openings 2504.Dielectric material
The 2508 projecting ILD layers of the dielectric constant included (for example, ILD layer 510 and ILD layer 512).In certain embodiments, it can borrow
Dielectric material 2508 is formed to filling dielectric medium waveguide openings 2504 by gas phase deposition technology (for example, PVD, CVD, PE-CVD etc.)
Thickness.Cmp (CMP) technique can be used to remove excessive dielectric material from the top surface of the 4th ILD layer 512
2508。
As shown in cross-sectional view 2510, the 4th ILD layer 512 be optionally exposed to the 5th etchant 2512 (for example,
CF4, CHF3, C4F8, HF etc.), the 5th etchant 2512 is configured to the 4th ILD layer 512 of etching to form more than second through hole
2514.More than second through hole 2514 include be arranged on above lower metal layer substantially round via openings (that is, through hole
2514 is main above lower floor second metal layer M2, to provide between the through hole subsequently formed and lower floor second metal layer M2
Contact).More than second through hole 2514 and dielectric medium waveguide openings 2504 it is laterally separated (that is, with more than second through hole 2514
Dielectric medium waveguide openings 2504 are set in identical perpendicular layers).
As shown in cross-sectional view 2516, the 4th metal material 2518 is formed in more than second through hole 2514.At some
In embodiment, the 4th metal material 2518 (for example, copper) can be by above-described depositing operation, follow-up shikishima plating process and CMP
Process deposits.
Figure 26 illustrates some of the cross-sectional view 2600 for corresponding to the integrated chip for operating 2020 and cross-sectional view 2606
Embodiment.
As shown in cross-sectional view 2600, the 5th ILD layer 518 is formed in the top of the 4th ILD layer 512.5th ILD layer 518
The 6th etchant 2602 (for example, CF4, CHF3, C4F8, HF etc.) is optionally exposed to, the 6th etchant 2602 is configured to
The 5th ILD layer 518 is etched to form more than the 4th openings 2604 comprising the metal valley for extending through the 5th ILD layer 518.
As shown in cross-sectional view 2606, fifth metal material 2608 is formed in more than the 4th opening 2604.At some
In embodiment, fifth metal material 2608 (for example, copper) can be by above-described depositing operation, follow-up shikishima plating process and CMP
Process deposits.Fifth metal material 2608 forms the second transmission electrode 520b' and second in the 3rd metal line layer M3 and receives electricity
Pole 522b'.Second transmission electrode 520b' is laterally separated by the 5th ILD layer 518 and the second receiving electrode 522b'.
Figure 27 illustrates displaying with the whole of the multiple band transmission element and receiving element being coupled to through integrating dielectric medium waveguide
Some embodiments of the block diagram of box-like chip 2700.
Integrated chip 2700 includes multiple band transmission element 2702, and multiple band transmission element 2702 is adjusted with multiple phases
Dependent element 2704a~2704c.In certain embodiments, multiple phase modulation element 2704a~2704c are included to be arranged in and partly led
One or more semiconductor elements in structure base board 102.Multiple phase modulation element 2704a~2704c are configured to adjust data
Fade in different carrier signals (that is, clock signal), to produce the dielectric knot treated along the top of semiconductor substrate 102 is arranged in
Multiple modulated signals that dielectric medium waveguide 106 in structure 104 is transmitted.In certain embodiments, multiple phase modulation elements
2704a~2704c is configured to by orthogonal amplitude modulating and changing (QAM) mechanism respectively by data-modulated to carrier signal.
Multiple phase modulation element 2704a~2704c be configured to receive respectively data-signal Dx (for example, wherein x=1,
3) and clock signal CLKx (for example, wherein x=1,2 or 3) 2 or.There is provided to multiple phase modulation element 2704a~2704c
Clock signal CLKx (that is, carrier signal) it is different, it is different that this difference produces multiple phase modulation element 2704a~2704c
Multiple modulated signals in frequency range.For example, first phase varying element 2704a is configured to receive the first clock pulse
Signal CLK1 and produce first frequency in the range of the first modulated signal.Similarly, second phase varying element 2704b can be through
Configure to receive the second modulated signal in the range of the second clock signal CLK2 and generation second frequency, and third phase modulation
Element 2704c can be configured to receive the 3rd modulated signal in the 3rd frequency range of the 3rd clock signal CLK3 and generation.
Multiple phase modulation element 2704a~2704c, which are coupled to, includes the first of multiple transmission electrode 2706a~2706b
Coupling element 2706.In certain embodiments, multiple transmission electrode 2706a~2706b can be included along dielectric medium waveguide 106
A upper electrode and a lower electrode for opposite side arrangement.In other embodiments, multiple transmission electrode 2706a~
2706b can include the multiple upper electrodes and multiple lower electrodes arranged along the opposite side of dielectric medium waveguide 106.First coupling
Element 2706 forms the interface that multiple modulated signals are coupled in dielectric medium waveguide 106.For example, multiple modulated letters
Number the first coupling element 2706 is set to produce multiple electric fields respectively, this little electric field extends in dielectric medium waveguide 106 and will be many respectively
Individual modulated signal is coupled in dielectric medium waveguide 106.
The example of some embodiments of frequency spectrum 2800 in dielectric medium waveguide 106 is illustrated in Figure 28.In frequency spectrum 2800,
The first modulated signal of arrangement in first frequency scope 2802 (for example, centered on 72GHz), in second frequency scope 2804
The second modulated signal of arrangement in (for example, centered on 96GHz), and the 3rd frequency range 2806 (for example, using 120GHz as
Center) the 3rd modulated signal of interior arrangement.By the different modulated signals under transmission different frequency scope 2802~2806, it is situated between
Electric matter waveguide 106 can transmit the first modulated signal, the second modulated signal and the 3rd simultaneously through adjusting in dielectric medium waveguide 106
Varying signal.Using dielectric medium waveguide 106 allow each phase modulation element 2704a~2704c larger frequency range (for example,
Transmission signal in 16GHz), so that data transfer overall rate is higher.
Dielectric medium waveguide 106 is configured to the first modulated signal, the second modulated signal and the 3rd modulated signal
The second coupling element 2708 is sent to, the second coupling element 2708 includes multiple the connecing along the side arrangement of dielectric medium waveguide 106
Receive electrode 2708a~2708b.Second coupling element 2708 forms the boundary that multiple modulated signals are coupled from dielectric medium waveguide 106
Face.Multiple modulated signals, multi-band reception element are provided from the second coupling element 2708 to multi-band reception element 2710
2710 are configured to the multiple modulated signals of demodulation.
Multi-band reception element 2710 includes multiple restitution element 2712a~2712c.In certain embodiments, multiband
Receiving element 2710 can have the same number of restitution element 2712a~2712c with varying element 2704a~2704c.Citing
For, multi-band reception element 2710 can include the first restitution element 2712a, the second restitution element 2712b and the 3rd demodulation member
Part 2712c.First restitution element 2712a is configured to receive the first modulated signal and the first clock signal CLK1, and through matching somebody with somebody
Put to demodulate the first modulated signal to restore the first data-signal D1.Second restitution element 2712b is configured to reception second
Modulated signal and the second clock signal CLK2, and be configured to the second modulated signal of demodulation to restore the second data-signal
D2.3rd restitution element 2712c is configured to receive the 3rd modulated signal and the 3rd clock signal CLK3, and is configured to solution
The 3rd modulated signal is adjusted to restore the 3rd data-signal D3.In certain embodiments, multi-band reception element 2710 is configured
With by orthogonal amplitude modulating and changing (QAM) mechanism demodulating data.
Figure 29 is illustrated with the integrated of the multiple band transmission element and receiving element being coupled to through integrating dielectric medium waveguide
The top view of some embodiments of chip 2900.
Integrated chip 2900, which is included, is configured to the multiple phases for producing multiple modulated signal Smod1~Smod3 tune
Dependent element 2704a~2704c.Multiple phase modulation element 2704a~2704c are by including one or more metal interconnecting layer (examples
Such as, conductive contact 2904, metal interconnecting wires 2906, metal throuth hole 2908 etc.) independent conductive path be respectively coupled to multiple biographies
A transmission electrode in transmission pole 2902a~2902c (in the first coupling element 2902).By multiple phase modulation elements
Each single transmission electrode being connected in multiple transmission electrode 2902a~2902c in 2704a~2704c reduces many
Interfere between frequency band between individual different frequency frequency band.For example, electrically decoupling multiple transmission electrode 2902a~2902c can be by
Interference, which reduces, between frequency band is more than 10dB.
Multiple transmission electrode 2902a~2902c be included in the top of dielectric medium waveguide 310 arrangement and with it is laterally separated each other
The conducting element (for example, metal interconnecting wires) of (for example, by dielectric material).Multiple transmission electrode 2902a~2902c are configured
To produce single electric field in the dielectric medium waveguide 310, this little individually electric field be based respectively on multiple modulated signal Smod1~
Smod3.Single electric field depending on the clock signal CLK1 provided to multiple phase modulation element 2704a~2704c~
Multiple modulated signal Smod1~Smod3 are coupled in dielectric medium waveguide 310 under CLK3 multiple different frequency bands.At some
In embodiment, dielectric medium waveguide 310 has the tapered distal end that width is continuously reduced from the first width to the second narrower width.One
In a little embodiments, multiple transmission electrode 2902a~2902c cross over tapered distal end.
Multiple receiving electrode 2910a~2910c (in the second coupling element 2910) are configured to connect from dielectric medium waveguide 310
Receive multiple modulated signal Smod1~Smod3.Multiple receiving electrode 2910a~2910c are included in the top of dielectric medium waveguide 310
Arrangement and with the conducting element (for example, metal interconnecting wires) of laterally separated (for example, by dielectric material) each other.It is multiple to receive electricity
Pole 2910a~2910c is by the independent conductive path for including one or more metal interconnecting layers (for example, metal wire, metal throuth hole etc.)
Footpath be respectively coupled to be configured to multiple phase demodulating element 2712a for demodulating multiple modulated signal Smod1~Smod3~
A phase demodulating element in 2712c.
Figure 30 A~Figure 30 B illustrate (orthogonal to shake with the multiband QAM through integrating dielectric medium waveguide is operationally coupled to
Width modulation) interface integrated chip 3000 some embodiments.
Figure 30 A, which illustrate to have, is operationally coupled to the multiband QAM (orthogonal amplitude modulating and changing) through integrating dielectric medium waveguide
The block diagram of the integrated chip 3000 of transfer element and receiving element.
Multiband QAM transmitter elements 3002, which are included, to be configured to produce by the modulated of the transmission of dielectric medium waveguide 106
Multiple QAM varying elements 3004a~3004c of signal.In certain embodiments, multiple QAM varying elements 3004a~3004c
It can respectively include and be configured to receive the one or more of data D1~D12 (for example, 2 bit digital signals) from Baseband processor 3006
Individual numerical digit analogy converter (digital-to-analog converters；DACs)3008.DAC3008 is produced to liter from data
Same phase (I) and quadrature phase (Q) equivalent fundamental frequency signal that frequency conversion mixer 3010 is provided.In certain embodiments, Ke Yigao
Data rate (for example, 8GB/ seconds) to DAC 3008 provide data so that in dielectric medium waveguide 106 data transfer entirety
Speed is higher (for example, 96GB/ seconds).
Multiple QAM varying elements 3004a~3004c also can respectively be included and are configured to produce high-frequency (for example, 90GHz)
Under oscillator output signal SOx (for example, sine wave) local oscillator 3012.Multiple QAM varying elements 3004a~
Local oscillator 3012 in 3004c is configured to produce oscillator output signal SO1~SO3 with different frequency.Xiang Zheng
Frequency divider 3014 is handed over to provide oscillator output signal SO1~SO3, quadrature divider 3014, which is configured to divide by division factor, shakes
Device output signal SO1~SO3 frequency is swung, 90 ° are offset to produce local oscillator signals.Carried to up-conversion frequency mixer 3010
For local oscillator signals, up-conversion frequency mixer 3010 by the equivalent fundamental frequency signal modulations of I and Q to local oscillator signals,
The frequency of the equivalent fundamental frequency signals of up-conversion I and Q whereby.
The output of up-conversion frequency mixer 3010 is combined to form multiple modulated input signals by adder 3016.One
In a little embodiments, the phase of the expression data mode of multiple modulated signals respectively shown in the stellar map 3038 with Figure 30 B
(Θ) and value (r).For example, the first modulated input signal can have corresponding to the first data mode first phase and
Amplitude is combined, and the second modulated input signal can have corresponding to second phase and amplitude combination of the second data mode etc..
In some embodiments, multiple QAM varying elements 3004a~3004c are configured to produce difference modulating signal SINx+And SINx-(its
Middle x=1,2,3), SINx+With SINx-Between there are 180 ° of differences.
In certain embodiments, the forward direction that can be received in multiple modulated signals by the first coupling element 2706 one or more
Amplifier element provides multiple modulated signals.Due to losing as frequency increases, therefore amplification member can be operated by control unit 3020
Part is multiple modulated produced by indivedual QAM varying elements in the multiple QAM varying elements 3004a~3004c of adjustment to apply
The different gains of the amplitude of signal, to compensate the pass loss of different frequency bands.For example, the modulated signal in lowest band
It can amplify by the gain smaller than modulated signal in high frequency band.In certain embodiments, amplifier element can be included
It is arranged in the amplifier 3018 in the downstream of up-conversion frequency mixer 3010.In other embodiment (not illustrating), amplifier element can
Include the amplifier element for the upstream for being arranged in up-conversion frequency mixer 3010.
The second coupling element 2708 for being coupled to multiband QAM receiving elements 3022 is configured to from dielectric medium waveguide 106
Receive multiple modulated signals.Multiband QAM receiving elements 3022 include multiple QAM restitution elements 3024a~3024c.It is multiple
QAM restitution elements 3024a~3024c includes down conversion mixers 3028 respectively, and down conversion mixers 3028 are configured to
Based on the local oscillator signals SO1 produced by local oscillator 3032a~3032c and quadrature divider 3034~SO3 demodulation
A modulated signal in the multiple modulated signals received from separator 3026.ADC (analog-to-
digital converter；ADC) 3030 it is configured to the output of down conversion mixers 3028 being converted into digital signal
The digital signal that processor 3036 is provided.In certain embodiments, filter element (for example, bandpass filter) (not illustrating) can
Positioned at the downstream of down conversion mixers 3028.Filter element is configured to being in for removal received signal and corresponds to demodulation
Component outside the frequency band of the clock signal of element.
Figure 31 is illustrated with multiband QAM (orthogonal amplitude modulating and changing) biographies being operationally coupled to through integrating dielectric medium waveguide
Some embodiments of three-dimensional (3D) view of the block diagram of the integrated chip 3100 of defeated element and receiving element.
Integrated chip 3100 includes multiple band transmission element 3102, and multiple band transmission element 3102 is adjusted with the first QAM
Dependent element 3104a, the 2nd QAM varying elements 3104b and the 3rd QAM varying elements 3104c.First QAM varying elements 3104a is passed through
Configure to produce the first difference modulation input signal SIN1+And SIN1-.2nd QAM varying elements 3104b is configured to generation second
Difference modulation input signal SIN2+And SIN2-.3rd QAM varying elements 3104c is configured to produce the 3rd difference modulation input letter
Number SIN3+And SIN3-。
Multiple band transmission element 3102 is coupled to multiple top transmission electrodes by more than first differential drive circuit 3110
3106a~3106e (be arranged in dielectric medium waveguide 106 top) and it is coupled to multiple lower transfer electrode 3108a~3108e (cloth
Put below dielectric medium waveguide 106).More than first differential drive circuit 3110 is configured to drive multiple top transmission electrodes
A bottom in a top transmission electrode and multiple lower transfer electrode 3108a~3108e in 3106a~3106e is passed
Transmission pole.For example, more than first differential drive circuit 3110 can include the first transistor and second transistor element respectively,
The first transistor, which has, is coupled to the first difference modulation input signal (for example, SIN2+) first grid and be coupled to multiple tops
First drain electrode of a top transmission electrode in transmission electrode 3106a~3106e, second transistor element, which has, is coupled to the
Two difference modulation input signals are (for example, SIN2-) second grid and be coupled in multiple lower transfer electrode 3108a~3108e
A lower transfer electrode second drain electrode.In certain embodiments, multiple top transmission electrode 3106a~3106e and that
This electrical isolation, and multiple lower transfer electrode 3108a~3108e are with being electrically isolated from one another.
Multiple top transmission electrode 3106a~3106e include first group of biography for being coupled to the first QAM varying elements 3104a
Transmission pole 3108c, second group of transmission electrode 3108b and 3108d for being coupled to the 2nd QAM varying elements 3104b, and it is coupled to
Three QAM varying elements 3104c the 3rd group of transmission electrode 3108a and 3108e.In certain embodiments, first group of transmission electrode,
One of second group of transmission electrode or the 3rd group of transmission electrode multiple include multiple transmission electrodes.In certain embodiments,
First group of transmission electrode, second group of transmission electrode and the 3rd group of transmission electrode are arranged with balanced configuration.For example, first group
Transmission electrode can include central electrode, and second group of transmission electrode can include the electrode around central electrode, and the 3rd group of transmission electricity
Pole can include most external electrode.In certain embodiments, first group of transmission electrode, second group of transmission electrode and the 3rd group of transmission electricity
Pole is arranged with the configuration depending on the carrier frequency of associated QAM varying elements.For example, the first QAM varying elements
3104a can produce the modulated signal in lowest band, the 2nd QAM varying elements 3104b can produce in intermediate frequency band through adjusting
Varying signal, and the 3rd QAM varying elements 3104c can produce the modulated signal in highest frequency band.In certain embodiments, through with
Put with produce the QAM varying elements of the modulated signal in lowest band may be coupled to one group of ratio be configured to produce high frequency band
In modulated signal the less electrode of QAM varying elements.
Integrated chip 3100 also includes multi-band reception element 3118, and multi-band reception element 3118 has the first QAM
Restitution element 3120a, the 2nd QAM restitution elements 3120b and the 3rd QAM restitution elements 3120c.In certain embodiments, multifrequency
Band receiving element 3118 is coupled to multiple top receiving electrode 3112a~3112e by more than second differential drive circuit 3116
(be arranged in dielectric medium waveguide 106 top) and it is coupled to multiple bottom receiving electrode 3114a~3114e and (is arranged in dielectric medium ripple
Lead 106 lower sections).More than second differential drive circuit 3116 includes the first transistor and second transistor element respectively, and first is brilliant
Body pipe has the first grid and coupling for a top receiving electrode being coupled in multiple top receiving electrode 3112a~3112e
The first drain electrode of multi-band reception element 3118 is connected to, second transistor element, which has, is coupled to multiple bottom receiving electrodes
The second grid of a bottom receiving electrode in 3114a~3114e and the second leakage for being coupled to multi-band reception element 3118
Pole.
Multiple top receiving electrode 3112a~3112e connect comprising be coupled to the first QAM restitution elements 3120a first group
Receive electrode 3112c, be coupled to the 2nd QAM restitution elements 3120b second group of transmission electrode 3112b and 3112d, and be coupled to the
Three QAM restitution elements 3120c the 3rd group of transmission electrode 3112a and 3112e.In certain embodiments, first group of transmission electrode,
Second group of transmission electrode and the 3rd group of transmission electrode are along dielectric medium waveguide 106 with first group of receiving electrode, second group of reception electricity
Pole and the mirror-image arrangement of the 3rd group of receiving electrode.In certain embodiments, multiple top receiving electrode 3112a~3112e and that
This electrical isolation, and multiple bottom receiving electrode 3114a~3114e are with being electrically isolated from one another.
More than second differential drive circuit 3116, which is configured to produce, corresponds to difference modulation input signal SINX+And SINX-
Multiple difference modulation output signal S of (wherein x=1,2,3)OUTX+And SOUTX-(wherein x=1,2,3).For example, difference is driven
Dynamic circuit 3116, which is configured to produce, corresponds to modulated input signal SIN1+And SIN1-Difference modulation output signal SOUT1+And
SOUT1-.Self difference drive circuit 3116 provides difference modulation output signal S to the first QAM restitution elements 3120aOUT1+And SOUT1-,
Self difference drive circuit 3116 provides difference modulation output signal S to the 2nd QAM restitution elements 3120bOUT2+And SOUT2-, and from
Differential drive circuit 3116 provides difference modulation output signal S to the 3rd QAM restitution elements 3120cOUT3+And SOUT3-。
Figure 32 illustrates to be formed comprising the whole of the multiple band transmission element and receiving element being coupled to through integrating dielectric medium waveguide
The flow chart of some embodiments of the method 3200 of box-like chip.
At 3202, the multiple band transmission element for including multiple phase modulation elements is formed in substrate.Multiple phases are adjusted
Dependent element is configured to produce multiple modulated signals under different frequency scope.
At 3204, the multi-band reception element for including multiple phase demodulating elements is formed in substrate.Multiple phase solutions
Element is adjusted to be configured to the multiple modulated signals of demodulation.
At 3206, the first metal material is formed in more than first openings in the first ILD layer, to form first through hole
Layer.First through hole layer includes the multiple through holes for contacting multiple phase modulation elements and multiple phase demodulating elements.
At 3208, more than the second shielding element opening and first formed in the second ILD layer for covering the first ILD layer
The second metal material is formed in multiple metal wire trenchs.The formation of the second metal material is formed in multiple shielding element openings to include
The shielding element of multiple grounded metal lines of parallel arrangement in second ILD layer.
At 3210, the 3rd metal material is formed in the lower electrode opening in the 3rd ILD layer, to form one or more
Lower transfer electrode and one or more bottom receiving electrodes.Multiple phase modulation elements are coupled to one or more lower transfer electrodes
In at least one lower transfer electrode.Multiple phase demodulating elements are coupled at least one in one or more bottom receiving electrodes
Individual bottom receiving electrode.
At 3212, the 4th ILD layer of the 3rd ILD layer of covering is patterned to dielectric medium waveguide openings.Dielectric medium
Waveguide openings have the second end of the first end for covering multiple lower transfer electrodes and the multiple bottom receiving electrodes of covering.
At 3214, dielectric material is formed in dielectric medium waveguide openings, to form dielectric medium ripple in the 4th ILD layer
Lead.The dielectric constant of dielectric material is bigger than the dielectric constant of ILD layer around.
At 3216, the 4th ILD layer is patterned with more than second through hole of formation in the 4th ILD layer.
At 3218, the 4th metal material is formed in more than second through hole.
At 3220, fifth metal material is formed in the upper electrode opening in the 5th ILD layer for covering the 4th ILD layer
Material, to form one or more top transmission electrodes and one or more top receiving electrodes.Multiple phase modulation elements are coupled to one
Or at least one top transmission electrode in multiple top transmission electrodes.Multiple phase demodulating elements are coupled to one or more tops
At least one top receiving electrode in receiving electrode.
Therefore, this disclosure system is on including the multiple band transmission element and reception being coupled to through integrating dielectric medium waveguide
The integrated chip of element.
In certain embodiments, this disclosure system is on an integrated chip.Integrated chip includes and is arranged on a base
The dielectric medium waveguide in an interlayer dielectric structure above plate.A multiple band transmission element with multiple phase modulation elements
It is configured to produce multiple modulated signals in different frequency bands.Multiple transmission electrodes are located at along the first side of dielectric medium waveguide
And be configured to a modulated signal in multiple modulated signals being coupled in dielectric medium waveguide respectively.
In certain embodiments, integrated chip further includes multiple local oscillators.The plurality of local oscillator warp
Configure to produce multiple oscillator signals with different frequency and be configured into the plurality of phase modulation element
Out of phase varying element provides the different oscillator signals in the plurality of oscillator signal.
In certain embodiments, integrated chip further includes multiple amplifier elements and a control unit.Control is single
Member is configured to operate the plurality of amplifier element to adjust one of a modulated signal in the plurality of modulated signal respectively
Amplitude amount.The amount depends on a frequency band of the modulated signal.
In certain embodiments, the plurality of transmission electrode is electrically isolated from one another.
In certain embodiments, dielectric medium waveguide has a tapered distal end.One width of tapered distal end is from one first width
It is continuously reduced to one second narrower width.Multiple transmission electrodes cross over tapered distal end.
In certain embodiments, integrated chip further includes multiple receiving electrodes and a multi-band reception element.
Multiple receiving electrode positioning are along the first side of dielectric medium waveguide and are configured to one in the plurality of modulated signal respectively
Individual modulated signal is coupled out dielectric medium waveguide.Multi-band reception element has multiple phase demodulating elements.The plurality of phase solution
Element is adjusted to be configured to receive the modulated signal such as this from the plurality of receiving electrode.
In certain embodiments, multiple band transmission element includes the first phase tune for being coupled to one first group of transmission electrode
Dependent element, the second phase varying element for being coupled to one second group of transmission electrode and it is coupled to the one of one the 3rd group of transmission electrode
Third phase varying element.The multi-band reception element includes the first phase demodulation member for being coupled to one first group of receiving electrode
Part, the second phase restitution element for being coupled to one second group of receiving electrode and it is coupled to the one the 3rd of one the 3rd group of receiving electrode
Phase demodulating element.
In certain embodiments, first group of transmission electrode, second group of transmission electrode and the 3rd group of transmission electrode are along dielectric
Matter waveguide is in a mirror-image arrangement with first group of receiving electrode, second group of receiving electrode and the 3rd group of receiving electrode.
In certain embodiments, in first group of transmission electrode, second group of transmission electrode or the 3rd group of transmission electrode one or
Multiple multiple transmission electrodes including being located at along one first side of dielectric medium waveguide.
In certain embodiments, the plurality of phase modulation element is configured to produce one first modulated signal and one second
Modulated signal.First modulated signal is by dielectric medium waveguide transmission under a first frequency scope.Second modulated signal by
The dielectric medium waveguide transmission is under the second frequency scope separated with first frequency scope.
In certain embodiments, integrated chip further includes multiple differential drive circuits.The plurality of differential driving electricity
Road is configured to receive the first input signal and second from a phase modulation element in the plurality of phase modulation element respectively
Input signal and to produce multiple differential signals.The plurality of differential drive circuit is each configured into the plurality of transmission electrode
A transmission electrode and along the dielectric medium waveguide one second side arrange one second many transmission electrodes in one biography
Transmission pole provides a differential signal in the plurality of differential signal.
In other embodiments, this disclosure system is on an integrated chip.Integrated chip includes and is arranged on a base
The dielectric medium waveguide in an interlayer dielectric structure above plate.One first phase varying element, which is coupled to, to be located at along dielectric medium
One first transmission electrode of one first side of waveguide.First phase varying element is configured to produce in a first frequency scope
One first modulated signal.First transmission electrode is configured to the first modulated signal being coupled in dielectric medium waveguide.One
Two phase varying element is coupled to positioned at one second transmission electrode along the first side of dielectric medium waveguide.Second phase modulation member
Part is configured to produce one second modulated signal in a second frequency scope.Second transmission electrode is configured to the second warp
Modulating signal is coupled in dielectric medium waveguide.
In certain embodiments, the first transmission electrode and the second transmission electrode electrical isolation.
In certain embodiments, dielectric medium waveguide has a tapered distal end.One width of tapered distal end is from one first width
It is continuously reduced to one second narrower width.First transmission electrode and the second transmission electrode cross over tapered distal end.
In certain embodiments, integrated chip further includes a first phase restitution element and a second phase solution
Adjust element.First phase restitution element is coupled to positioned at one first receiving electrode along the first side of dielectric medium waveguide and through matching somebody with somebody
Put to receive the first modulated signal.Second phase restitution element is coupled to positioned at along the one the of the first side of dielectric medium waveguide
Two receiving electrodes and be configured to receive the second modulated signal.
In certain embodiments, first phase varying element includes one first local oscillator.First local oscillator is passed through
Configure to produce one first oscillator signal under a first frequency.Second phase varying element includes one second local oscillations
Device.Second local oscillator is configured to produce one second oscillator signal under the second frequency different from first frequency.
In certain embodiments, integrated chip further includes multiple amplifier elements and a control unit.Control is single
Member is configured to according to operating the plurality of amplifier element to adjust the first modulated signal respectively and the one of the second modulated signal shake
Width amount.The amount depends on the frequency band of the first modulated signal and the second modulated signal.
In other embodiments, this disclosure system is on forming the method through integrating dielectric medium waveguide.Method is included：
The multiple band transmission element for including multiple phase modulation elements is formed in substrate, plurality of phase modulation element is configured to production
Multiple modulated signals in raw different frequency bands.Method is further included：Formed in substrate and include multiple phase demodulating elements
Multi-band reception element, plurality of phase demodulating element is configured to the multiple modulated signals of demodulation.Method is further wrapped
Contain：Dielectric medium waveguide is formed in interlayer dielectric (ILD) structure of covering substrate.Method is further included：Along dielectric medium ripple
The side led forms one or more transmission electrodes, and wherein one or more transmission electrodes are configured to multiple modulated signals being coupled to
In dielectric medium waveguide.Method is further included：One or more receiving electrodes are formed along the side of dielectric medium waveguide, wherein one or more
Individual receiving electrode is configured to decouple multiple modulated signals from dielectric medium waveguide.
In certain embodiments, method is further included：Adjust a modulated signal in the plurality of modulated signal
An amplitude amount, the amount depend on the modulated signal a frequency band.
In certain embodiments, the plurality of phase modulation element is configured to produce one first modulated signal and one second
Modulated signal.First modulated signal is under a first frequency scope by dielectric medium waveguide transmission.Second modulated signal exists
By dielectric medium waveguide transmission under the second frequency scope separated with first frequency scope.
The feature of some embodiments is outlined above, so that those who familiarize themselves with the technology is better understood the state of this disclosure
Sample.Skilled artisan will understand that, this disclosure easily can be used as design or changed for performing with introducing herein
Embodiment identical purpose and/or reach other techniques and the basis of structure of identical advantage.Those who familiarize themselves with the technology is also
It will be appreciated that spirit and scope of this little equivalent structure without departing from this disclosure, and those who familiarize themselves with the technology can not take off
From this disclosure spirit and scope in the case of to carry out herein various changes, substitute and change.
Claims (1)
1. a kind of integrated chip, it is characterised in that the integrated chip is included：
One dielectric medium waveguide, is arranged in an interlayer dielectric structure of a surface；
One multiple band transmission element, with the multiple phase modulations for being configured to produce multiple modulated signals in different frequency bands
Element；And
Multiple transmission electrodes, position and are configured to the plurality of modulated letter respectively along one first side of the dielectric medium waveguide
Number one of them modulated signal be coupled to the dielectric medium waveguide in.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/010,816 | 2016-01-29 | ||
| US15/010,816 US9715131B2 (en) | 2014-09-11 | 2016-01-29 | Integrated fan-out package including dielectric waveguide |
| US15/258,348 US10162198B2 (en) | 2014-09-11 | 2016-09-07 | Multiband QAM interface for slab waveguide |
| US15/258,348 | 2016-09-07 |
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| CN107026160A true CN107026160A (en) | 2017-08-08 |
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| TWI768794B (en) * | 2020-03-31 | 2022-06-21 | 台灣積體電路製造股份有限公司 | Optical device and method for fabricating the same |
| US11525957B2 (en) | 2020-03-31 | 2022-12-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fabrication process control in optical devices |
| US12066671B2 (en) | 2022-01-12 | 2024-08-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices with vertically stacked and laterally offset intermediate waveguides |
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| TW201740148A (en) | 2017-11-16 |
| CN107026160B (en) | 2022-03-15 |
| TWI707168B (en) | 2020-10-11 |
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