CN107026153B - Packaging part - Google Patents

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Publication number
CN107026153B
CN107026153B CN201611046177.0A CN201611046177A CN107026153B CN 107026153 B CN107026153 B CN 107026153B CN 201611046177 A CN201611046177 A CN 201611046177A CN 107026153 B CN107026153 B CN 107026153B
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China
Prior art keywords
tube core
voltage regulator
core
integrated voltage
encapsulating material
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CN201611046177.0A
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Chinese (zh)
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CN107026153A (en
Inventor
余振华
侯上勇
李云汉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN107026153A publication Critical patent/CN107026153A/en
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    • H—ELECTRICITY
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

The embodiment provides a kind of packaging parts, including integrated voltage regulator (IVR) tube core, wherein IVR tube core includes the metal column at the top surface of the first IVR tube core.Packaging part further includes the first encapsulating material for wherein encapsulating the first IVR tube core, wherein the first encapsulating material has the top surface coplanar with the top surface of metal column.A plurality of redistribution lines are located above the first encapsulating material and IVR tube core.A plurality of redistribution lines are electrically coupled to metal column.Core chips is Chong Die with a plurality of redistribution lines and is bonded to a plurality of redistribution lines.Core chips is encapsulated in second encapsulating material, wherein the corresponding edge of the edge of the first encapsulating material and the second encapsulating material is vertically aligned with one another.Insertion piece or package substrate are located at below IVR tube core and are bonded to IVR tube core.

Description

Packaging part
Technical field
The embodiment of the present invention is related to semiconductor field, relates more specifically to a kind of packaging part.
Background technique
The power requirement with higher that central processing unit (CPU) consumes input/output (IO) and CPU.For example, CPU may include multiple cores and need to consume sizable power.On the other hand, the requirement to the power of offer is also very It is high.For example, supply voltage needs are highly stable.Therefore, multiple pressure regulators can connect to same cpu chip to provide power supply.
Summary of the invention
The embodiment provides a kind of packaging parts, comprising: the first integrated voltage regulator (IVR) tube core, wherein described First integrated voltage regulator tube core includes: metal column, at the top surface of the first integrated voltage regulator tube core；First encapsulating material Material, by the first integrated voltage regulator die encapsulation in first encapsulating material, wherein first encapsulating material has The top surface coplanar with the top surface of the metal column；A plurality of redistribution lines are located at first encapsulating material and described first and integrate Above pressure regulator tube core, wherein a plurality of redistribution lines are electrically coupled to the metal column；First core chips is and described more Redistribution lines are overlapped and are bonded to a plurality of redistribution lines；Second encapsulating material encapsulates first core chips In second encapsulating material, wherein the corresponding side at the edge of first encapsulating material and second encapsulating material Edge is vertically aligned with one another；And insertion piece or package substrate, below the first integrated voltage regulator tube core and engage To the first integrated voltage regulator tube core.
The embodiments of the present invention also provide a kind of packaging parts, comprising: the first integrated voltage regulator (IVR) tube core and the second collection It at pressure regulator tube core, each includes: metal column；Regulator circuit is electrically coupled to the metal column；And inductor, it is electrically coupled To the regulator circuit；First encapsulating material, by the first integrated voltage regulator tube core and the second integrated voltage regulator pipe Core is encapsulated in first encapsulating material, wherein first encapsulating material has and the first integrated voltage regulator tube core The top surface coplanar with the top surface of the metal column in the second integrated voltage regulator tube core；Dielectric layer, it is integrated with described first Pressure regulator tube core, the second integrated voltage regulator tube core and first encapsulating material overlapping；A plurality of redistribution lines have position Part in the dielectric layer, wherein a plurality of redistribution lines are electrically coupled to the first integrated voltage regulator tube core and institute State the second integrated voltage regulator tube core；First central processing unit (CPU) chip and the second central processing unit chip, respectively with institute It states the first integrated voltage regulator tube core and the second integrated voltage regulator tube core is overlapped and is electrically coupled to described first and integrates Pressure regulator tube core and the second integrated voltage regulator tube core；And second encapsulating material, by the first central processing unit core Piece and second central processing unit chip are encapsulated in second encapsulating material.
The embodiments of the present invention also provide a kind of packaging parts, comprising: the first component pipe core, comprising: semiconductor substrate；The One through hole and the second through hole run through the semiconductor substrate；Active circuit, at the surface of the semiconductor substrate； First metal column, at the top surface of first component pipe core, wherein first metal column is electrically coupled to the active electricity Road and first through hole；And second metal column, at the top surface of first component pipe core, wherein described second Metal column is electrically coupled to second through hole, and second metal column with it is all active in first component pipe core Circuit is electrically disconnected；First component pipe core is encapsulated in first encapsulating material by the first encapsulating material；Second device pipe Core, it is Chong Die with first component pipe core and be electrically coupled to first component pipe core；And packaging part component, it is located at described Below first component pipe core and it is bonded to first component pipe core, wherein second through hole and second metal The packaging part component is electrically coupled to second component pipe core by column.
Detailed description of the invention
When reading in conjunction with the accompanying drawings, the embodiment that the present invention may be better understood according to the following detailed description. It is emphasized that according to the standard practices in industry, being not necessarily to scale to various parts.In fact, in order to clear It discusses, the size of various parts can be arbitrarily increased or reduced.
Fig. 1 to Fig. 9 shows the centre in accordance with some embodiments in the formation of packaging part for including integrated voltage regulator The sectional view in stage.
Figure 10 shows the sectional view of the packaging part in accordance with some embodiments including integrated voltage regulator.
Figure 11 shows the process flow in accordance with some embodiments for being used to form packaging part.
Specific embodiment
Following disclosure provides many different embodiments or example for realizing different characteristic of the invention.Below The specific example of component and arrangement is described to simplify the present invention.Certainly, these are only example, are not intended to limit this hair It is bright.For example, in the following description, above second component or the upper formation first component may include the first component and second Part is formed as the embodiment directly contacted, and also may include can be formed between the first component and second component it is additional Component, so that the embodiment that the first component and second component can be not directly contacted with.In addition, the present invention can be in each example Middle repeat reference numerals and/or letter.The repetition is for purposes of simplicity and clarity, and itself not indicate to be discussed Relationship between each embodiment and/or configuration.
Moreover, for ease of description, can be used herein such as " ... below ", " in ... lower section ", " lower part ", " ... on The spatially relative term in face ", " top " etc., in order to describe an element or component and another element or component as shown in the figure Relationship.Other than orientation shown in figure, spatially relative term is intended to include the different direction of device in use or operation. Device can otherwise orient (be rotated by 90 ° or in other directions), and spatial relative descriptor as used herein can be with Similarly make corresponding explain.
A kind of multi-layer packaging part and forming method thereof is provided according to each exemplary embodiment.It can be used on substrate Chip (Chip-on-Wafer-on-Substrate, CoWoS) technique forms multi-layer packaging part on wafer.It shows to form this The intermediate stage of packaging part.Discuss some modifications of some embodiments.It is identical through each view and illustrative embodiments Reference label is for indicating identical element.
Fig. 1 to Fig. 9 shows the section in the intermediate stage in accordance with some embodiments in the formation of multi-layer packaging part Figure.It is schematically shown in the process flow 200 that step shown in Fig. 1 to Fig. 9 is also shown in FIG. 11.
Referring to Fig.1, carrier 20 is provided, and adhesive layer 22 is set above carrier 20.Carrier 20 can be blank glass Glass carrier, blank ceramic monolith, organic carrier etc., and can have the shape of the semiconductor crystal wafer of circular top view shape. Sometimes, carrier 20 is referred to as carrier wafer.For example, adhesive layer 22 can be formed by photothermal conversion (LTHC) material, and can also To use other kinds of adhesive.According to some embodiments of the present invention, adhesive layer 22 can decompose under the heat of light, and And it therefore can be from the structure release carrier 20 being formed thereon.
Referring to Fig. 2, mask placement device tube core 24 (including 24A, 24B, 24C, 24D and 24E) above adhesive layer 22.Accordingly Step is shown as the step 202 in process flow shown in Figure 11.Through specification, component pipe core 24 is also known as level 1 Tube core.It should be understood that implementing the processing step then discussed under wafer scale.Therefore, have with include component pipe core 24A, The identical multiple tube core groups of the tube core group of 24B, 24C, 24D and 24E.Multiple tube core groups may be arranged to include rows and columns Array.Component pipe core 24 can be the same or different from each other.For example, component pipe core 24A, 24B, 24C and 24D can be with those This is identical, and is different from component pipe core 24E.
According to some embodiments of the present invention, component pipe core 24 is to include for supplying for tube core adjusting voltage above Integrated voltage regulator (IVR) tube core of pressure regulator.Circuit schematic in IVR is shown as formed in semiconductor substrate 28 26. According to an alternative embodiment of the invention, component pipe core 24 includes logic dice or such as static random access memory (SRAM) is managed The memory dice of core, dynamic random access memory (DRAM) tube core etc..
IVR circuit 26 may include simulation pump circuit (pump circuit), digital control piece and for adjusting voltage Other circuits.For example, simulation pump circuit is used to electric current being pumped into logic dice above.Digital control piece has determining simulation When circuit needs to pump the function of electric current (pump current).When being used for advanced IVR, digital control piece can be determined Need to open how much phases of simulation pump, to be optimized to the electric current output of component pipe core above.In addition, component pipe core 24 may be used also To include the inductor 30 for being electrically coupled to simulation pump circuit sum number word control block.IVR circuit can also include being located at component pipe core Down detection circuit under voltage in 52 (including 52A, 52B and 52C, Fig. 9).Down detection circuit is by device pipe above under voltage Core 52 (Fig. 8) is used detecting voltage decline, digitizing and feeding back to the simulation pump circuit in component pipe core 24.
According to some embodiments of the present invention, component pipe core 24 is independent IVR tube core, wherein in addition to by regulator circuit Those of use, it is arranged in component pipe core 24 without other logic circuits.According to alternative embodiment, some logic circuits or deposit Memory circuit is arranged in inside component pipe core 24 together with regulator circuit.
Component pipe core 24 includes semiconductor substrate 28, can be silicon substrate, silicon-carbon substrate, III-V compound and partly leads Body substrate etc..Component pipe core 24 further includes interconnection structure 32.According to some embodiments of the present invention, interconnection structure 32 includes multiple Dielectric layer 34 and metal wire and through-hole (not shown) in dielectric layer 34.Dielectric layer 34 may include can be by low k dielectric Inter-metal dielectric (IMD) layer that material is formed, for example, the dielectric constant (k value) of low k dielectric lower than 3.5, below about 3.0, Or it is below about 2.5.In addition, close to the top surface of component pipe core 24, such as silicon nitride layer, silicon oxide layer, undoped can have The non-low k passivation layer of silicate glass (USG) layer, and/or polymeric layer.In addition, the metal column 40 in surface dielectric layer 34 (including 40A and 40B) is located at the surface of interconnection structure 32.Metal column 40 can be containing copper pad, containing aluminum pad etc..According to one One top surface of a little embodiments, the top of dielectric layer 34 is coplanar with the top surface of metal column 40.According to some embodiments, surface is situated between A part covering metal column 40 of electric layer 34.Surface dielectric layer 34 can be polymeric layer, for example, it can be by polybenzoxazoles (PBO) it is formed.
Inductor 30 is embedded in interconnection structure 32, and the still part of regulator circuit.30 company of can be used of inductor The metal wire and through-hole connect is formed with the shape with coil.Therefore, according to some embodiments of the present invention, inductor 30 is collection On-chip inductors in the identical chip of Cheng Yu IVR circuit.According to an alternative embodiment of the invention, inductor 30 is formed in The outside of IVR tube core 24 is as separate inductor.
Component pipe core 24 further include through hole (being alternatively referred to as silicon through hole or substrate through hole) 36 (including 36A and 36B).It should be understood that although through hole 36 is shown as the semiconductor substrate in Fig. 2, the placer above carrier 20 When part tube core 24, through hole 36 can be not extend at the bottom surface of semiconductor substrate 28.In addition, through hole 36 is extended between half Mid-plane between the top and bottom of conductor substrate 28, and as shown in fig. 7, the bottom end of through hole 36 will be in subsequent back It is exposed in the grinding steps of face.Each through hole 36 is by the dielectric layer (not shown) around corresponding through hole 36 and accordingly Semiconductor substrate 28 be electrically insulated.
Through hole 36A and 36B are used to the conductive component of 28 top of semiconductor substrate being connected to corresponding semiconductor substrate Conductive component below 28.Through hole 36B be electrically coupled to inside corresponding component pipe core 24 device (such as IVR circuit is led Line, inductor 30 etc.).Through hole 36B can also be electrically coupled to metal column 40B.On the other hand, the through hole in component pipe core 24 36A is used separately for the conductive component (component pipe core 52 in such as Fig. 8) of corresponding 24 top of component pipe core being connected to device Conductive component (metal pad in insertion piece 70 in such as Fig. 8) below part tube core 24.Through hole 36A is not attached to device Inside tube core 24 any other circuit (active device including such as transistor and diode and such as capacitor, inductor, The passive device of resistor etc.).Therefore, through hole 36A is for the component outside interconnection devices tube core 24, and is not used in device The interior connection of circuit inside tube core 24.In other words, through hole 36A has function identical with molding through hole (not shown), And it moulds through hole and the outside in component pipe core 24 can be set and run through encapsulating material 44 (Fig. 8).However, in component pipe core 24 Inside forms the not additional manufacturing cost of through hole 36A, this is because, through hole 36A and perforation different from molding through hole Hole 36B is formed simultaneously.Further, since the technology that through hole 36A is used to form component pipe core is formed, so through hole 36 can To have than the molding higher density of through hole and smaller size, and the sum of through hole 36A can be higher than molding perforation Hole.
As shown in Fig. 2, each through hole 36A, which is connected to, is electrically coupled to leading for metal column 40A for corresponding through hole 36A One in power path 38.Conductive path 38 can be single routing path of no branch/bifurcated, and be not attached to corresponding device Any other metal column 40B, inductor, resistor, capacitor, transistor, diode in part tube core 24 etc..Therefore, although In component pipe core 24, but through hole 36A is not related to adjusting related voltage/signal transmission with voltage.In addition, although leading Power path 38 is shown as straight path, but they may include horizontal metal wire.Use through hole 36A (and conductive path 38) with substitute molding through hole beneficial aspects with conductive path 38 has the function of to be routed again, and metal column 40A need not be overlapped Corresponding through hole 36A, and it is straight and vertical for moulding through hole, and cannot be routed again.
Referring to Fig. 3, encapsulating material 44 is encapsulated on component pipe core 24.Corresponding step is shown as technique shown in Figure 11 Step 204 in process.Encapsulating material 44 is assigned, and then for example, being cured in heat curing process.Encapsulating material 44 The gap between component pipe core 24 is filled, and can be contacted with adhesive layer 22.Encapsulating material 44 may include moulding compound, molding Bottom filler, epoxy resin and/or resin.After encapsulating process, the top surface of encapsulating material 44 is higher than metal column 40 and passes through The top of through-hole 14.
Next, implementing such as to chemically-mechanicapolish polish the planarisation step of (CMP) step or grinding steps to planarize packet Closure material 44, until the metal column 40 of exposure component pipe core 24.Corresponding step is shown as in process flow shown in Figure 11 Step 206.The structure of generation is shown in Fig. 3.Due to planarization, so the top surface of the top surface of metal column 40 and encapsulating material 44 It is substantially flush (coplanar).
With reference to Fig. 4, dielectric layer 46 and corresponding redistribution lines (RDL) are formed above encapsulating material 44 and component pipe core 24 48 one or more layers.Corresponding step is shown as the step 208 in process flow shown in Figure 11.According to the present invention one A little embodiments, dielectric layer 46 are formed by the polymer of PBO, polyimides etc..According to an alternative embodiment of the invention, dielectric Layer 46 is formed by the Inorganic Dielectric Material of silicon nitride, silica, silicon oxynitride etc..
RDL 48 is formed as being electrically coupled to metal column 40.RDL 48 may include metal trace (metal wire) and through-hole, be somebody's turn to do Through-hole is located at below corresponding metal trace and is connected to corresponding metal trace.According to some embodiments of the present invention, lead to It crosses shikishima plating process and forms RDL 48, wherein each RDL 48 includes seed layer (not shown) and the plating above seed layer Deposited metal material.The metal material of seed layer and plating can be formed by identical material or different materials.
During the formation of RDL 48, pattern dielectric layer 46 to be formed via openings (being occupied by RDL 48), and on Layer RDL 48 is extended in via openings to contact lower layer RDL 48 or metal column 40.In addition, some RDL 48 can be electrically interconnected Component pipe core 24.(for example, using laser) top dielectric 46 can be patterned to form opening 50 wherein, thus exposure Some metal pads in RDL 48.
Fig. 5 shows the metal pad that component pipe core 52 (including 52A, 52B and 52C) is bonded to the exposure in RDL 48 On.Corresponding step is shown as the step 210 in process flow shown in Figure 11.Through specification, component pipe core 52 also claims For 2 tube core of level.Component pipe core 52 can be bonded to metal pad 48 by solder areas 56.Each component pipe core 52 can wrap Including makes the semiconductor substrate 58 of its back side upward.Component pipe core 52 further includes the front (table directed downwardly positioned at semiconductor substrate 58 Face) at integrated circuit device 54 (active device such as including such as transistor, be not shown).Component pipe core 52A and 52B can To include the logic pipe of central processing unit (CPU) tube core, image processing unit (GPU) tube core, mobile application tube core etc. Core.Component pipe core 52A and 52B can be mutually the same.Component pipe core 52C can be the input for component pipe core 52A and 52B/ (high speed) input/output (IO) tube core of output.The RDL 60 being shown in broken lines is set to indicate component pipe core 52A and 52B to IO pipe The electrical connection of core 52C.
It is some embodiments of CPU tube core according to wherein component pipe core 52A and 52B, integrated circuit 54 may include multiple Functional circuit, control unit, memory assembly, clock circuit, pad transceiver circuit, logic gate library etc..Control The data path of unit control CPU.Memory assembly includes register file, cache memory (sram cell) etc..When Clock circuit includes clock driver, phaselocked loop (PLL), clock distribution network etc..Using logic gate library to execute logic behaviour Make.
Component pipe core 52A is electrically connected to component pipe core 24A and 24B.In addition, component pipe core 24A and 24B adjust voltage supply To be used for component pipe core 52A.Component pipe core 52B is connected to component pipe core 24C and 24D.In addition, component pipe core 24C and 24D are adjusted Voltage is for giving for component pipe core 52B.Each of component pipe core 52A and component pipe core 52B can include multiple cores The heart, and component pipe core 52A and component pipe core 52B are alternatively referred to as core chips.The component pipe core 52C that can be I/O chip connects It is connected to component pipe core 24E, component pipe core 24E adjusts voltage to be used for I/O chip 52C.According to some embodiments of the present invention, device Part tube core 52A and component pipe core 24A and 24B are completely overlapped.Component pipe core 52A can also be extended transversely with more than component pipe core 24A With the edge of 24B.Component pipe core 52B and component pipe core 24C and 24D are completely overlapped.Component pipe core 52B can also extend transversely with super Cross the edge of component pipe core 24C and 24D.
Referring to Fig. 6, encapsulating material 64 is encapsulated on component pipe core 52.Corresponding step is shown as technique shown in Figure 11 Step 212 in process.Encapsulating material 64 may include moulding compound, molded bottom filler, epoxy resin or resin.Encapsulate material The top surface of the bottom surface physical contact top dielectric 46 of material 64.After the distribution, for example, solidifying encapsulating material in heat curing process Material 64.According to some embodiments of the present invention, implement planarisation step to planarize encapsulating material 64 until encapsulating material 64 Top surface is coplanar with the top surface of component pipe core 52.Corresponding step is shown as the step 214 in process flow shown in Figure 11.Root According to alternative embodiment of the invention, do not implement to planarize, and in final structure, encapsulating material 64 includes and 52 weight of component pipe core Folded some parts.Through specification, the structure above layer 22 is known as packaging part 66, and packaging part 66 includes multiple packaging parts, often A packaging part all includes component pipe core 24A, 24B, 24C, 24D, 24E and 52A, 52B and 52C.
Next, packaging part 66 is detached from from carrier 20.Corresponding step is shown as in process flow shown in Figure 11 Step 216.The structure of generation is shown in Fig. 7.For example, by the way that UV light or laser projection are implemented packaging part 66 on adhesive layer 22 From the disengaging of carrier 20.For example, cause LTHC to decompose by the thermal conductivity that UV light or laser generate when adhesive layer 22 is formed by LTHC, And therefore carrier 20 is separated from packaging part 66.Implement grinding back surface with the base portion of grinding elements tube core 24 and encapsulating material 44 Point.Implement grinding back surface until the bottom end of exposure through hole 36A and 36B.According to some embodiments, in the bottom of component pipe core 24 Place forms metal pad and/or metal trace (not shown) to be electrically connected to through hole 36A and 36B.According to alternative embodiment, Metal pad and/or metal trace are not formed at the bottom of component pipe core 24.
In a subsequent step, implement tube core sawing with by 66 sawing of packaging part be discrete packaging part 68, discrete envelope Piece installing 68 is mutually the same, and one in discrete packaging part 68 shows in fig. 8.Corresponding step technique stream shown in Figure 11 Journey is illustrated as step 216.
Since packaging part 68 is from 68 sawing of packaging part, so the edge of encapsulating material 44 is corresponding to encapsulating material 64 Edge-perpendicular alignment.In addition, the edge of encapsulating material 44 also with the respective edges perpendicular alignmnet of dielectric layer 46.
Next, packaging part 68 is bonded to insertion piece 70 with reference to Fig. 8.According to some exemplary embodiments, pass through solder areas 71 implement engagement.According to alternative embodiment, the other joint methods for such as mixing engagement can be used.Corresponding step is shown as Step 218 in process flow shown in Figure 11.Engagement can be chip on wafer (CoW) engagement, wherein multiple packaging parts (chip) 68 is bonded to same insertion piece wafer, which includes multiple insertions identical with the insertion piece 70 shown Part.According to some embodiments of the present invention, interconnection structure (not shown) substantially identical with the interconnection structure 84 in Figure 10 can be with It is formed at the bottom of packaging part 68, wherein the RDL in interconnection structure is electrically coupled to through hole 36A and 36B.Insertion piece 70 can To include the interconnection structure 74 of 72 top of semiconductor substrate 72 (it can be silicon substrate) and semiconductor substrate.In interconnection structure 74 Middle formation metal wire and through-hole 76.Through hole 78 is formed in semiconductor substrate 72.Insertion piece 70 is without such as transistor and two The active device of pole pipe.Insertion piece 70 can not have or may include the passive device of resistor, inductor, capacitor etc. Part (not shown).Bottom filler 73 can be distributed between packaging part 68 and insertion piece 70.Then, insertion piece wafer can be by Cut into multiple packaging parts, each packaging part includes insertion piece 70 and component pipe core 24 and 52 above.
Referring to Fig. 9, for example, insertion piece 70 is bonded to package substrate 80 by solder areas 82.Corresponding step is shown as Step 220 in process flow shown in Figure 11.Package substrate 80 can be laminated substrates (few core) or can have Core.Conductive trace and/or core (not shown) in package substrate 80 are electrically connected to solder areas 82.Package substrate 80 can To have the top surface area bigger than the top surface area of part 70 inserted above.
Figure 10 shows the packaging part according to alternative embodiment.In addition to using insertion piece, these embodiments are not similar to Embodiment in Fig. 9, and packaging part 68 is spliced directly to package substrate 80.According to some embodiments of the present invention, it encapsulates Part 68 includes the interconnection structure 84 formed at the bottom surface of component pipe core 24 and encapsulating material 44.It can be used and be used to form Jie Electric layer 46 and the essentially identical method of RDL 48 and material form interconnection structure, and therefore details are not described herein.
The embodiment of the present invention has some advantageous features.As shown in Figure 9 and Figure 10, component pipe core 52A can have The top surface area bigger than total top surface area of component pipe core 24A and 24B.It correspondingly, can be below corresponding core chips 52A Direct mask placement device tube core 24A and 24B, and total top surface area of component pipe core 24A, 24B and 52A are substantially device pipe The top surface area of core 52A.It is (all by the way that IVR tube core (such as 24A and 24B) is directly placed at its corresponding core devices tube core Such as 52A) in the following, the distance from core devices tube core to its pressure regulator is minimized.Similarly, by the way that IVR tube core 24E is direct Be placed on component pipe core 52C in the following, the pressure regulator of the component pipe core from component pipe core 52C to IVR in tube core 24E distance quilt It minimizes.Therefore power-efficient is improved.As control, if IVR tube core is placed near core chips, because of IVR Tube core is closer to some cores in core chips and far from other cores in core chips, so layout is uneven.Pass through IVR tube core 24 is directly placed at core chips that IVR tube core 24 services in the following, making arrangement balancing.
Further, since component pipe core 24 is smaller, so molding through hole can be substituted by through hole 36A, otherwise, molding is passed through Through-hole will be formed (if without using the embodiment of the present invention) so that 70/ package substrate 80 of insertion piece is connected to component pipe core 52.This eliminate be used to form molding through hole cost, while be not used to form through hole 36A generation cost (because Through hole 36A and through hole 36B are formed simultaneously).In addition, IVR tube core 24 usually has low-density in their interconnection structure Metal wire and through-hole.Therefore, the interconnection structure of IVR tube core can be used for being formed embedded-type electric sensor.
According to some embodiments of the present invention, a kind of packaging part includes IVR tube core, wherein IVR tube core includes being located at first Metal column at the top surface of IVR tube core.Packaging part further includes by the first IVR die encapsulation in the first encapsulating material wherein, In, the first encapsulating material has the top surface coplanar with the top surface of metal column.A plurality of redistribution lines are located at the first encapsulating material and IVR Above tube core.A plurality of redistribution lines are electrically coupled to metal column.Core chips it is Chong Die with a plurality of redistribution lines and be bonded to it is a plurality of again Distributing line.Second encapsulating material encapsulates core chips wherein, wherein the edge of the first encapsulating material and the second encapsulating material Corresponding edge be vertically aligned with one another.Insertion piece or package substrate are located at below IVR tube core and are bonded to IVR tube core.
According to some embodiments of the present invention, a kind of packaging part includes the first IVR tube core and the 2nd IVR tube core, each IVR Tube core all includes metal column, is electrically coupled to the regulator circuit of metal column and is electrically coupled to the inductor of regulator circuit.The One encapsulating material by the first IVR tube core and the 2nd IVR die encapsulation wherein.First encapsulating material has and is located at the first IVR The coplanar top surface in the top surface of tube core and the metal column in the 2nd IVR tube core.Dielectric layer and the first IVR tube core, the 2nd IVR tube core, It is overlapped with the first encapsulating material.A plurality of redistribution lines include the part in dielectric layer.A plurality of redistribution lines are electrically coupled to One IVR tube core and the 2nd IVR tube core.First cpu chip and the second cpu chip respectively with the first IVR tube core and the 2nd IVR tube core It is overlapped and is electrically coupled to the first IVR tube core and the 2nd IVR tube core.Second encapsulating material is by the first cpu chip and the 2nd CPU Chip package is wherein.
According to some embodiments of the present invention, a kind of packaging part includes: the first component pipe core, and the first component pipe core includes half Conductor substrate, the first through hole and the second through hole through semiconductor substrate；Active circuit at the surface of semiconductor substrate； The first metal column at the top surface of first component pipe core；And first component pipe core top surface at the second metal column.First gold medal Belong to column and is electrically coupled to active circuit and the first through hole.Second metal column is electrically coupled to the second through hole, and with the first device pipe All active circuits in core are electrically disconnected.Packaging part further includes that the first component pipe core is encapsulated in the first encapsulating material therein, And the second component pipe core is Chong Die with the first component pipe core and is electrically coupled to the first component pipe core.Packaging part component is located at device pipe Below core and it is bonded to component pipe core.Packaging part component is electrically coupled to the second device pipe by the second through hole and the second metal column Core.
The embodiment provides a kind of packaging parts, comprising: the first integrated voltage regulator (IVR) tube core, wherein described First integrated voltage regulator tube core includes: metal column, at the top surface of the first integrated voltage regulator tube core；First encapsulating material Material, by the first integrated voltage regulator die encapsulation in first encapsulating material, wherein first encapsulating material has The top surface coplanar with the top surface of the metal column；A plurality of redistribution lines are located at first encapsulating material and described first and integrate Above pressure regulator tube core, wherein a plurality of redistribution lines are electrically coupled to the metal column；First core chips is and described more Redistribution lines are overlapped and are bonded to a plurality of redistribution lines；Second encapsulating material encapsulates first core chips In second encapsulating material, wherein the corresponding side at the edge of first encapsulating material and second encapsulating material Edge is vertically aligned with one another；And insertion piece or package substrate, below the first integrated voltage regulator tube core and engage To the first integrated voltage regulator tube core.
According to one embodiment of present invention, wherein the first integrated voltage regulator tube core includes: semiconductor substrate；With And through hole, it is located in the semiconductor substrate, wherein first core chips is electrically coupled to described insert by the through hole Enter part or the package substrate, without the circuit being electrically coupled in the first integrated voltage regulator tube core.
According to one embodiment of present invention, wherein the first integrated voltage regulator tube core includes: semiconductor substrate；Mutually Link structure, is located above the semiconductor substrate；And built-in inductor, it is located in the interconnection structure.
According to one embodiment of present invention, packaging part further includes and the first integrated voltage regulator tube core identical second Integrated voltage regulator tube core, the second integrated voltage regulator die encapsulation is in first encapsulating material, wherein second collection It is Chong Die with first core chips at pressure regulator tube core and be electrically coupled to first core chips.
According to one embodiment of present invention, packaging part further include: third integrated voltage regulator tube core is encapsulated in described first In encapsulating material；And input/output tube core, it is encapsulated in second encapsulating material, wherein the input/output tube core It is Chong Die with the third integrated voltage regulator tube core and be electrically coupled to the third integrated voltage regulator tube core.
According to one embodiment of present invention, packaging part further include: the 4th integrated voltage regulator tube core and the 5th integrated pressure regulation Device tube core is encapsulated in first encapsulating material, wherein the 4th integrated voltage regulator tube core and the 5th integrated pressure regulation Device tube core is identical as the first integrated voltage regulator tube core；And second core chips, with the 4th integrated voltage regulator tube core The 4th integrated voltage regulator tube core and the described 5th is overlapped and is electrically coupled to the 5th integrated voltage regulator tube core to integrate Pressure regulator tube core.
According to one embodiment of present invention, wherein the first integrated voltage regulator tube core includes semiconductor substrate, described The bottom surface of semiconductor substrate is coplanar with the bottom surface of first encapsulating material.
According to one embodiment of present invention, wherein the insertion piece is bonded to the first integrated voltage regulator tube core, with And the insertion piece extends transversely with the edge more than first encapsulating material.
According to one embodiment of present invention, wherein the insertion piece includes: additional semiconductor substrate；And it is additional Through hole, run through the additional semiconductor substrate.
The embodiments of the present invention also provide a kind of packaging parts, comprising: the first integrated voltage regulator (IVR) tube core and the second collection It at pressure regulator tube core, each includes: metal column；Regulator circuit is electrically coupled to the metal column；And inductor, it is electrically coupled To the regulator circuit；First encapsulating material, by the first integrated voltage regulator tube core and the second integrated voltage regulator pipe Core is encapsulated in first encapsulating material, wherein first encapsulating material has and the first integrated voltage regulator tube core The top surface coplanar with the top surface of the metal column in the second integrated voltage regulator tube core；Dielectric layer, it is integrated with described first Pressure regulator tube core, the second integrated voltage regulator tube core and first encapsulating material overlapping；A plurality of redistribution lines have position Part in the dielectric layer, wherein a plurality of redistribution lines are electrically coupled to the first integrated voltage regulator tube core and institute State the second integrated voltage regulator tube core；First central processing unit (CPU) chip and the second central processing unit chip, respectively with institute It states the first integrated voltage regulator tube core and the second integrated voltage regulator tube core is overlapped and is electrically coupled to described first and integrates Pressure regulator tube core and the second integrated voltage regulator tube core；And second encapsulating material, by the first central processing unit core Piece and second central processing unit chip are encapsulated in second encapsulating material.
According to one embodiment of present invention, wherein the first integrated voltage regulator tube core and the second integrated pressure regulation Device tube core is mutually the same, and first central processing unit chip and second central processing unit chip phase each other Together.
According to one embodiment of present invention, wherein the edge of first encapsulating material and second encapsulating material Corresponding edge-perpendicular alignment.
According to one embodiment of present invention, packaging part further include: insertion piece or package substrate are located at first collection At below pressure regulator tube core and the second integrated voltage regulator tube core and being bonded to the first integrated voltage regulator tube core and institute State the second integrated voltage regulator tube core.
According to one embodiment of present invention, packaging part further include: third integrated voltage regulator tube core is encapsulated in described first In encapsulating material；And input/output tube core, it is encapsulated in second encapsulating material, wherein the input/output tube core It is Chong Die with the third integrated voltage regulator tube core and be electrically coupled to the third integrated voltage regulator tube core.
The embodiments of the present invention also provide a kind of packaging parts, comprising: the first component pipe core, comprising: semiconductor substrate；The One through hole and the second through hole run through the semiconductor substrate；Active circuit, at the surface of the semiconductor substrate； First metal column, at the top surface of first component pipe core, wherein first metal column is electrically coupled to the active electricity Road and first through hole；And second metal column, at the top surface of first component pipe core, wherein described second Metal column is electrically coupled to second through hole, and second metal column with it is all active in first component pipe core Circuit is electrically disconnected；First component pipe core is encapsulated in first encapsulating material by the first encapsulating material；Second device pipe Core, it is Chong Die with first component pipe core and be electrically coupled to first component pipe core；And packaging part component, it is located at described Below first component pipe core and it is bonded to first component pipe core, wherein second through hole and second metal The packaging part component is electrically coupled to second component pipe core by column.
According to one embodiment of present invention, wherein first component pipe core includes integrated voltage regulator (IVR) tube core, It include integrated voltage regulator circuit and inductor in the integrated voltage regulator tube core and second component pipe core includes centre Manage unit (CPU) tube core.
According to one embodiment of present invention, packaging part further includes and the first integrated voltage regulator tube core identical second Integrated voltage regulator tube core, wherein the second integrated voltage regulator tube core is Chong Die with second component pipe core and is electrically coupled to Second component pipe core.
According to one embodiment of present invention, packaging part further include: a plurality of redistribution lines are located at first encapsulating material Above first component pipe core, wherein a plurality of redistribution lines are electrically coupled to first metal column and described second Metal column；And second encapsulating material, second component pipe core is encapsulated in second encapsulating material, wherein described The corresponding edge of the edge of first encapsulating material and second encapsulating material is vertically aligned with one another.
According to one embodiment of present invention, packaging part further include: multiple dielectric layers, a plurality of redistribution lines are located at institute It states in multiple dielectric layers；And solder areas, it extends in a dielectric layer at the top of the multiple dielectric layer.
According to one embodiment of present invention, wherein second metal column is not electrically coupled to first component pipe core In any passive device.
Foregoing has outlined the component of several embodiments, make those skilled in the art that reality of the invention may be better understood Apply example.It should be appreciated by those skilled in the art that they can easily be used for using based on the present invention to design or modify It realizes and other process and structures in the identical purpose of this introduced embodiment and/or the identical advantage of realization.Art technology Personnel it should also be appreciated that this equivalent constructions without departing from the spirit and scope of the present invention and without departing substantially from of the invention In the case where spirit and scope, they can make a variety of variations, replace and change herein.

Claims (20)

1. a kind of packaging part, comprising:
First integrated voltage regulator (IVR) tube core, wherein the first integrated voltage regulator tube core includes:
Metal column, at the top surface of the first integrated voltage regulator tube core；
First encapsulating material, by the first integrated voltage regulator die encapsulation in first encapsulating material, wherein described One encapsulating material has the top surface coplanar with the top surface of the metal column；
A plurality of redistribution lines are located above first encapsulating material and the first integrated voltage regulator tube core, wherein described more Redistribution lines are electrically coupled to the metal column；
First core chips, it is Chong Die with a plurality of redistribution lines and be bonded to a plurality of redistribution lines；
First core chips is encapsulated in second encapsulating material by the second encapsulating material, wherein first encapsulating The corresponding edge of the edge of material and second encapsulating material is vertically aligned with one another；And
Insertion piece or package substrate below the first integrated voltage regulator tube core and are bonded to the described first integrated tune Depressor tube core.
2. packaging part according to claim 1, wherein the first integrated voltage regulator tube core includes:
Semiconductor substrate；And
Through hole is located in the semiconductor substrate, wherein first core chips is electrically coupled to described by the through hole Insertion piece or the package substrate, without the circuit being electrically coupled in the first integrated voltage regulator tube core.
3. packaging part according to claim 1, wherein the first integrated voltage regulator tube core includes:
Semiconductor substrate；
Interconnection structure is located above the semiconductor substrate；And
Built-in inductor is located in the interconnection structure.
4. packaging part according to claim 1 further includes identical with the first integrated voltage regulator tube core second integrated Pressure regulator tube core, the second integrated voltage regulator die encapsulation is in first encapsulating material, wherein the described second integrated tune Depressor tube core is Chong Die with first core chips and is electrically coupled to first core chips.
5. packaging part according to claim 1, further includes:
Third integrated voltage regulator tube core is encapsulated in first encapsulating material；And
Input/output tube core is encapsulated in second encapsulating material, wherein the input/output tube core and the third collection It is overlapped at pressure regulator tube core and is electrically coupled to the third integrated voltage regulator tube core.
6. packaging part according to claim 1, further includes:
4th integrated voltage regulator tube core and the 5th integrated voltage regulator tube core are encapsulated in first encapsulating material, wherein described 4th integrated voltage regulator tube core and the 5th integrated voltage regulator tube core are identical as the first integrated voltage regulator tube core；And
Second core chips, and thermocouple Chong Die with the 4th integrated voltage regulator tube core and the 5th integrated voltage regulator tube core It is bonded to the 4th integrated voltage regulator tube core and the 5th integrated voltage regulator tube core.
7. packaging part according to claim 1, wherein the first integrated voltage regulator tube core includes semiconductor substrate, institute The bottom surface for stating semiconductor substrate is coplanar with the bottom surface of first encapsulating material.
8. packaging part according to claim 1, wherein the insertion piece is bonded to the first integrated voltage regulator tube core, And the insertion piece extends transversely with the edge more than first encapsulating material.
9. packaging part according to claim 8, wherein the insertion piece includes:
Additional semiconductor substrate；And
Additional through hole runs through the additional semiconductor substrate.
10. a kind of packaging part, comprising:
First integrated voltage regulator (IVR) tube core and the second integrated voltage regulator tube core, each include:
Metal column；
Regulator circuit is electrically coupled to the metal column；With
Inductor is electrically coupled to the regulator circuit；
First encapsulating material, by the first integrated voltage regulator tube core and the second integrated voltage regulator die encapsulation described In one encapsulating material, wherein first encapsulating material has to be integrated with the first integrated voltage regulator tube core and described second The coplanar top surface in the top surface of the metal column in pressure regulator tube core；
Dielectric layer, with the first integrated voltage regulator tube core, the second integrated voltage regulator tube core and first encapsulating material Overlapping；
A plurality of redistribution lines have the part being located in the dielectric layer, wherein a plurality of redistribution lines are electrically coupled to described First integrated voltage regulator tube core and the second integrated voltage regulator tube core；
First central processing unit (CPU) chip and the second central processing unit chip, respectively with first integrated voltage regulator Tube core and the second integrated voltage regulator tube core are overlapped and are electrically coupled to the first integrated voltage regulator tube core and described Second integrated voltage regulator tube core；And
First central processing unit chip and second central processing unit chip are encapsulated in institute by the second encapsulating material It states in the second encapsulating material.
11. packaging part according to claim 10, wherein the first integrated voltage regulator tube core and the second integrated tune Depressor tube core is mutually the same, and first central processing unit chip and second central processing unit chip phase each other Together.
12. packaging part according to claim 10, wherein the edge of first encapsulating material and the second encapsulating material The corresponding edge-perpendicular alignment of material.
13. packaging part according to claim 10, further includes: it is integrated to be located at described first for insertion piece or package substrate Below pressure regulator tube core and the second integrated voltage regulator tube core and it is bonded to the first integrated voltage regulator tube core and described Second integrated voltage regulator tube core.
14. packaging part according to claim 10, further includes:
Third integrated voltage regulator tube core is encapsulated in first encapsulating material；And
Input/output tube core is encapsulated in second encapsulating material, wherein the input/output tube core and the third collection It is overlapped at pressure regulator tube core and is electrically coupled to the third integrated voltage regulator tube core.
15. a kind of packaging part, comprising:
First component pipe core, comprising:
Semiconductor substrate；
First through hole and the second through hole run through the semiconductor substrate；
Active circuit, at the surface of the semiconductor substrate；
First metal column, at the top surface of first component pipe core, wherein first metal column, which is electrically coupled to, described to be had Source circuit and first through hole；And
Second metal column, at the top surface of first component pipe core, wherein second metal column is electrically coupled to described Two through holes, and second metal column and all active circuits in first component pipe core are electrically disconnected；
First component pipe core is encapsulated in first encapsulating material by the first encapsulating material；
Second component pipe core, it is Chong Die with first component pipe core and be electrically coupled to first component pipe core；And
Packaging part component below first component pipe core and is bonded to first component pipe core, wherein described The packaging part component is electrically coupled to second component pipe core by two through holes and second metal column.
16. packaging part according to claim 15, wherein first component pipe core includes the first integrated voltage regulator (IVR) tube core includes integrated voltage regulator circuit and inductor and second device in the first integrated voltage regulator tube core Tube core includes central processing unit (CPU) tube core.
17. packaging part according to claim 16, first component pipe core further include and first integrated voltage regulator The identical second integrated voltage regulator tube core of tube core, wherein the second integrated voltage regulator tube core and the second component pipe core weight It folds and is electrically coupled to second component pipe core.
18. packaging part according to claim 15, further includes:
A plurality of redistribution lines are located above first encapsulating material and first component pipe core, wherein described a plurality of to divide again Wiring is electrically coupled to first metal column and second metal column；And
Second component pipe core is encapsulated in second encapsulating material by the second encapsulating material, wherein first encapsulating The corresponding edge of the edge of material and second encapsulating material is vertically aligned with one another.
19. packaging part according to claim 18, further includes:
Multiple dielectric layers, a plurality of redistribution lines are located in the multiple dielectric layer；And
Solder areas extends in a dielectric layer at the top of the multiple dielectric layer.
20. packaging part according to claim 15, wherein second metal column is not electrically coupled to the first device pipe Any passive device in core.
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US20200381392A1 (en) 2020-12-03
US10163851B2 (en) 2018-12-25
US11244924B2 (en) 2022-02-08
US20170221858A1 (en) 2017-08-03
US20190123019A1 (en) 2019-04-25
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US9627365B1 (en) 2017-04-18

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