KR102307844B1 - Embedded voltage regulator structure and method forming same - Google Patents

Abstract

The method includes attaching a voltage regulator to a first redistribution structure of a first package. A second redistribution structure is formed over the voltage regulator, and the voltage regulator is embedded within the second redistribution structure. The first substrate is attached to the second redistribution structure to form a second package including the first package. The first voltage may be provided to the second redistribution structure and provided to the voltage regulator through the second redistribution structure. A second voltage regulator adjusts the first voltage to a second voltage and provides a second voltage to the first device die through the first redistribution structure, and an output of the voltage regulator is directly attached to the first redistribution structure.

Description

EMBEDDED VOLTAGE REGULATOR STRUCTURE AND METHOD FORMING SAME

This application claims priority to U.S. Provisional Patent Application No. 62/779,857, filed on December 14, 2018, the entire contents of which are incorporated herein by reference.

In integrated circuits, some circuit components, such as System-On-Chip (SOC) dies and Central Processing Units (CPUs), have high input/output (IO) and power consumption requirements. For example, a CPU may include multiple cores and needs to consume a significant amount of power. On the other hand, the requirements for the power provided are also high. For example, the supply voltage needs to be very stable, and the voltage drop from the voltage source to the user device needs to be low. In particular, High Performance Computing (HPC) has become more popular and widely used in advanced networking and server applications, especially in artificial intelligence (AI)-related products, because it requires high data rates, bandwidths, and low latency.

In one embodiment, a method includes attaching a voltage regulator to a first redistribution structure of a first package. A second redistribution structure is formed over the voltage regulator, and the voltage regulator is embedded within the second redistribution structure. The first substrate is attached to the second redistribution structure to form a second package including the first package. In an embodiment, the method further comprises forming an encapsulant over and around the first substrate, and singulating the second package, wherein the encapsulant is deposited on sidewalls of the first substrate after singulation. remains in In an embodiment, the method further comprises attaching the first substrate to the printed circuit board to form the first device. In an embodiment, the method further includes the voltage regulator being within a lateral extent of the first redistribution structure. In an embodiment, the method further comprises wherein a lateral extent of the second redistribution structure is greater than a lateral extent of the first substrate. In an embodiment, a method includes routing a first voltage signal to a voltage regulator through a second redistribution structure, adjusting the first voltage signal to a second voltage signal, wherein the second voltage signal is less than the first voltage signal having the voltage magnitude, and routing the second voltage signal through the first redistribution structure to the device die of the first package without routing the second voltage signal through the second redistribution structure. In an embodiment, attaching the voltage regulator to the first redistribution structure includes bonding connectors of the voltage regulator to corresponding contact pads of the first redistribution structure.

In another embodiment, a method includes providing a first voltage to a first redistribution structure of the structure. The first voltage is provided to the voltage regulator through the first redistribution structure. The voltage regulator adjusts the first voltage to the second voltage. A second voltage is provided from the voltage regulator to the first device die through a second redistribution structure, and an output of the voltage regulator is directly attached to the second redistribution structure. In an embodiment, the method further comprises providing a second voltage to the second device die, wherein the first device die corresponds to the system die and the second device die corresponds to the memory die. In an embodiment, the method further comprises an output of the voltage regulator being within a lateral extent of the first device die. In an embodiment, the method further includes the voltage regulator having a back side opposite the output, the back side being embedded within the first redistribution structure.

In another embodiment, a structure includes a substrate and a first redistribution structure disposed over the substrate. The voltage regulator is disposed over the first redistribution structure, and the connector of the voltage regulator faces the first redistribution structure. The second redistribution structure is disposed over the voltage regulator, and the voltage regulator is disposed within a lateral extent of the second redistribution structure. The device die is disposed over a second redistribution structure, which electrically couples an output of the voltage regulator to an input of the device die. In an embodiment, the structure further comprises a first encapsulant surrounding the substrate. In an embodiment, the structure further comprises a lateral extent of the substrate less than a lateral extent of the first redistribution structure. In an embodiment, the structure further includes a plurality of connectors interposed between the substrate and the first redistribution structure, the plurality of connectors coupling the substrate to the first redistribution structure. In an embodiment, the structure further includes an underfill interposed between the voltage regulator and the second redistribution structure. In an embodiment, the structure further comprises a voltage regulator embedded within the first redistribution structure. In an embodiment, the structure further comprises a voltage regulator embedded within the two or more layers of the first redistribution structure. In an embodiment, the structure further comprises that the metallization pattern of the first redistribution structure is asymmetric. In an embodiment, the structure further includes a package disposed over the device die, a third redistribution structure interposed between the package and the device die, and one or more vias coupling the third redistribution structure to the second redistribution structure.

In another embodiment, a method includes attaching a first device to a carrier substrate. A first device is laterally encapsulated within a first encapsulant, and contact pads of the first device are exposed from the first encapsulant. A second device is attached to the contact pads. A first redistribution structure is formed over the first device and the first encapsulant, the first redistribution structure embeds a second device within one or more layers of the first redistribution structure. A prepared substrate is provided and attached to the first redistribution structure opposite the second device. In an embodiment, the method further comprises removing the carrier substrate and singling the first package from the second package, the first package comprising the first device and the prepared substrate, wherein the dimensions of the prepared substrate are It is the same before and after singularization. In an embodiment, the method further comprises laterally encapsulating the prepared substrate in a second encapsulant, and forming connectors over the prepared substrate, wherein the second encapsulant covers sidewalls of the prepared substrate after singulation. . In an embodiment, the method further comprises the second device being within a lateral extent of the first device.

By integrating the embedded IVR close to the device dies in the package, the path from the output of the IVR to the device dies can be shortened, reducing the IR drop and providing a more consistent voltage output from the IVR to the device die. By forming the embedded die and attaching the IVR to the embedded die, the IVR is embedded within the redistribution structure for the package. An IVR may also be embedded between two different redistribution structures, one for an interconnect for a package component with embedded device dies, and another for distributing signals between the package component and other devices or packages. it is for The IVR may also be aligned with one or more regulated voltage pin inputs of the embedded device dies to provide a short signal from the regulated voltage pin output of the IVR to the regulated voltage pin input of the embedded device dies. The use of semi-finished substrates provides robustness to the final device, lowers cost, and improves reliability and yield. The build process for the device may proceed on a support carrier, then transfer the support to a semi-finished substrate that is later attached. Because semi-finished substrates are spaced across the devices in the build process, the resulting substrate is actually narrower than the redistribution structure the substrate supports. Other devices or packages may also be attached to the device to provide additional functionality. The process of embedding the integrated user die, attaching the IVR, forming the redistribution structure on the IVR, and attaching the semi-finished substrate can be performed in a process flow such as a one-stop-shop. , can reduce production costs.

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features have not been drawn to scale. Indeed, the dimensions of various features may be arbitrarily increased or decreased for clarity of description.
1 illustrates a cross-sectional view of an integrated circuit die in accordance with some embodiments.
2-13 illustrate cross-sectional views of intermediate steps during a process for forming a package component, in accordance with some embodiments.
14-22 illustrate cross-sectional views of intermediate steps during a process for forming a package component including an embedded integrated voltage regulator, in accordance with some embodiments.
23-29 illustrate cross-sectional views of intermediate steps during a process for forming a package component including an embedded integrated voltage regulator, in accordance with some embodiments.
30-31 illustrate cross-sectional views of intermediate steps during a process for forming a package component including an embedded integrated voltage regulator, in accordance with some embodiments.
32 is a flow diagram illustrating a process flow for regulating a voltage provided to a device die, in accordance with some embodiments.

The following disclosure provides many different embodiments or examples of implementing various features of the invention. Specific examples of components and apparatus are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature on or over a second feature in the following details may include embodiments in which the first and second features are formed in direct contact, and also the first and second features are formed in direct contact. It may include embodiments in which additional features may be formed between the first and second features such that the two features may not be in direct contact. Also, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity, and such repetition itself does not affect the relationship between the various embodiments and/or configurations disclosed.

Also, "below", "below", "below", "above", "above" to describe the relationship of another element(s) or feature(s) to one element or feature shown in the drawings. Spatial relative terms such as " and the like may be used herein for ease of description. The spatially relative terms are intended to encompass different orientations of a device in use or in operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90° or at other orientations), and thus the spatially relative descriptors used herein may be interpreted similarly.

In accordance with some embodiments, an embedded integrated voltage regulator (IVR) is provided for use with an integrated fan out (InFO) package to provide high current to an embedded device die. By embedding the voltage regulator, the output of the voltage regulator can be physically closer to the device die, and thus will experience less voltage drop (or "IR drop") due to resistance between the voltage regulator and the device die. Semiconductor technologies continue to shrink at more advanced technology nodes, making semiconductors increasingly sensitive to fluctuations in supply voltages. Placing the IVR closer to the device die provides reduced IR drop between the output of the IVR and the power input of the device die.

1 illustrates a cross-sectional view of an integrated circuit die 50 in accordance with some embodiments. The integrated circuit die 50 will be packaged in a subsequent process to form an integrated circuit package. The integrated circuit die 50 may include a logic die (eg, a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, etc.); a memory die or cube of memory dies (eg, a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (eg, a power management integrated circuit (PMIC) die), A radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (such as a digital signal processing (DSP) die), a front end die (such as an analog (AFE) die) front-end) dies), etc., or a combination thereof.

The integrated circuit die 50 may be formed within a wafer, which may include different device regions that are singulated in subsequent steps to form a plurality of integrated circuit dies. The integrated circuit die 50 may be processed according to applicable manufacturing processes to form an integrated circuit. For example, the integrated circuit die 50 includes a semiconductor substrate 52, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may include other semiconductor materials such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphorus, indium phosphorus, indium arsenide, and/or indium antimony; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates may also be used, such as multilayer or gradient substrates. The semiconductor substrate 52 has an active side, sometimes referred to as the front side (eg, the up-facing surface in FIG. 1 ), and an inactive side, sometimes referred to as the back side (eg, the down-facing surface in FIG. 1 ). ) has

Device 54 may be formed on the front surface of semiconductor substrate 52 . Device 54 may be an active device (eg, a transistor, diode, etc.), a capacitor, a resistor, or the like. An inter-layer dielectric (ILD) 56 overlies the front surface of the semiconductor substrate 52 . ILD 56 may surround and cover device 54 . The ILD 56 includes one or more dielectric layers formed of materials such as PSG (Phospho-Silicate Glass), BSG (Boro-Silicate Glass), BPSG (Boron-Doped Phospho-Silicate Glass), USG (undoped silicate glass), and the like. can do.

A conductive plug 58 extends through the ILD 56 to electrically and physically couple with the device 54 . For example, if device 54 is a transistor, conductive plug 58 may be coupled to the gate and source/drain regions of the transistor. The conductive plug 58 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, or the like, or a combination thereof. An interconnect structure 60 is over the ILD 56 and the conductive plug 58 . The interconnect structure 60 interconnects the devices 54 to form an integrated circuit. Interconnect structure 60 may be formed by, for example, metallization patterns in a dielectric layer on ILD 56 . The metallization pattern includes metal lines, such as metal line 60A and metal line 60D, formed in one or more low k dielectric layers, such as dielectric layer 60B and dielectric layer 60E, via 60C and via 60F. ), including vias such as The metallization patterns of interconnect structure 60 are electrically coupled to device 54 by conductive plug 58 .

The integrated circuit die 50 further includes pads 62, such as aluminum pads, to which external connections are made. Pads 62 are on the active side of integrated circuit die 50 , such as in and/or on interconnect structure 60 . One or more passivation films 64 are on the integrated circuit die 50 , such as portions of the interconnect structure 60 and pads 62 . An opening extends through the passivation film 64 to the pad 62 . A die connector 66 such as a conductive pillar (eg, formed of a metal such as copper) extends through the opening in the passivation film 64 and is physically and electrically coupled to each of the pads 62 . do. The die connector 66 may be formed, for example, by plating or the like. Die connector 66 is electrically coupled to respective integrated circuits of integrated circuit die 50 .

Optionally, a solder region (eg, a solder ball or solder bump) may be disposed on the pad 62 . The solder balls may be used to perform chip probe (CP) tests on the integrated circuit die 50 . A CP test may be performed on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Accordingly, only the integrated circuit die 50 that is KGD is post-processed and packaged, and dies that fail the CP test are not packaged. After testing, the solder region may be removed in subsequent processing steps.

Dielectric layer 68 may (or may not) be on the active side of integrated circuit die 50 , such as over passivation film 64 and die connector 66 . Dielectric layer 68 laterally encapsulates die connector 66 , and dielectric layer 68 laterally coextensive with integrated circuit die 50 . The dielectric layer 68 may initially bury the die connector 66 such that the top surface of the dielectric layer 68 is above the top surface of the die connector 66 . In some embodiments where the solder region is disposed on the die connector 66 , the dielectric layer 68 may also fill the solder region. Alternatively, the solder regions may be removed prior to forming the dielectric layer 68 .

The dielectric layer 68 may include a polymer such as polybenzoxazole (PBO), polyimide, or benzocyclobutene (BCB); nitrides such as silicon nitride and the like; oxides such as silicon oxide, PSG, BSG, BPSG, and the like; etc., or a combination thereof. The dielectric layer 68 may be formed by, for example, spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, die connector 66 is exposed through dielectric layer 68 during formation of integrated circuit die 50 . In some embodiments, the die connector 66 remains buried and is exposed during subsequent processing for packaging the integrated circuit die 50 . Exposing the die connector 66 may remove any solder areas that may be present on the die connector 66 .

In some embodiments, the integrated circuit die 50 is a stacked device including a plurality of semiconductor substrates 52 . For example, the integrated circuit die 50 may be a memory device, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc. including a plurality of memory dies. In such embodiments, the integrated circuit die 50 includes a plurality of semiconductor substrates 52 interconnected by through-substrate vias (TSVs). Each semiconductor substrate 52 may (or may not) have an interconnect structure 60 .

2-13 illustrate cross-sectional views of intermediate steps during a process for forming the first package component 100 , in accordance with some embodiments. A first package region 100A and a second package region 100B are shown, and one or more integrated circuit dies 50 are packaged to form an integrated circuit package within respective package regions 100A, 100B. . Integrated circuit packages may also be referred to as integrated fan out (InFO) packages.

In FIG. 2 , a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102 . The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 102 may be a wafer, allowing a plurality of packages to be simultaneously formed on the carrier substrate 102 .

The release layer 104 may be formed of a polymer-based material and may be removed along with the carrier substrate 102 from the overlying structures to be formed in subsequent steps. In some embodiments, release layer 104 is an epoxy-based thermal-release material that loses its adhesive properties when heated, such as a Light-to-Heat-Conversion (LTHC) release coating. am. In other embodiments, release layer 104 may be a UV glue that loses its adhesive properties when exposed to ultraviolet (UV) light. Release layer 104 may be dispensed as a liquid and cured, may be a laminate film laminated on carrier substrate 102 , or the like. The top surface of the exfoliation layer 104 may be planarized and may have a high degree of flatness.

3 , in some embodiments, a back redistribution structure 106 may be formed on the exfoliation layer 104 . In the illustrated embodiment, the backside redistribution structure 106 includes a dielectric layer 108 , a metallization pattern 110 (sometimes referred to as a redistribution layer or redistribution line), and a dielectric layer 112 . The rear redistribution structure 106 is optional. In some embodiments, a dielectric layer without a metallization pattern is formed on the exfoliation layer 104 instead of the backside redistribution structure 106 .

A dielectric layer 108 may be formed on the exfoliation layer 104 . A bottom surface of the dielectric layer 108 may be in contact with a top surface of the exfoliation layer 104 . In some embodiments, dielectric layer 108 is formed of a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer 108 may include a nitride such as silicon nitride; oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), and the like; formed by, etc. The dielectric layer 108 may be formed by any acceptable deposition process, such as spin coating, CVD, laminating, or the like, or a combination thereof.

A metallization pattern 110 may be formed on the dielectric layer 108 . As an example of forming the metallization pattern 110 , a seed layer is formed over the dielectric layer 108 . In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 110 . The patterning forms openings through the photoresist exposing the seed layer. A conductive material is formed over the exposed portions of the seed layer and in the openings of the photoresist. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. Then, portions of the seed layer on which the conductive material is not formed and the photoresist are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed using an acceptable etching process, such as a Ÿ‡ etch or dry etching. The conductive material and the remaining portions of the seed layer form the metallization pattern 110 .

The dielectric layer 112 may be formed on the metallization pattern 110 and the dielectric layer 108 . In some embodiments, dielectric layer 112 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, which may be patterned using a lithographic mask. In other embodiments, dielectric layer 112 may include a nitride such as silicon nitride; It is formed of oxides such as silicon oxide, PSG, BSG, BPSG, and the like. The dielectric layer 112 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. The dielectric layer 112 is then patterned to form an opening 114 exposing portions of the metallization pattern 110 . The patterning may be formed by any acceptable process, such as exposing the dielectric layer 112 to light if the dielectric layer 112 is a photosensitive material, or etching using, for example, anisotropic etching. When the dielectric layer 112 is a photosensitive material, the dielectric layer 112 may be developed after exposure.

It should be understood that the backside redistribution structure 106 may include any number of dielectric layers and metallization patterns. If more dielectric layers and metallization patterns are formed, the steps and processes discussed above may be repeated. The metallization pattern may include conductive lines and conductive vias. Conductive vias may be formed during formation of the metallization pattern by forming the conductive material of the seed layer and the metallization pattern in the opening of the underlying dielectric layer. Accordingly, the conductive vias may connect and electrically couple various conductive lines to each other.

In FIG. 4 , in embodiments using the backside redistribution structure 106 , through vias 116 extending in a direction away from the uppermost dielectric layer (eg, dielectric layer 112 ) of the backside redistribution structure 106 . may be formed in the opening 114 . As an example for forming the through vias 116 , a seed layer (not shown) is over the backside redistribution structure 106 , for example, with a dielectric layer 112 exposed by an opening 114 and a metallization pattern ( 110). In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In a particular embodiment, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. Then, a photoresist is formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of photoresist corresponds to the conductive vias. The patterning forms openings through the photoresist exposing the seed layer. A conductive material is formed over the exposed portions of the seed layer and in the openings of the photoresist. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. Portions of the seed layer on which the conductive material is not formed and the photoresist are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed using an acceptable etching process, such as a Ÿ‡ etch or dry etching. The conductive material and remaining portions of the seed layer form a through via 116 .

In FIG. 5 , integrated circuit die 50 is adhered to dielectric layer 112 by adhesive 118 . A desired type and quantity of integrated circuit die 50 is attached within each of the package regions 100A, 100B. In the illustrated embodiment, a plurality of integrated circuit dies 50 are adhered adjacent to each other, including a first integrated circuit die 50A and a second integrated circuit die 50B, wherein additional integrated circuit dies 50 are desired. It can be included as a bar. The first integrated circuit die 50A may be a logic device such as a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), a microcontroller, or the like. The second integrated circuit die 50B may be a memory device such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, or the like. In some embodiments, the integrated circuit dies 50A, 50B may be the same type of dies as the SoC die. The first integrated circuit die 50A and the second integrated circuit die 50B may be formed in processes of the same technology node, or may be formed in processes of different technology nodes. For example, the first integrated circuit die 50A may be formed with a more advanced process node than the second integrated circuit die 50B. The integrated circuit dies 50A, 50B may have different sizes (eg, different heights and/or surface areas), or may have the same dimensions (eg, the same height and/or surface areas). The space available for through via 116 in package regions 100A, 100B may be limited, particularly when integrated circuit dies 50A, 50B include devices with large footprints, such as SoCs. The use of the backside redistribution structure 106 enables an improved interconnect configuration when the package regions 100A, 100B have limited space available for the through via 116 .

Adhesive 118 is on the backside of the integrated circuit dies 50A, 50B and attaches the integrated circuit dies 50A, 50B to a backside redistribution structure 106 , such as dielectric layer 112 . Adhesive 118 may be any suitable adhesive, epoxy, die attach film (DAF), or the like. Adhesive 118 may be applied to the backside of integrated circuit dies 50A, 50B, or may be applied over the surface of carrier substrate 102 . For example, adhesive 118 may be applied to the backside of integrated circuit dies 50A, 50B prior to singulation that separates integrated circuit dies 50A, 50B.

6 , an encapsulant 142 is formed on and around the various components. After formation, encapsulant 142 encapsulates through via 116 and integrated circuit dies 50A, 50B. The encapsulant 142 may be a molding compound, epoxy, or the like. The encapsulant 142 may be applied by compression molding, transfer molding, etc., and may be formed over the carrier substrate 102 such that the through via 116 and/or the integrated circuit dies 50A, 50B are buried or covered. have. An encapsulant 142 is further formed in gap regions between the integrated circuit dies 50 . The encapsulant 142 may be applied in liquid or semi-liquid form and then cured.

In FIG. 7 , a planarization process is performed on encapsulant 142 to expose through vias 116 and die connector 66 . The planarization process may also remove material from the through via 116 , the dielectric layer 68 , and/or the die connector 66 until the die connector 66 and the through via 116 are exposed. The top surfaces of through via 116 , die connector 66 , dielectric layer 68 , and encapsulant 142 are coplanar after the planarization process. The planarization process may be, for example, chemical-mechanical polish (CMP), a grinding process, or the like. In some embodiments, planarization may be omitted, for example, if through via 116 and/or die connector 66 are already exposed.

8-11 , a front redistribution structure 122 (see FIG. 11 ) is formed over the encapsulant 142 , the through via 116 , and the integrated circuit dies 50A, 50B. The front redistribution structure 122 includes dielectric layers 124 , 128 , 132 , 136 ; and metallization patterns 126 , 130 , 134 . The metallization pattern may also be referred to as a redistribution layer or a redistribution line. The front redistribution structure 122 is shown as an example with three layers of metallization patterns. More or fewer dielectric layers and metallization patterns may be formed in the front redistribution structure 122 . If fewer dielectric layers and metallization patterns are formed, the steps and processes discussed below may be omitted. If a greater number of dielectric layers and metallization patterns are formed, the steps and processes discussed below may be repeated.

In FIG. 8 , a dielectric layer 124 is deposited over encapsulant 142 , through vias 116 , and die connector 66 . In some embodiments, dielectric layer 124 is formed of a photosensitive material, such as PBO, polyimide, BCB, or the like, that can be patterned using a lithographic mask. The dielectric layer 124 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. The dielectric layer 124 is then patterned. The patterning forms openings exposing portions of the through vias 116 and die connector 66 . The patterning may be formed by any acceptable process, such as exposing the dielectric layer 124 to light if the dielectric layer 124 is a photosensitive material, or etching using, for example, anisotropic etching. When the dielectric layer 124 is a photosensitive material, the dielectric layer 112 may be developed after exposure.

Then, a metallization pattern 126 is formed. The metallization pattern 126 includes line portions (also referred to as conductive lines) that extend along the major surface on the major surface of the dielectric layer 124 . The metallization pattern 126 further includes a through via 116 and via portions (also referred to as conductive vias) extending through the dielectric layer 124 to physically and electrically couple with the integrated circuit die 50 . As an example for forming the metallization pattern 126 , a seed layer is formed over the dielectric layer 124 and in an opening extending through the dielectric layer 124 . In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of photoresist corresponds to the metallization pattern 126 . The patterning forms openings through the photoresist exposing the seed layer. A conductive material is then formed over the exposed portions of the seed layer and in the openings of the photoresist. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and portions of the underlying seed layer forms a metallization pattern 126 . Portions of the seed layer on which the conductive material is not formed and the photoresist are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed using an acceptable etching process, such as a Ÿ‡ etch or dry etching.

In FIG. 9 , a dielectric layer 128 is deposited over the metallization pattern 126 and the dielectric layer 124 . Dielectric layer 128 may be formed in a manner similar to dielectric layer 124 , and may be formed of a material similar to dielectric layer 124 .

Then, the metallization pattern 130 is formed. The metallization pattern 130 includes line portions extending along the major surface on the major surface of the dielectric layer 128 . The metallization pattern 130 further includes via portions extending through the dielectric layer 128 to be physically and electrically coupled to the metallization pattern 126 . The metallization pattern 130 may be formed in a manner similar to the metallization pattern 126 and of a similar material. In some embodiments, the metallization pattern 130 has a different size than the metallization pattern 126 . For example, the conductive lines and/or vias of the metallization pattern 130 may be wider or thicker than the conductive lines and/or vias of the metallization pattern 126 . Also, the metallization pattern 130 may be formed with a larger pitch than the metallization pattern 126 .

In FIG. 10 , a dielectric layer 132 is deposited over the metallization pattern 130 and the dielectric layer 128 . The dielectric layer 132 may be formed in a similar manner to the dielectric layer 124 and may be formed of a material similar to the dielectric layer 124 .

Then, a metallization pattern 134 is formed. The metallization pattern 134 includes line portions extending along the major surface on the major surface of the dielectric layer 132 . The metallization pattern 134 further includes via portions extending through the dielectric layer 132 to be physically and electrically coupled to the metallization pattern 130 . The metallization pattern 134 may be formed in a manner similar to the metallization pattern 126 and of a similar material. The metallization pattern 134 is the uppermost metallization pattern of the front redistribution structure 122 . As such, all intermediate metallization patterns (eg, metallization patterns 126 , 130 ) of front redistribution structure 122 are interposed between metallization pattern 134 and integrated circuit dies 50A, 50B. is placed on In some embodiments, the metallization pattern 134 has a different size than the metallization patterns 126 , 130 . For example, the conductive lines and/or vias of the metallization pattern 134 may be wider or thicker than the conductive lines and/or vias of the metallization patterns 126 and 130 . Also, the metallization pattern 134 may be formed with a larger pitch than the metallization pattern 130 .

In FIG. 11 , a dielectric layer 136 is deposited over the metallization pattern 134 and the dielectric layer 132 . The dielectric layer 136 may be formed in a similar manner to the dielectric layer 124 and may be formed of the same material as the dielectric layer 124 . The dielectric layer 136 is the uppermost dielectric layer of the front redistribution structure 122 . As such, all metallization patterns (eg, metallization patterns 126 , 130 , 134 ) of front redistribution structure 122 are disposed between dielectric layer 136 and integrated circuit dies 50A and 50B. are placed Further, all intermediate dielectric layers (eg, dielectric layers 124 , 128 , 132 ) of front redistribution structure 122 are disposed between dielectric layer 136 and integrated circuit dies 50A, 50B.

In FIG. 12 , contact pads 138 are formed for external connection to the front redistribution structure 122 . The contact pad 138 is on a major surface of the dielectric layer 136 and has bump portions extending along the major surface, and extends through the dielectric layer 136 to physically and electrically couple with the metallization pattern 134 . It has via parts. Consequently, the contact pad 138 is electrically coupled to the through via 116 and the integrated circuit dies 50A, 50B. In some embodiments, the contact pad 138 may have a top surface that is flush with the top surface of the dielectric layer 136 . The contact pad 138 may be formed of the same material as the metallization pattern 126 . In some embodiments, the contact pad 138 has a different size than the metallization patterns 126 , 130 , 134 .

Contact pads 140 are formed to provide connector points for an IVR chip (or other device) that may be bonded in subsequent processing. The contact pad 140 extends through the dielectric layer 136 to physically and electrically couple with the metallization pattern 134 and bump portions on and extending along the major surface of the dielectric layer 136 . It may have via portions. In some embodiments, the contact pad 140 may have a top surface that is flush with the top surface of the dielectric layer 136 . The metallization pattern 134 routes specific contact pads 140 to the integrated circuit die to route the regulated voltage output from the IVR chip (discussed in more detail below) to the integrated circuit dies 50A and/or 50B. may be electrically coupled to the voltage inputs of s 50A and/or 50B. The metallization pattern 134 may electrically couple other contact pads 140 to particular contact pads 138 for routing voltage input signals to the IVR chip.

Other features and processes may also be included. For example, test structures to support three-dimensional (3D) packaging or verification testing of 3D integrated circuit (3DIC) devices may be included. The test structures may include test pads formed in the wiring layer or on the substrate, for example, to enable 3D packaging or testing of 3DICs, the use of probes and/or probe cards, and the like. Verification tests can be performed on the final structure as well as the intermediate structure. In addition, the structures and methods disclosed herein can be used with test methods that incorporate interim verification of known good dies to increase yield and reduce cost.

In FIG. 13 , for example, the singulation process is performed by sawing along the scribe line region 150 , for example, between the first package region 100A and the second package region 100B. The sawing separates the first package area 100A from the second package area 100B. In some embodiments, prior to singulation, carrier substrate debonding is performed to detach (or “debond”) the carrier substrate 102 from the backside redistribution structure 106 , eg, the dielectric layer 108 . do. According to some embodiments, debonding projects light, such as laser light or UV light, onto the release layer 104 so that the release layer 104 decomposes due to the heat of the light and the carrier substrate 102 can be removed. includes doing The structure is then turned over and placed on a tape, such as tape 148 . In some embodiments, the singulation process may be performed by sawing from the rear surface of the first package area 100A toward the front surface of the first package area 100A. In other embodiments, the structure is turned over again and another tape (not shown) so that the singulation process can be performed by sawing from the front side of the first package area 100A toward the back side of the first package area 100A. may be placed on the Following the singulation process, the first package region 100A is singulated from the second package region 100B to create the first package component 100 .

14-21 show cross-sectional views of intermediate steps during the process for forming the second package component 200 . In FIG. 14 , one or more singulated first package components 100 may be mounted to a carrier substrate 202 . Additional package components (not shown) may also be mounted to the carrier substrate 202 . The additional package component may be the same as the first package component 100 or may be a different type of package component. The carrier substrate 202 may be similar to the carrier substrate 102 . The carrier substrate 202 may have a release layer 204 formed on the carrier substrate 202 , the release layer 204 being formed using materials and processes such as those described above with respect to the release layer 104 . can be

In FIG. 15 , an encapsulant 206 is formed on and around the various components. After formation, the encapsulant 206 encapsulates the first package component 100 . The encapsulant 206 may be a molding compound, epoxy, or the like. The encapsulant 206 may be applied by compression molding, transfer molding, or the like, and formed over the carrier substrate 202 such that the first package component 100 is buried or covered. An encapsulant 206 is further formed in gap regions between the first package components 100 . The encapsulant 206 may be applied in liquid or semi-liquid form and then cured. Following formation of encapsulant 206 , a planarization process is performed on encapsulant 206 to expose contact pads 138 and contact pads 140 . The top surfaces of contact pad 138 , contact pad 140 , and encapsulant 206 are coplanar after the planarization process. The distance between the top surface of the encapsulant 206 and the top surface of the dielectric layer 136 may be between about 5 μm and about 100 μm, such as about 10 μm, although other distances are conceivable and may be used. In some other embodiments, the planarization process may cause the top surface of the encapsulant 206 and the top surface of the dielectric layer 136 to be coplanar. The planarization process may be, for example, chemical-mechanical polish (CMP), a grinding process, or the like. In some embodiments, planarization may be omitted, for example, if contact pad 138 and contact pad 140 are already exposed.

In FIG. 16 , an integrated voltage regulator (IVR) 210 is provided and aligned to the contact pads 140 . IVR 210 includes contact pads 205 , each of which corresponds to a contact pad of contact pads 140 . The IVR 210 may also include a conductive connector 207 formed on each contact pad 205 . The conductive connector 207 may be a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a micro bump, a bump formed by an electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, or the like. . The conductive connector 207 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connector 207 is formed by initially forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the solder layer is formed on the structure, a reflow may be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 207 includes metal pillars (eg, copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillar may be solder free and has substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillar. The metal cap layer may include nickel, tin, tin lead, gold, silver, palladium, indium, nickel palladium gold, nickel gold, or the like, or a combination thereof, and may be formed by a plating process. The conductive connector 207 may have a pitch of between about 20 μm and about 80 μm, such as about 40 μm, although other pitches are conceivable and may be used. The pitch corresponds to the placement of the contact pads 140 . The IVR 210 may be positioned using a pick and place process or other suitable process.

IVR 210 may have a thickness between about 10 μm and about 200 μm, such as about 30 μm, although other dimensions are conceivable and may be used. The IVR 210 may have a width dimension of between about 2 mm and 40 mm, such as about 5 mm, and a depth dimension (in and out of the ground) of between about 2 mm and about 80 mm, such as about 5 mm. However, other dimensions are conceivable and may be used.

In FIG. 17 , IVR 210 is bonded to contact pad 140 by conductive connector 207 . In some embodiments, the conductive connector 207 may be reflowed to couple the IVR 210 to the contact pad 140 . In some embodiments, bonding may be achieved by the illustrated flip chip process. In other embodiments, IVR 210 may be a surface mount device. In still other embodiments, the IVR 210 may be bonded by a wire bonding process.

In some embodiments, an epoxy flux (not shown) may be formed on the conductive connector 207 before the conductive connector 207 is reflowed, and the IVR 210 attaches to the first package component 100 . At least a portion of the epoxy portion of the epoxy flux remains after being deposited.

In some embodiments, an underfill 208 is formed between the first package component 100 and the IVR 210 to surround the conductive connector 207 . The underfill 208 may reduce stress and protect against bonding due to reflow of the conductive connector 207 . The underfill may be formed by a capillary flow process after the IVR 210 is attached, or may be formed by a suitable deposition method before the IVR 210 is attached. In embodiments where an epoxy flux is formed, the epoxy flux may act as the underfill 208 .

Although only one IVR 210 is shown, it should be understood that multiple IVR devices may be used as appropriate. The lateral extent of the IVR 210 may be within the lateral extent of the front redistribution structure 122 (see FIG. 12 ). In other words, the footprint of the IVR 210 may be completely overlapped by the footprint of the first package component 100 . In other embodiments, an edge portion of the IVR 210 may protrude beyond a lateral extent of the front redistribution structure 122 . In some embodiments, the design of the front redistribution structure 122 is a series of metallization patterns of the front redistribution structure 122 (eg, the metallization patterns 126 , 130 , 134 of FIG. 12 ). can provide one or more vias of the , so that the vias provide a short path to the voltage input of the integrated circuit dies 50A and/or 50B.

In some embodiments, vias may be aligned and stacked through each dielectric layer of the redistribution structure to form a short path. In some embodiments, the IVR 210 may have a regulated voltage output vertically aligned with the voltage input of the integrated circuit dies 50A and/or 50B, in which embodiments the via also connects each dielectric layer. Aligned and stacked therethrough, they form a straight vertical path between the IVR 210 output voltage portion and the voltage input portion of the integrated circuit dies 50A and/or 50B. In some embodiments, the total length of the path from the regulated voltage output of the IVR 210 to the voltage input of the integrated circuit dies 50A and/or 50B is between about 20 μm and about 1,000 μm, about 100 μm. and about 5,000 μm, or between about 100 μm and about 40,000 μm.

The short path is smaller than a voltage regulator mounted next to the integrated circuit dies 50A and/or 50B, for example using a micro lead-frame chip carrier (MLCC), the IVR 210 . to provide an IR drop from to the integrated circuit dies 50A and/or 50B. In some embodiments, the total IR drop may be between about 0.5% and 2.5%, such as about 1.4%, although other values are conceivable. In contrast, a voltage regulator mounted via an MLCC can have an IR drop of about 4.5% or more.

Those skilled in the art will recognize that other devices may be used in place of or in addition to the IVR 210 . In some embodiments, devices such as an integrated package device (IPD), memory device such as SRAM, etc., silicon bridges, and/or other devices may be used to create a system on wafer device. For ease of reference, the following disclosure specifically describes IVR 210 , but it should be understood that any of these devices may be used and are within the scope of the present disclosure.

In FIG. 18 , a redistribution structure 240 (see FIG. 11 ) is formed over the encapsulant 206 , the first package component 100 , and the IVR 210 . The redistribution structure 240 includes dielectric layers 212 , 218 , 222 , 226 , 230 , 234 , 238 ; and metallization patterns 216 , 220 , 224 , 228 , 232 , 236 . The metallization pattern may also be referred to as a redistribution layer or a redistribution line. The redistribution structure 240 is shown as an example with six layers of metallization patterns. More or fewer dielectric layers and metallization patterns may be formed in the redistribution structure 240 .

A dielectric layer 212 is deposited over the encapsulant 206 and the contact pads 138 and the IVR 210 . In some embodiments, dielectric layer 212 is formed of a photosensitive material, such as PBO, polyimide, BCB, or the like, that can be patterned using a lithographic mask. The dielectric layer 212 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. The dielectric layer 212 may have a thickness between about 35 μm and about 250 μm thick, such as about 50 μm thick, although other thicknesses may be used and are contemplated. The dielectric layer 212 is then patterned. The patterning forms an opening exposing portions of the contact pad 138 . The patterning may be formed by any acceptable process, such as exposing the dielectric layer 212 to light if the dielectric layer 212 is a photosensitive material, or etching using, for example, anisotropic etching. When the dielectric layer 212 is a photosensitive material, the dielectric layer 212 may be developed after exposure.

In some embodiments, the distance D1 between the top surface of the IVR 210 and the top surface of the dielectric layer 212 is between about 0 μm (coplanar) and about 100 μm, such as about 15 μm, other Dimensions are conceivable. In other embodiments, the top surface of the IVR 210 may protrude above the top surface of the dielectric layer 212 (see FIG. 19 ).

Then, a metallization pattern 216 is formed. The metallization pattern 216 includes line portions (also referred to as conductive lines) that extend along the major surface on the major surface of the dielectric layer 212 . The metallization pattern 216 further includes through vias 214 (also referred to as conductive vias) extending through the dielectric layer 212 to physically and electrically couple with the contact pads 138 . As an example for forming the metallization pattern 216 , a seed layer is formed over the dielectric layer 212 and in an opening extending through the dielectric layer 212 . In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of photoresist corresponds to the metallization pattern 216 . The patterning forms openings through the photoresist exposing the seed layer. A conductive material is then formed over the exposed portions of the seed layer and in the openings of the photoresist. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and portions of the underlying seed layer forms a metallization pattern 216 . Portions of the seed layer on which the conductive material is not formed and the photoresist are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed using an acceptable etching process, such as a Ÿ‡ etch or dry etching.

The process described above for forming the dielectric layer 212 and the metallization pattern 216 may be repeated as needed to form a desired number of layers of the redistribution structure 240 . In the illustrated embodiment, dielectric layer 218 and metallization pattern 220 are formed, followed by dielectric layer 222 and metallization pattern 224 , followed by dielectric layer 226 and metallization pattern 228 . forming, then forming dielectric layer 230 and metallization pattern 232 , and then forming dielectric layer 212 and metallization pattern 216 to form dielectric layer 234 and metallization pattern 236 . can be repeated. A final dielectric layer 238 may be formed over the metallization pattern 236 , which may be formed in a manner similar to the dielectric layer 212 . Dielectric layer 238 is the uppermost dielectric layer of redistribution structure 240 .

In FIG. 19 , the IVR 210 has a top surface that protrudes above the top surface of the dielectric layer 212 . The IVR 210 may protrude a distance D2, where D2 is between about 0 μm (coplanar) and about 50 μm, such as about 15 μm, although other dimensions are conceivable. In such embodiments, IVR 210 may protrude into a plurality of dielectric layers of redistribution structure 240 . The distance D3 between the top surface of the IVR 210 and the top of the next dielectric layer of the redistribution structure 240 may be between about 0 μm (coplanar) and about 100 μm, such as about 15 μm, Other dimensions are conceivable.

In FIG. 20 , under-bump metallurgies (UBM) 242 are formed for external connection to the front redistribution structure 240 . UBM 242 is on and has bump portions extending along the major surface of dielectric layer 238 , and vias extending through dielectric layer 238 to physically and electrically couple with metallization pattern 236 . have parts. As a result, the UBM 242 is electrically coupled to the through via 214 and the first package component 100 . The UBM 242 may be formed of the same material as the metallization pattern 236 . In some embodiments, UBM 242 has a different size than metallization patterns 216 , 220 , 224 , 228 , 232 , 236 . A specific UBM 242 is coupled to the IVR 210 to route the high voltage signal to the IVR 210 for conditioning and conversion to a low voltage signal for providing to the first package component 100 .

In FIG. 21 , a conductive connector 246 is formed on the UBM 242 . The conductive connector 246 may be a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a micro bump, a bump formed by an electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, or the like. . The conductive connector 246 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connector 246 is formed by initially forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the solder layer is formed on the structure, a reflow may be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 246 includes metal pillars (eg, copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillar may be solder free and has substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillar. The metal cap layer may include nickel, tin, tin lead, gold, silver, palladium, indium, nickel palladium gold, nickel gold, or the like, or a combination thereof, and may be formed by a plating process.

22 , instead of forming the UBM 242 , a metallization pattern 244 may be formed over the dielectric layer 238 , in accordance with some embodiments. The metallization pattern 244 may be formed using materials and processes similar to those described above with respect to the metallization pattern 216 . The metallization pattern 244 may have regions formed in a pattern suitable for forming a conductive connector 246 that may be formed using processes and materials as described above.

In FIG. 23 , a semi-finished substrate 300 (also referred to as substrate 300 ) is provided and, in FIG. 24 , bonded to the second package component 200 . The substrate 300 provides strength and rigidity for the first package component 100 . The substrate 300 reduces warpage problems that may be caused by a coefficient of thermal expansion (CTE) mismatch between the different layers of the redistribution structure 240 . Without the substrate 300 , when the carrier substrate 202 is removed, the second package component 200 is likely to experience warpage problems. In the absence of the substrate 300 , the redistribution structures 240 are interconnected in each layer such that the left side of the pattern is the same as the right side of the pattern for any particular one of the metallization patterns, in order to reduce the warping effect. It is possible to use metallization patterns that mirror the However, since the substrate 300 is provided, the substrate core 310 and other layers provide stability and stiffness to prevent warping, so that each of the metallization patterns 216 , 220 , 224 , 228 , 232 , 236 is Allows it to vary across the entire layer, which provides more flexibility in pattern routing. In other words, the right side of the metallization patterns may be different from the left side of the metallization patterns, or the right side of the metallization patterns may be asymmetrical with the left side of the metallization pattern.

Using the semi-finished substrate 300 also has the advantage that the substrate 300 is manufactured in a separate process. Using a separate process to form the substrate 300 may lead to greater reliability and higher substrate yield. In addition, since the substrate 300 is formed in a separate process, the substrate 300 can be individually tested, so that a known good substrate 300 is used in a subsequent process of attaching the substrate 300 to the second package component 200 . let this be used.

The semi-finished substrate 300 may include a substrate core 310 having vias 312 formed therein, and bonding pads 322 over the substrate core 310 . Substrate 300 may also have bonding pads 342 formed on the bottom of substrate 300 . In some embodiments, the via 312 may be surrounded by a barrier layer 314 . The substrate 300 may be formed in a separate process. The substrate core 310 may be made of a semiconductor material such as silicon, germanium, or diamond. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphorus, silicon germanium carbide, gallium arsenide phosphorus, gallium indium phosphorus, combinations thereof, and the like may also be used. Additionally, the substrate core 310 may be a silicon-on-insulator (SOI) substrate. In general, an SOI substrate includes a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. The substrate core 310, in one alternative embodiment, is based on an insulating core, such as a glass fiber reinforced resin core. One exemplary core material is a glass fiber resin such as FR4 (flame retardant grade 4 material). Alternatives to core materials include pre-impregnated composite fibers (prepregs), insulating or build-up films, paper, glass fibers, non-woven glass fabrics, silicone, resin coated copper (RCC), molding materials, polyimides, photo image dielectrics (PIDs), ceramics, glass, bismaleimide-triazine (BT) resins, or alternatively, printed circuit board (PCB) materials or films. A build-up film including a laminate and coating or other laminate such as Ajinomoto Build-up Film (ABF) may be used for the substrate core 310 .

The substrate core 310 may include active and passive devices (not shown), or may be free of active devices, passive devices, or both. Those skilled in the art will appreciate that a wide variety of devices may be used, such as transistors, capacitors, resistors, combinations thereof, and the like. Such devices may be formed using any suitable methods.

A top redistribution structure 340 and/or a bottom redistribution structure 360 may be formed on the semi-finished substrate 300 . The top redistribution structure 340 includes dielectric layers 324 , 328 , 332 ; and metallization patterns 326 , 330 , 334 . The metallization pattern may also be referred to as a redistribution layer or a redistribution line. The top redistribution structure 340 is shown as an example with three layers of metallization patterns in three dielectric layers. More or fewer dielectric layers and metallization patterns may be formed in the uppermost redistribution structure 340 .

Dielectric layer 324 may be formed using processes and materials similar to those discussed above with respect to dielectric layer 212 . Further, the dielectric layer 324 may include a prepreg, RCC, a molding material, polyimide, PID, or the like. Dielectric layer 324 may also be made of one or more lamination layers or coatings. The metallization pattern 326 may be formed using materials and processes similar to those discussed above with respect to the metallization pattern 216 . Following the formation of the metallization pattern 326 , the process of forming the dielectric layer and the metallization pattern may be repeated as needed to form a desired number of layers of the top redistribution structure 340 . In the illustrated embodiment, the process of forming dielectric layer 324 and metallization pattern 326 forms dielectric layer 328 and metallization pattern 330 , followed by dielectric layer 332 and metallization pattern 334 . can be repeated to form. The dielectric layer 332 is the uppermost dielectric layer of the uppermost redistribution structure 340 .

The bottom redistribution structure 360 includes dielectric layers 344 , 348 , 352 ; and metallization patterns 346 , 350 , 354 . The bottom redistribution structure 360 is shown as an example with three layers of metallization patterns in three dielectric layers. More or fewer dielectric layers and metallization patterns may be formed in the bottom redistribution structure 360 .

The bottom redistribution structure 360 of the substrate 300 inverts the substrate 300 , and the bottom redistribution structure 360 uses processes and materials similar to those discussed above with respect to the top redistribution structure 340 . ) can be formed by forming In particular, dielectric layers 344, 348, and 352 may be formed similarly to dielectric layers 324, 328, and 332, respectively. Similarly, the metallization patterns 346 , 350 , and 354 may be formed similarly to the metallization patterns 326 , 330 , and 334 , respectively.

In FIG. 24 , the substrate 300 is bonded to the second package component 200 by a conductive connector 246 to form a package 400 . In some embodiments, the substrate 300 may be disposed on the conductive connector 246 using a pick and place process or other suitable processes, and may be disposed on the conductive connector 246 by a flip chip bonding process or other suitable bonding process. can be joined to In some embodiments, the conductive connector 246 is reflowed to attach the substrate 300 to the second package component 200 with the metallization pattern 354 . The conductive connector 246 electrically and/or physically couples the substrate 300 to the second package component 200 .

Before the conductive connector 246 is reflowed, an epoxy flux (not shown) may be formed on the conductive connector 122 , and at least a portion of the epoxy portion of the epoxy flux may form a semi-finished substrate 300 on the second conductive connector 122 . It remains after being attached to the package component 200 . This remaining epoxy portion may act as an underfill to reduce stress and protect the bonding resulting from reflow of the conductive connector 246 . In some embodiments, an underfill (not shown) may be formed between the second package component 200 and the substrate 300 and around the conductive connector 246 . The underfill may be formed by a capillary flow process after the substrate 300 is attached, or may be formed by a suitable deposition method before the substrate 300 is attached.

In some embodiments, passive devices (eg, a surface mount device (SMD), not shown) are also attached to the first package component 100 (eg, to the contact pad 140 ). or bonding a pad associated with the metallization pattern 334 or metallization pattern 354 to the second package component 200 (eg, to the UBM 242 ) or to the substrate 300 (eg, the metallization pattern 334 ). for) can be attached. Passive devices may be attached to the first package component 100 prior to forming the redistribution structure 240 to form the second package component 200 , or may be attached to the second package component prior to attaching the substrate 300 . 200 , or before or after mounting the substrate 300 to the second package component 200 .

In FIG. 25 , multiple packages 400 (eg, packages 400A, 400B) are shown formed on a carrier substrate 202 , which are later singulated into individual packages. It should be understood that additional such packages may be formed on the carrier substrate 202 . An enlarged area is shown where substrate 300A of package 400A is adjacent substrate 300B of package 400B. Substrate 300A is separated from adjacent substrate 300B by a distance D4 between about 25 μm and about 1,000 μm, such as about 500 μm. This distance provides a space for singling the package 400A from the package 400B. As a result of the process of forming package 400A and package 400B, each of the substrates 300A, 300B will be smaller than the second package components 200A, 200B, respectively. In other words, the package 400 will result in a substrate that is not as wide as the package components attached to it. This will be shown in further discussion below.

In FIG. 26 , encapsulant 406 is formed on, around, and between substrates 300A and 300B. After formation, encapsulant 406 encapsulates substrates 300A, 300B. The encapsulant 406 may be a molding compound, epoxy, or the like. The encapsulant 406 may be applied by compression molding, transfer molding, or the like, and formed over the carrier substrate 202 so that the semi-finished substrates 300A, 300B are buried or covered. An encapsulant 406 is further formed between the semi-finished substrates 300A and each of the second package components 200A, 200B. The encapsulant 406 may be applied in liquid or semi-liquid form and then cured. Following formation of the encapsulant 406 , a planarization process is performed on the encapsulant 406 to expose the metallization pattern 334 (see FIG. 23 ). The top surfaces of the metallization pattern 334 and the encapsulant 406 are coplanar after the planarization process. The planarization process may be, for example, chemical-mechanical polish (CMP), a grinding process, or the like. In some embodiments, planarization may be omitted, for example if the metallization pattern 334 is already exposed. Other processes may be used to achieve similar results. For example, a dielectric or passivation layer may be formed over the metallization pattern 334 prior to forming the encapsulant 406 . In such cases, a dielectric or passivation layer may be patterned in a subsequent step to expose portions of the metallization pattern 334 .

In FIG. 27 , a dielectric layer 410 is formed over semi-finished substrates 300A and 300B. In some embodiments, dielectric layer 410 is a solder resist and may be formed of a polymer that may be a photosensitive material such as PBO, polyimide, BCB, etc. that may be patterned using a lithographic mask. In other embodiments, dielectric layer 410 may include a nitride such as silicon nitride; It is formed of oxides such as silicon oxide, PSG, BSG, BPSG, and the like. The dielectric layer 410 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. The dielectric layer 410 is then patterned to form openings exposing portions of the metallization pattern 334 (see FIG. 23 ), which openings correspond to, for example, connector locations in a later formed ball grid array. . The patterning may be formed by any acceptable process, such as exposing the dielectric layer 410 to light if the dielectric layer 410 is a photosensitive material, or etching using, for example, anisotropic etching. When the dielectric layer 410 is a photosensitive material, the dielectric layer 410 may be developed after exposure.

A conductive connector 414 is formed in the opening of the dielectric layer 410 . In some embodiments, an under bump metal portion (eg, similar to UBM 242 ) may be formed prior to forming the conductive connector 414 . In other embodiments, a conductive connector 414 may be formed on exposed portions of the metallization pattern 334 . The conductive connector 414 may be a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a micro bump, a bump formed by an electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, or the like. . The conductive connector 414 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connector 414 is formed by initially forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the solder layer is formed on the structure, a reflow may be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 414 includes metal pillars (eg, copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillar may be solder free and has substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillar. The metal cap layer may include nickel, tin, tin lead, gold, silver, palladium, indium, nickel palladium gold, nickel gold, or the like, or a combination thereof, and may be formed by a plating process.

28 , to detach (or “debond”) the carrier substrate 202 (see FIG. 27 ) from the second package component 200 , eg, from the second package components 200A, 200B. Carrier substrate debonding is performed. According to some embodiments, debonding projects light, such as laser light or UV light, onto the release layer 204 so that the release layer 204 decomposes due to the heat of the light and the carrier substrate 202 can be removed. includes doing The structure is then turned over and placed on tape 420, such as blue tape for singulation.

29 , in some embodiments, a singulation process is performed by sawing along a scribe line region, eg, between package 400A and package 400B. Sawing separates the package 400A from the package 400B. The resulting singulated package 400 is from either package 400A or package 400B.

Then, each singulated package 400 is mounted to a printed circuit board 600 using a conductive connector 414 . Printed circuit board 600 may include active and passive components as well as other devices. In some embodiments, the printed circuit board 600 may be an interposer or other package component. Printed circuit board 600 may include a voltage source device 601 that is mounted to printed circuit board 600 to provide a high voltage signal to conductive connector 414, the high voltage signal being It is then routed through the substrate 300 to the various components.

29 , due to processing techniques, width D5 and width D6 of encapsulant 406 remain on each side of semifinished substrate 300 . Other sides of the semi-finished substrate 300 may have a similar residual amount of encapsulant 406 on those sides. The widths D5 and D6 are greater than zero and can reach about 500 μm, for example between about 5 μm and about 500 μm, such as about 250 μm, although other values are conceivable. In some embodiments, the width of the encapsulant 406 may be uniform on each side of the semi-finished substrate 300 . In other embodiments, the width of the encapsulant 406 may be different on each side of the substrate 300 . In this way, the width of the semi-finished substrate 300 is less than the width of the second package component 200 by the sum of D5 and D6. In other words, the redistribution structure 240 is wider than the substrate 300 . In other words, the substrate has a smaller footprint than the supporting second package component 200 .

In some embodiments, the conductive connector 414 is reflowed to attach the package 400 to corresponding bond pads of the printed circuit board 600 . The conductive connector 414 electrically and/or physically couples the printed circuit board 600 to the package 400 .

Before the conductive connector 414 is reflowed, an epoxy flux (not shown) may be formed on the conductive connector 414 , and at least a portion of the epoxy portion of the epoxy flux is transferred to the package 400 by the printed circuit board 600 . ) remains after being attached to it. This remaining epoxy portion can act as an underfill to reduce stress and protect the bonding resulting from reflow of the conductive connector 414 .

It should be understood that package 400 may be implemented with other device stacks. For example, although a PoP structure is shown, package 400 may also be implemented as a Flip Chip Ball Grid Array (FCBGA) package. In such embodiments, package 400 may be mounted on a substrate, such as printed circuit board 600 . A lid or heat spreader may be attached to the package 400 .

Other features and processes may also be included. For example, test structures may be included to support validation testing of 3D packaging or 3DIC devices. The test structures may include test pads formed in the wiring layer or on the substrate, for example, to enable 3D packaging or testing of 3DICs, the use of probes and/or probe cards, and the like. Verification tests can be performed on the final structure as well as the intermediate structure. In addition, the structures and methods disclosed herein can be used with test methods that incorporate interim verification of known good dies to increase yield and reduce cost.

30 , in some embodiments, third package component 500 is coupled to first package component 100 of package 400 to form package 800 . One of the third package components 500 is combined in each package 800A, 800B to form an integrated circuit device stack in each region of the first package component 100 . In such embodiments, the third packaged component 500 is either before or after singulation of the first package component 100 (see FIG. 10 ) or the singulation of the second package component 200 (see FIG. 29 ). It may be coupled to the first package component 100 before or after singulation. For example, the carrier substrate 202 can be removed and the package 400 can be turned over and placed on the tape 440 (see FIG. 28 ). The third package component 500 may then be attached. In embodiments that do not use the third package component 500 , the rear redistribution structure 106 and the through via 116 may be omitted.

The third package component 500 includes a substrate 502 and one or more stacked dies 510 (eg, dies 510A, 510B) coupled to the substrate 502 . Although a set of stacked dies 510 ( 510A, 510B) is shown, in other embodiments, a plurality of stacked dies 510 (each having one or more stacked dies) are on the same side of the substrate 502 . It can be arranged side by side coupled to. The substrate 502 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, a compound material such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphorus, silicon germanium carbide, gallium arsenide phosphorus, gallium indium phosphorus, combinations thereof, and the like may also be used. Additionally, the substrate 502 may be a silicon-on-insulator (SOI) substrate. In general, an SOI substrate includes a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. Substrate 502, in one alternative embodiment, is based on an insulating core, such as a fiberglass reinforced resin core. One exemplary core material is a fiberglass resin such as FR4. Alternative core materials include bismaleimide-triazine (BT) resins, or alternatively, other printed circuit board (PCB) materials or films. A build-up film such as Ajinomoto build-up film (ABF) or other laminate may be used for the substrate 502 .

The substrate 502 may include active and passive devices (not shown). A wide variety of devices may be used, such as transistors, capacitors, resistors, combinations thereof, and the like, to create the structural and functional requirements of the design for the third package components 500 . Such devices may be formed using any suitable methods.

The substrate 502 may also include metallization layers (not shown) and conductive vias 508 . A metallization layer can be formed over active and passive devices and is designed to connect various devices to form functional circuitry. The metal layers may be formed of alternating layers of dielectric material (eg, low k dielectric material) and conductive material (eg, copper) with vias interconnecting the layers of conductive material, which may be (deposition, damascene, dual may be formed through any suitable process (such as mashin, etc.). In some embodiments, the substrate 502 is substantially free of active and passive devices.

The substrate 502 may have a bonding pad 504 on a first side of the substrate 502 to couple to the stacked dies 510 , and a second side of the substrate 502 to couple to a conductive connector 520 . may have a bonding pad 506 thereon, a second side opposite the first side of the substrate 502 . In some embodiments, bonding pads 504 , 506 are formed by forming recesses (not shown) in dielectric layers (not shown) on first and second sides of substrate 502 . The recess may be formed to allow the bonding pads 504 and 506 to be embedded in the dielectric layer. In other embodiments, the recesses are omitted since the bonding pads 504 and 506 may be formed on the dielectric layer. In some embodiments, bonding pads 504 and 506 include a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, etc., or a combination thereof. The conductive material of the bonding pads 504 and 506 may be deposited over a thin seed layer. The conductive material may be formed by an electrochemical plating process, an electroless plating process, CVD, atomic layer deposition (ALD), PVD, or the like, or a combination thereof. In an embodiment, the conductive material of the bonding pads 504 , 506 is copper, tungsten, aluminum, silver, gold, etc., or a combination thereof.

In an embodiment, bonding pad 504 and bonding pad 506 are UBMs comprising three layers of conductive material, such as a titanium layer, a copper layer, and a nickel layer. of other materials and layers to form bond pads 504 , 506 , such as a chromium/chromium copper alloy/copper/gold arrangement, a titanium/titanium tungsten/copper arrangement, or a copper/nickel/gold arrangement. Arrangements may be used. Any suitable materials or layers of materials that may be used for bonding pads 504 and 506 are intended to be fully included within the scope of this application. In some embodiments, conductive vias 508 extend through the substrate 502 and couple at least one of the bonding pads 504 to at least one of the bonding pads 506 .

In the illustrated embodiment, stacked die 510 is coupled to substrate 502 by wire bonds 512 , although other connections may be used, such as conductive bumps. In an embodiment, stacked die 510 is a stacked memory die. For example, the stacked die 510 may be a memory die such as a low power (LP) double data rate (DDR) memory module, such as memory modules such as LPDDR1, LPDDR2, LPDDR3, and LPDDR4.

Stacked die 510 and wire bond 512 may be encapsulated by molding material 514 . Molding material 514 may be molded onto stacked die 510 and wire bond 512 using, for example, compression molding. In some embodiments, the molding material 514 is a molding compound, polymer, epoxy, silicon oxide filler, etc., or a combination thereof. A curing process may be performed to cure the molding material 514 ; The curing process may be thermal curing, UV curing, or the like, or a combination thereof.

In some embodiments, stacked die 510 and wire bond 512 are embedded in molding material 514 , and after curing of molding material 514 , remove excess portions of molding material 514 and remove the third package. To provide a substantially flat surface for component 500, a planarization step, such as grinding, is performed.

After the third package component 500 is formed, the third package component 500 passes through the metallization pattern of the conductive connector 520 , the bonding pad 506 , and the backside redistribution structure 106 (see FIG. 3 ). mechanically and electrically bonded to the first package component 100 . In some embodiments, the stacked die 510 includes a wire bond 512 , bond pads 504 , 506 , a conductive via 508 , a conductive connector 520 , a back redistribution structure 106 , and a through via 116 . ), and to the integrated circuit dies 50A, 50B (see FIG. 5 ) and/or the IVR 210 (see FIG. 17 ) via the front redistribution structure 122 .

In some embodiments, a solder resist is formed on the opposite side of the substrate 502 from the stacked die 510 . A conductive connector 520 may be disposed within the opening in the solder resist to electrically and mechanically couple to conductive features (eg, bond pad 506 ) in the substrate 502 . Solder resist may be used to protect areas of the substrate 502 from external damage.

In some embodiments, an epoxy flux (not shown) may be formed on the conductive connector 520 before the conductive connector 520 is reflowed, and the third package component 500 forms the first package component ( 100), at least a portion of the epoxy portion of the epoxy flux remains.

In some embodiments, the underfill 501 (eg, shown applied to the third package component 500 shown on the left but omitted on the third package component 500 shown on the right) is a conductive connector in some embodiments. It is formed between the first package component 100 and the third package component 500 to surround the 520 . The underfill 501 may reduce stress and protect against bonding due to reflow of the conductive connector 520 . The underfill 501 may be formed by a capillary flow process after the third package component 500 is attached, or may be formed by a suitable deposition method before the third package component 500 is attached. In embodiments where an epoxy flux is formed, the epoxy flux may act as the underfill 501 .

31 , in some embodiments, a singulation process is performed by sawing along a scribe line region, eg, between package 800A and package 800B (see FIG. 30 ). Sawing separates the package 800A from the package 800B. The resulting singulated package 800 is from either package 800A or package 800B.

Then, each singulated package 800 is mounted to a printed circuit board 600 using a conductive connector 414 , in accordance with some embodiments. Printed circuit board 600 may include active and passive components as well as other devices. In some embodiments, the printed circuit board 600 may be an interposer or other package component. Printed circuit board 600 may include a voltage source device 601 that is mounted to printed circuit board 600 to provide a high voltage signal to conductive connector 414, the high voltage signal being It is then routed through the substrate 300 to the various components. In some embodiments, conductive connector 414 is reflowed to attach package 800 to corresponding bond pads of printed circuit board 600 to form device 900 . The conductive connector 414 electrically and/or physically couples the printed circuit board 600 to the package 800 , as described above with respect to FIG. 29 .

In FIG. 32 , a flow diagram is provided illustrating operation of a structure in accordance with some embodiments, such as the embodiments described above with respect to package 400 or package 800 . Although the flow of FIG. 32 is discussed below with respect to package 400 , it should be understood that this flow is generally applicable to all conceivable embodiments. At operation 1010 , a high voltage signal (eg, from voltage source device 601 ) is received via a voltage input. The voltage input may be received, for example, at one of the conductive connectors 414 (see FIG. 29 ) or at one of the conductive connectors 246 (see FIG. 24 ). In some embodiments, the high voltage signal may have a nominal value of about 5V or about 12V, a current between about 4A and about 15A, for a total power of between about 20W and about 120W, such as about 40W, but other values are conceivable and can be used. At operation 1020 , the high voltage signal is routed to an embedded IVR, eg, IVR 210 (see FIG. 29 ) by a first redistribution structure, eg, redistribution structure 240 (see FIG. 22 ). . In some embodiments, the total ohmic load through redistribution structure 240 may be between about 0.05 ohms and about 10 ohms, such as about 0.1 ohms, although other values are conceivable.

At operation 1030 , the high voltage signal is converted to a regulated voltage signal by the IVR. The magnitude of the regulated voltage signal is smaller than the magnitude of the high voltage signal. In some embodiments, the regulated voltage signal can be between about 0.1V and about 2.5V, such as about 0.7V, and the current for the regulated voltage signal can be between about 10A and about 200A, such as about 58A have. Other values for the regulated voltage output are conceivable and may be used. In some embodiments, the ratio of regulated voltage output to high voltage signal may be between about 10% and about 20%, although other values are conceivable and may be used. At operation 1040 , the regulated voltage signal is routed by the second redistribution structure to the embedded device die without routing the regulated voltage signal through the first redistribution structure. For example, the regulated voltage signal from the IVR 210 is routed by the front redistribution structure 122 (see FIG. 12 ) to the embedded integrated circuit dies 50A and/or 50B (see FIG. 5 ). In some embodiments, the total ohmic load through the second redistribution structure (such as redistribution structure 122 ) may be between about 0.05Ω and about 10Ω, such as about 0.1Ω, although other values are contemplated. . The total voltage drop for a regulated voltage of 0.7V can be between about 9mV and about 14mV, although other values are conceivable. At operation 1050 , optionally in some embodiments, the regulated voltage signal may be routed to other devices, including routing the regulated voltage signal back to the other devices via the first redistribution structure. can do.

In order that aspects of the present disclosure may be better understood by those skilled in the art, features of several embodiments have been outlined above. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. you should know Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations will occur to those skilled in the art without departing from the spirit and scope of the present disclosure. You have to be aware that you can do it in your invention.

Examples

Example 1. A method comprising:

attaching the voltage regulator to a first redistribution structure of a first package;

forming a second redistribution structure over the voltage regulator, the voltage regulator embedded within the second redistribution structure; and

attaching a first substrate to the second redistribution structure to form a second package including the first package.

Example 2. In Example 1,

forming an encapsulant over and around the first substrate; and

The method further comprising singling the second package, wherein the encapsulant remains on sidewalls of the first substrate after singulation.

Example 3. The method of Example 1,

and attaching the first substrate to a printed circuit board to form a first device.

Embodiment 4. The method of embodiment 1, wherein the voltage regulator is within a lateral extent of the first redistribution structure.

Embodiment 5 The method of embodiment 1, wherein a lateral extent of the second redistribution structure is greater than a lateral extent of the first substrate.

Example 6. The method of Example 1,

routing a first voltage signal to the voltage regulator through the second redistribution structure;

adjusting the first voltage signal to a second voltage signal, the second voltage signal having a smaller voltage magnitude than the first voltage signal; and

and routing the second voltage signal through the first redistribution structure to a device die of the first package without routing the second voltage signal through the second redistribution structure.

Embodiment 7. The method of Embodiment 1 wherein attaching the voltage regulator to the first redistribution structure comprises bonding connectors of the voltage regulator to corresponding contact pads of the first redistribution structure. how to be.

Example 8. A method comprising:

attaching the first device to the carrier substrate;

transversely encapsulating the first device in a first encapsulant;

exposing contact pads of the first device from the first encapsulant;

attaching a second device to the contact pads;

forming a first redistribution structure over the first device and the first encapsulant, the first redistribution structure embedding the second device within one or more layers of the first redistribution structure;

providing a prepared substrate; and

attaching the prepared substrate to the first redistribution structure opposite the second device.

Example 9. The method of Example 8,

removing the carrier substrate; and

The method further comprising singling a first package from a second package, wherein the first package includes the first device and the prepared substrate, wherein the dimensions of the prepared substrate are the same before and after singulation.

Example 10. The method of Example 9,

transversely encapsulating the prepared substrate in a second encapsulant; and

and forming connectors on the prepared substrate, wherein the second encapsulant covers sidewalls of the prepared substrate after singulation.

Embodiment 11 The method of embodiment 8, wherein the second device is within a lateral extent of the first device.

Example 12. A structure comprising:

a first redistribution structure disposed over the substrate;

a voltage regulator disposed over the first redistribution structure, the connectors of the voltage regulator facing the first redistribution structure;

a second redistribution structure disposed over the voltage regulator, the voltage regulator disposed within a lateral extent of the second redistribution structure; and

a device die disposed over the second redistribution structure, the second redistribution structure electrically coupling an output of the voltage regulator to an input of the device die.

Example 13. The method of Example 12,

The structure further comprising a first encapsulant surrounding the substrate.

Embodiment 14. The structure of embodiment 13, wherein a lateral extent of the substrate is less than a lateral extent of the first redistribution structure.

Example 15. The method of Example 12,

and a plurality of connectors interposed between the substrate and the first redistribution structure, wherein the plurality of connectors couple the substrate to the first redistribution structure.

Example 16. The method of Example 12,

The structure further comprising an underfill disposed between the voltage regulator and the second redistribution structure.

Embodiment 17 The structure of embodiment 12, wherein the voltage regulator is embedded within the first redistribution structure.

Embodiment 18 The structure of embodiment 17, wherein the voltage regulator is embedded within two or more layers of the first redistribution structure.

Embodiment 19. The structure of embodiment 12, wherein the metallization pattern of the first redistribution structure is asymmetric.

Example 20. The method of Example 12,

a package disposed over the device die;

a third redistribution structure interposed between the package and the device die;

The structure further comprising one or more vias coupling the third redistribution structure to the second redistribution structure.

Claims (10)

In the method,
attaching the voltage regulator to a first redistribution structure of a first package;
forming a second redistribution structure over the voltage regulator, the voltage regulator embedded within the second redistribution structure; and
attaching a first substrate to the second redistribution structure to form a second package including the first package;
including,
and a lateral extent of the second redistribution structure is greater than a lateral extent of the first substrate. In the method,
attaching a first device to a carrier substrate, wherein the first device is an integrated fan out package, the integrated fan out package comprising: a first embedded die laterally surrounded by a first encapsulant; a fan-out interconnect disposed beyond the first encapsulant;
transversely encapsulating the first device in a second encapsulant, the second encapsulant formed on sidewalls of the fan-out interconnect;
exposing the contact pads of the first device from the second encapsulant;
attaching a second device to the contact pads;
forming a first redistribution structure over the first device and the first encapsulant, the first redistribution structure embedding the second device within one or more layers of the first redistribution structure;
providing a prepared substrate; and
attaching the prepared substrate to the first redistribution structure opposite to the second device;
A method comprising In the structure,
a first redistribution structure disposed over the substrate;
a voltage regulator disposed over the first redistribution structure, the connectors of the voltage regulator facing the first redistribution structure;
a second redistribution structure disposed over the voltage regulator, the voltage regulator disposed within a lateral extent of the second redistribution structure; and
a device die disposed over the second redistribution structure, the second redistribution structure electrically coupling an output of the voltage regulator to an input of the device die;
including,
and a lateral extent of the substrate is less than a lateral extent of the first redistribution structure. 4. The method of claim 3,
a first encapsulant surrounding the substrate
Further comprising, the structure. delete 4. The method of claim 3,
a plurality of connectors interposed between the substrate and the first redistribution structure
further comprising,
wherein the plurality of connectors couple the substrate to the first redistribution structure. 4. The method of claim 3,
Underfill interposed between the voltage regulator and the second redistribution structure
Further comprising, the structure. 4. The method of claim 3,
and the voltage regulator is embedded within the first redistribution structure. 4. The method of claim 3,
The structure of claim 1, wherein the metallization pattern of the first redistribution structure is asymmetric. 4. The method of claim 3,
a package disposed over the device die;
a third redistribution structure interposed between the package and the device die; and
one or more vias coupling the third redistribution structure to the second redistribution structure
Further comprising, the structure.

Images