CN107025930B

CN107025930B - Address detector for enabling/disabling burst mode reads in SRAM

Info

Publication number: CN107025930B
Application number: CN201611025525.6A
Authority: CN
Inventors: 普雷姆库马尔·塞特阿拉曼; 维诺德·梅内塞斯
Original assignee: Texas Instruments Inc
Current assignee: Texas Instruments Inc
Priority date: 2015-11-16
Filing date: 2016-11-15
Publication date: 2022-03-15
Anticipated expiration: 2036-11-15
Also published as: CN107025930A

Abstract

The present invention relates to an address detector for enabling/disabling burst mode reads in an SRAM. An SRAM read controller includes a first flip-flop (402), a second flip-flop (404), and a comparator (420). The first flip-flop (402) is configured to store a first row address input indicative of a first row address of an access request to a first memory cell of an array of memory cells arranged as rows and columns and a second row address input indicative of a second row address of an access request to a second memory cell of the array of memory cells. The second flip-flop (404) is configured to store the first and second row address inputs. The comparator (420) is configured to compare the first and second row address inputs and to output a control signal (222) based on the comparison.

Description

Address detector for enabling/disabling burst mode reads in SRAM

Technical Field

The present invention relates to the field of Static Random Access Memory (SRAM) technology, and in particular, the present invention relates to an SRAM, an SRAM read controller, and a method for reducing power consumption in an SRAM.

Background

Static Random Access Memory (SRAM) is a memory that utilizes latches to store each bit. Because SRAM is static, there is no need to periodically refresh the memory, and as a result, it is typically faster, less dense, and more expensive than Dynamic Random Access Memory (DRAM). Due to the speed of SRAM, SRAM is commonly used in computer applications that require fast memory (e.g., cache memory) for Central Processing Units (CPU), external burst mode SRAM caches, hard disk buffers, router buffers, CPU register files, and the like. Although SRAM is faster, it also consumes most of the system's level dynamic power. In some cases, SRAM may consume up to 90% of system level dynamic power.

Disclosure of Invention

The problems presented above are solved in large part by systems and methods for reducing power consumption in Static Random Access Memory (SRAM). In some embodiments, an SRAM comprises: an array of memory cells arranged in rows and columns and a read controller that manages reading from the memory cells. The memory cell array includes word lines corresponding to the rows and bit lines corresponding to the columns. The read controller includes a precharge circuit and an address detector. The address detector includes a first flip-flop and a comparator. The first flip-flop includes a master latch and a slave latch. The first flip-flop is configured to receive a first row address input indicative of a first row address of an access request to a first memory cell of the array of memory cells and a second row address input indicative of a second row address of an access request to a second memory cell of the array of memory cells. In response to receiving the second row address input, the first master latch is configured to store a first bit of the second row address input and the first slave latch is configured to store a first bit of the first row address input. The comparator is configured to compare the first row address input with the second row address input and to output a control signal based on the comparison. The precharge circuit is configured to receive the control signal and precharge the bit line based on the first row address input being different from the second row address input.

Another illustrative embodiment is a method for reducing power consumption in an SRAM. The method may comprise: a first row address input is received indicating a first row address of an access request to a first memory cell of an array of memory cells arranged as rows and columns. The method may further comprise: a second row address input is received indicating a second row address of an access request to a second memory cell of the array of memory cells. The method may further comprise: in response to receiving the second row address input, storing a first bit of the second row address input in a master latch of a first flip-flop and storing a first bit of the first row address input in a slave latch of the first flip-flop. The method may further comprise: comparing the first row address input with the second row address input. The method may further comprise: precharging a plurality of bit lines of the memory cell array based on the first row address input being different from the second row address input.

Yet another illustrative embodiment is an SRAM read controller comprising a first flip-flop, a second flip-flop, and a comparator. The first flip-flop is configured to store a first row address input indicative of a first row address of an access request to a first memory cell of an array of memory cells arranged as rows and columns and a second row address input indicative of a second row address of an access request to a second memory cell of the array of memory cells. The second flip-flop is configured to store the first and second row address inputs. The comparator is configured to compare the first and second row address inputs and output a control signal based on the comparison.

Drawings

For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

FIG. 1 shows a block diagram of an integrated circuit, according to various embodiments;

FIG. 2 shows a block diagram of a Static Random Access Memory (SRAM) according to various embodiments;

FIG. 3 shows a block diagram of an array of memory cells, according to various embodiments;

FIG. 4 shows a block diagram of an address detector, according to various embodiments;

FIG. 5 shows a circuit diagram of a comparator according to various embodiments;

FIG. 6 shows a flow diagram of a method for reducing power consumption in an SRAM, in accordance with various embodiments; and

FIG. 7 shows a flow diagram of a method for comparing a first row address input and a second row address input.

Symbols and terms

Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include (but not limited to)". Furthermore, the term "coupled" is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections. The recitation "based on" is intended to mean "based, at least in part, on". Thus, if X is based on Y, then X may be based on Y and any number of other factors.

Detailed Description

The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the invention, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.

Static Random Access Memory (SRAM) is a memory that utilizes latches to store each bit. Because SRAM is static, there is no need to periodically refresh the memory, and as a result, it is typically faster, less dense, and more expensive than Dynamic Random Access Memory (DRAM). Due to the speed of SRAM, SRAM is commonly used in computer applications that require fast memory (e.g., cache memory) for Central Processing Units (CPU), external burst mode SRAM caches, hard disk buffers, router buffers, CPU register files, and the like. Thus, SRAM is a basic building block for many systems. Although SRAM is faster, it also consumes most of the system's level dynamic power. In some cases, SRAM may consume up to 90% of system level dynamic power. Therefore, it is necessary to reduce power consumption of the SRAM.

Conventional SRAM designs typically precharge each differential pair of bit lines in a column of the memory storage array at each read access. Thus, the precharging of the bit lines is initiated each time a memory cell in the memory cell array is to be read. Once the bit lines are precharged in a conventional SRAM, the word line corresponding to the row in which the memory cell is to be read is activated. This creates a differential voltage in the column containing the memory cell being read, allowing the sense amplifier to read the contents of the memory cell. If another memory cell is to be read, the process repeats beginning with precharging the bit line. This repeated precharging of the bit lines results in a high level of power consumption.

Instead of precharging at each read, each precharge may be selectively completed. The bit lines may not be precharged when a linear burst read is performed such that the same row address (i.e., the same word line is activated) is used for successive reads. For example, after a first read of a memory cell, if the next memory cell to be read is on the same word line but in a different column of the memory array, precharge may not be performed. However, the bit lines are precharged before and after successive reads. Thus, the address detector may be used to determine whether the row address has changed from one read to the next. If the row address has changed, then precharge is activated for the bit line. If the row address has not changed, then no precharge is performed.

Conventional SRAMs typically include a row address input and a column address input for indicating which memory cell access is requested by the SRAM. The row address input of a conventional SRAM may include a master latch that stores the row address input for a requested memory cell access. Alternatively, multiple master latches may each store one bit of the row address input for a requested memory cell access. In addition, most conventional SRAMs include built-in self-test (BIST) capability. Thus, in addition to master latches, slave latches for each master latch may be included in conventional SRAMs. Each pair of master and slave latches may comprise a flip-flop. To utilize this circuit, the address detector may store the current row address input into the master latches and/or store one bit of the row address request into each of the master latches. The slave latch may then store the row address input of the previous row access request. The comparator may then compare the current row access request stored in the master latch with the previous row access request stored in the slave latch. If the current row access request is the same as the previous row access request, then the next memory cell to be read is on the same word line and does not need to be precharged. However, if the current row access request is different from the previous row address request, the next memory cell to be read is on a different word line, and the read controller can begin precharging the bit lines of the memory array.

Fig. 1 shows a block diagram of an integrated circuit 100, according to various embodiments. The integrated circuit 100 may include a processor 102 and an SRAM 104, and in some embodiments the SRAM 104 may be coupled to the processor 102. Integrated circuit 100 may also include various additional components, such as transceivers, clock generators, ports, and so forth; however, these components have been omitted for clarity. The processor 102 may be a control processor, a signal processor, a central processor, or any other type of processor. The processor 102 may be, for example, a general purpose microprocessor, a digital signal processor, a microcontroller, or other suitable device configured to execute instructions for performing operations. Processor architectures typically include execution units (e.g., fixed point, floating point, integer, etc.), instruction decode, peripherals (e.g., interrupt controllers, timers, direct memory access controllers, etc.), input/output systems (e.g., serial ports, parallel ports, etc.), and various other components and subsystems.

The SRAM 104 is a static random access memory that may provide storage for data and/or instructions capable of being processed by the processor 102. The SRAM 104 is designed such that it exhibits data retention and utilizes latch circuits to store each bit of data. The SRAM 104 is coupled to the processor 102 such that the processor 102 can read data and/or instructions from the SRAM 104 and/or write data and/or instructions to the SRAM 104 for storage. In some embodiments, SRAM 104 is a component of processor 102, while in alternative embodiments, SRAM 104 is different from processor 102. In addition, multiple SRAMs 104 may be included in the integrated circuit 100.

FIG. 2 shows a block diagram of an SRAM 104, according to various embodiments. The SRAM 104 may include a memory cell array 202, a read controller 204, a column decoder 206, and sense amplifiers 208. The array 202 of memory cells may be arranged as rows and columns of memory cells, sometimes referred to as bitcells, each storing one bit of data.

FIG. 3 shows a block diagram of a memory cell array 202, according to various embodiments. The memory cell array 202 may include word lines 302-312 corresponding to rows and columns 322-328 of the memory cell array 202. Each of the columns 322-328 may be comprised of a differential pair of bit lines. For example, column 322 may be comprised of bit lines 332-334; column 324 may be comprised of bit lines 336-338; column 326 may be comprised of bit lines 340-342; and column 328 may be comprised of bit lines 344-346. The storage cells (e.g.,

storage cells

352, 354, and 356, which make up storage cell array 202) are at the intersection of each of word lines 302-312 and columns 322-328.

Each of the storage cells in storage array 202 (e.g.,

storage cells

352, 354, and 356) may be arranged to store a single bit of data. In some embodiments, each of the storage cells comprises a six transistor ("6T") SRAM cell formed from a pair of cross-coupled inverters. Each inverter includes a p-channel transistor and an n-channel transistor. The source of the first pass gate transistor is connected to the gate node of the first inverter and the drain node of the second inverter. Similarly, the source of the second pass gate transistor is connected to the gate node of the second inverter and the drain node of the first inverter. The gates of the pass gate transistors are connected to a common word line, such as word line 302 for

memory cells

352 and 354 and word line 308 for memory cell 356, while the drains of the pass gate transistors are connected to a differential pair of bit lines, such as

bit lines

332 and 334 for

memory cells

352 and 356 and

bit lines

336 and 338 for memory cell 354. In alternative embodiments, the storage cells of the storage array 202 may be any type of SRAM bit cell, such as a four transistor ("4T") SRAM cell, an eight transistor ("8T") SRAM cell, a ten transistor ("10T") SRAM cell, or any other SRAM storage cell.

Returning to FIG. 2, a read controller 204 is coupled to the memory cell array 202 and is configured to manage the reading of memory cells contained in the memory cell array 202. The read controller 204 may include a precharge circuit 210 and an address detector 212. The read controller may be any type of memory controller that manages the flow of data into and from the memory cell array 202 to the memory cell array 202. At the beginning of a read cycle, the precharge circuit 210 is configured to cause each of the differential pairs of bit lines (both positive and negative signals) to be precharged to a common voltage. To read any of the memory cells, the word line corresponding to the memory cell to be read is activated. For example, if memory cell 352 is to be read, word line 302 is activated. In some embodiments, a row controller (not shown) may cause a word line to be activated. Once the word lines are activated, each of the pass gate transistors from each of the memory cells on the activated word line is enabled. For example, if word line 302 is activated, pass gate transistors in

storage cells

352 and 354 are enabled, as well as a pass gate transistor for any other storage cell connected to word line 302. This causes the bit line voltage for one of the two differential pairs of bit lines connected to each of the memory cells to drop based on whether the memory cell connected to that differential pair stores a 0 or a 1. For example, once word line 302 is activated, the voltage along

bit line

332 or 334 will drop based on whether memory cell 352 stores a 0 or a 1. Similarly, the voltage along

bit line

336 or 338 will drop based on whether memory cell 354 contains a 0 or a 1.

Column decoder 206 determines which of columns 322-328 from FIG. 3 contains the memory cell to be read. More specifically, column decoder 206 is configured to receive an output signal from each of columns 322-328 and select an output signal from the column corresponding to the memory cell being read. Each of the output signals corresponds to a differential voltage carried in a differential pair of bit lines. For example, if memory cell 352 is to be read, then column decoder 206 selects column 322 and its differential pair of bit lines 322-334. The sense amplifier 208 can then sense which of the selected differential pair of bit lines has the higher voltage by amplification, thus determining whether the memory cell stores a 0 or a 1. In other words, the sense amplifiers 208 are configured to determine the state of the selected column by sensing the column voltage differential. Continuing with the previous example, once column decoder 206 selects column 322, the sense amplifiers will sense or determine which of

bit lines

322 and 334 has the higher voltage. Once determined, the state of the memory cell 352 can be determined.

The read controller 204 may then identify consecutive reads from memory cells accessed via the same word line. For example, if a read from storage cell 352 is followed immediately by a read from storage cell 354 that is on the same word line as storage cell 352, i.e., word line 302, read controller 204 makes this identification. Unlike conventional SRAM, if the following identification is made: successive reads from memory cells accessed via the same word line are made by read controller 204, then bit lines 332-346 are not precharged between the two reads. Because activation of a particular word line produces a differential for each of the memory cells on the word line that represents the state of the bit in each of the memory cells, precharging is not necessary to read other memory cells on the same word line. Thus, prior to or at the beginning of a continuous read, bit lines 332-346 may only be precharged once in conjunction with the continuous read. By reducing the number of precharges (i.e., by not precharging differential pairs of bit lines after each read), the power consumed by the SRAM 104 is reduced.

At the end of a read cycle (once consecutive reads end), the precharge circuit 210 is configured to again cause each of the differential pairs of bit lines to be precharged to a common voltage. More specifically, the address detector 212 is configured to determine (i.e., detect) any row address change request in the SRAM 104. In other words, the address detector 212 is configured to determine whether a request consists of SRAM 104 and when a request consists of SRAM 104 to read a memory cell in the memory array 202 that is not on the currently read word line. Once the address detector 212 detects a row address change request, a control signal 222 indicating that a row address request has been received is transmitted to the precharge circuit 210. The read controller 204 utilizing the precharge circuit 210 causes each of the differential pair of bit lines 332-346 to be precharged to enable the memory cells on different word lines to be read. For example, if memory cell 352 is read, then word line 302 is activated. However, if address detector 212 detects a row address change request such that memory cell 356 is to be read, then word line 306 needs to be activated. Because word line 306 is a different word line (on a different row) than word line 302, precharge circuit 210 causes a differential pair of bit lines 332-346 to be precharged. Thus, read controller 204 can store an indication of which word line was last asserted (word line 302 in this example). Based on the word line currently asserted or to be asserted (word line 306 in this example) being different from the last asserted word line (word line 302), precharge circuit 210 causes a precharge of bit lines 332-346.

FIG. 4 shows a block diagram of an address detector 212, according to various embodiments. The address detector 212 may include row address flip-flops 402 and 404 (each of which may correspond to a single bit of a row address) and a comparator 420. The ellipsis between flip-

flops

402 and 404 indicates that address detector 212 may support any suitable number of flip-flops corresponding to bits of the row address, although only two flip-flops are shown for clarity. The flip-flops 402-404 may receive a row address input indicating a row address of a memory cell to be accessed within the memory cell array 202. For example, flip-flop 402 may receive one bit of the row address of word line 302 (shown as input 442), and flip-flop 404 may also receive one bit of the row address of word line 302 (shown as input 444), such that memory cell 352 may be accessed and read (i.e., first access). Flip-flop 402 may store one bit of the row address of the word line to be accessed in master latch 406, while flip-flop 404 may store one bit of the row address of the word line to be accessed in master latch 410.

At the end of the first read cycle (i.e., after the designated memory cell has been accessed and read), flip-flops 402-404 may receive a second row address input (i.e., a second access) indicating the row address of the memory cell to be accessed next. For example, flip-flop 402 may receive one bit of a row address of word line 306 (shown as input 442), and flip-flop 404 may also receive one bit of a row address of word line 306 (shown as input 444), such that memory cell 356 may be accessed and read. Flip-flops 402-404 store the row address of the memory cell for the second access request in master latches 406 and 410, respectively. The row address for the previous read (i.e., the first access) is stored in slave latch 408 for flip-flop 402 and slave latch 412 for flip-flop 404. Continuing with the previous example, after receiving the second access request, slave latch 408 stores one bit of the row address of wordline 302 for the second read access, and slave latch 412 also stores one bit of the row address of wordline 302. Thus, flip-flop 402 includes: a master latch 406 storing one bit of the row address of the current read request; and a slave latch 408 that stores one bit of the row address of the previous read request. Similarly, the flip-flop 404 includes: a master latch 410 that stores one bit of the row address of the current read request; and a slave latch 412 that stores one bit of the row address of the previous read request.

Comparator 420, which may be any type of signal comparator, receives the contents of master latches 406 and 410 and the contents of slave latches 408 and 412. For example, after the master latch 406 receives the row address input 442 for a most recent access request (e.g., a second access request), the master latch 406 stores a particular state (e.g., HIGH or LOW) based on the row address input 442. The state is also provided to comparator 420 via signal 432. The previous state of master latch 406 (e.g., the state stored in master latch 406 due to the first access request) is then stored in slave latch 408. The state is also provided to comparator 420 via signal 434. In a similar manner, the master latch 410 receives a row address input 444 for a most recent access request (e.g., a second access request) and stores a particular state based on the row address input 444. The status pass signal 436 is also provided to the comparator 420. The previous state of the master latch 410 (e.g., the state stored in the master latch 410 due to the first access request) is then stored in the slave latch 412 and is also provided to the comparator 420 via signal 438.

After receiving the states of master latches 406 and 410 and slave latches 408 and 412 through signals 432-438, comparator 420 is used to compare the states to determine whether the states remain the same. In other words, the comparator 420 compares the state of the current row address inputs 442-444 with the previous row address inputs. The comparator 420 may then output the control signal 222 received by the precharge circuit 210. If the comparator 420 determines that the current row address inputs 442-444 are the same as the previous row address inputs, the comparator 420 may output the control signal 222 that causes the precharge circuit 210 to not precharge the bit lines 332-346. However, if the comparator 420 determines that the current row address inputs 442-444 are different from the previous row address inputs, the comparator 420 may output the control signal 222 that causes the precharge circuit 210 to precharge the bit lines 332-346.

Fig. 5 shows a circuit diagram of a comparator 420, the comparator 420 may include exclusive-or (XOR) gates 502-504 and a NOR (NOR) gate 506, according to various embodiments. XOR gate 502 may be configured to receive signals 432-434 from flip-flop 402 and perform an XOR operation on those signals. More specifically, XOR gate 502 may receive a signal 432 indicative of the state of master latch 406 and a signal 434 indicative of the state of slave latch 408. If the signals 432-434 are in the same state (i.e., if the signal 432 is HIGH and the signal 434 is HIGH, or if the signal 432 is LOW and the signal 434 is LOW), the XOR gate 502 outputs the XOR output 522 as a LOW signal. However, if the signals 432-434 are in different states (i.e., if the signal 432 is HIGH and the signal 434 is LOW, or if the signal 432 is LOW and the signal 434 is HIGH), the XOR gate 502 outputs the XOR output 522 as a HIGH signal. Similarly, the XOR gate 504 may receive a signal 436 indicative of the state of the master latch 410 and a signal 438 indicative of the state of the slave latch 412. If the signals 436-438 are in the same state (i.e., if the signal 436 is HIGH and the signal 438 is HIGH, or if the signal 436 is LOW and the signal 438 is LOW), the XOR gate 504 outputs the XOR output 524 as a LOW signal. However, if the signals 436-438 are in different states (i.e., if the signal 436 is HIGH and the signal 438 is LOW, or if the signal 436 is LOW and the signal 438 is HIGH), the XOR gate 504 outputs the XOR output 524 as a HIGH signal.

The NOR gate 506 may be configured to receive the XOR outputs 522-524 and perform a NOR operation on those signals. More specifically, if the XOR outputs 522-524 are all LOW, then the NOR gate 506 outputs the HIGH control signal 222. However, in all other cases (i.e., if the XOR outputs 522-524 are all HIGH, if the XOR output 522 is HIGH and the XOR output 524 is LOW, or if the XOR output 522 is LOW and the XOR output 524 is HIGH), the NOR gate 506 outputs the LOW control signal 222. Thus, the control signal 222 is HIGH only when the state of the master latch 406 is equal to the state of the slave latch 408 and the state of the master latch 410 is equal to the state of the slave latch 412. Thus, the HIGH control signal 222 may cause the precharge circuit 210 to not precharge the bit lines 332-346, while the LOW control signal 22 may cause the precharge circuit 210 to precharge the bit lines 332-346.

FIG. 6 shows a flow diagram of a method 600 for reducing power consumption in an SRAM (e.g., SRAM 104), in accordance with various embodiments. FIG. 7 shows a flow diagram of a method 700 for comparing a first row address input and a second row address input, according to various embodiments. Although depicted sequentially for convenience, at least some of the acts shown in

methods

600 and 700 may be performed in a different order and/or performed in parallel. Additionally, some embodiments may perform only some of the acts shown or may perform additional acts. In some embodiments, at least some operations of

methods

600 and 700, as well as other operations described herein, may be performed by SRAM 104 and/or read controller 204 implemented by a processor or state machine executing instructions stored in a non-transitory computer-readable storage medium.

Method 600 begins in block 602 with receiving a first row address input indicating a first row address for an access to a first memory cell, such as memory cell 352 of an array of memory cells arranged as rows and columns, such as memory array 202. For example, address detector 212 may receive a row address input corresponding to an access request to word line 302 in order to access storage cell 352. In block 604, method 600 continues with receiving a second row address input indicating a second row address of an access request to a second memory cell (e.g.,

memory cell

354 or 356 of the memory cell array). For example, address detector 212 may receive a row address input corresponding to an access request to word line 302 to access memory cell 354 or to receive a row address input corresponding to an access request to word line 306 to access memory cell 356.

Method 600 continues in block 606 in response to receiving the second row address input, storing a first bit of the second row address input in a master latch (e.g., master latch 406) of a first flip-flop (e.g., flip-flop 402) and storing a first bit of the first row address input in a slave latch (e.g., slave latch 408) of the first flip-flop. For example, master latch 406 may store one bit of the row address input corresponding to a second access request (e.g., an access request to wordline 302 to access memory cell 354 or an access request to wordline 306 to access memory cell 356), while slave latch 408 may store one bit of the row address input corresponding to a first or previous access request (e.g., an access request to wordline 302 to access memory cell 352) in response to receiving the second row address input. Similarly, in block 608, the method 600 continues in response to receiving the second row address input, storing a second bit of the second row address input in a master latch (e.g., master latch 410) of a second flip-flop (e.g., flip-flop 404) and storing the second bit of the first row address input in a slave latch (e.g., slave latch 412) of the second flip-flop.

The method 600 continues in block 610 with determining whether the first row address input is the same as the second row address input. For example, a first row address input and a second row address input may be compared. In block 610, if it is determined that the first row address input is the same as the second row address input, in block 612, the method 600 continues with reading the first memory cell and the second memory cell without precharging the bit lines of the memory array. For example, if the first row address input is the same as the second row address input, then

memory cells

352 and 354 residing on the same word line 302 are read without precharging bit lines 332-346 between the reads. However, if in block 610 it is determined that the first row address input is not the same or different than the second row address input, the method 600 continues to precharge the bit lines of the memory array in block 614. For example, if the first row address input is the same as the second row address input, then the memory cell 352 residing on word line 302 may be read, followed by precharging the bit lines 332-346. The memory cells 356 residing on word line 306 can then be read. The method may then be repeated in a similar manner for additional access requests.

FIG. 7 shows a flow diagram of a method 700 of comparing a first row address input with a second row address input, according to various embodiments. Method 700 begins in block 702 with performing an XOR operation on bits stored in a master latch (e.g., master latch 406) and a slave latch (e.g., slave latch 408) of a first flip-flop (e.g., flip-flop 402) to generate a first XOR output (e.g., XOR output 522). Continuing from the example of FIG. 6, bits from the row address input for the current access request are stored in master latch 406, while bits from the row address input for the previous access request are stored in slave latch 408. An XOR operation may be performed on those two bits (shown as signals 432-434) by XOR gate 502 to produce XOR output 522.

Similarly, in block 704, the method 700 continues with performing an XOR operation on the bits stored in the master latch (e.g., master latch 410) and the slave latch (e.g., slave latch 412) of the second flip-flop (e.g., flip-flop 404) to generate a second XOR output (e.g., XOR output 524). Continuing with the previous example, bits from the row address input for the current access request are stored in the master latch 410, while bits from the row address input for the previous access request are stored in the slave latch 412. An XOR operation may be performed on those two bits (shown as signals 436-438) by XOR gate 504 to produce XOR output 524.

The method 700 continues in block 706 with performing a NOR operation on the first and second XOR outputs to generate a control signal (e.g., the control signal 222). For example, the NOR gate 506 may perform a NOR operation on the XOR outputs 522-524 to generate the control signal 222. The HIGH control signal 222 may cause the precharge circuit 210 to not precharge the bit lines 332-346, while the LOW control signal 22 may cause the precharge circuit 210 to precharge the bit lines 332-346.

The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims

1. A static random access memory, SRAM, comprising:

an array of memory cells arranged in rows and columns and including word lines corresponding to the rows and bit lines corresponding to the columns; and

a read controller for managing reads from the memory cells, the read controller including a precharge circuit and an address detector, the address detector including:

a first flip-flop comprising a first master latch and a first slave latch, the first flip-flop configured to receive a first row address input indicative of a first row address of an access request to a first memory cell of the array of memory cells and a second row address input indicative of a second row address of an access request to a second memory cell of the array of memory cells, wherein in response to receiving the second row address input, the first master latch is configured to store a first bit of the second row address input and the first slave latch is configured to store a first bit of the first row address input;

a comparator configured to compare the first row address input with the second row address input and to output a control signal based on the comparison;

wherein the precharge circuit is configured to receive the control signal and precharge the bit line based on the first row address input being different from the second row address input; and

wherein the read controller is further configured to read the first memory cell and the second memory cell based on the second row address input being the same as the first row address input without precharging the bit line between the reads of the first and second memory cells.

2. The SRAM of claim 1, wherein the address detector further comprises a second flip-flop comprising a second master latch and a second slave latch, the second flip-flop configured to receive the first row address input and the second row address input, and in response to receiving the second row address input, the second master latch is configured to store a second bit of the second row address input, and the second slave latch is configured to store a second bit of the first row address input.

3. The SRAM of claim 2, wherein the comparator is further configured to:

comparing the first bit stored in the first master latch with the first bit stored in the second slave latch; and

comparing the second bit stored in the second master latch with the second bit stored in the second slave latch.

4. The SRAM of claim 3, wherein:

the comparison of the first bit comprises performing an exclusive-OR (XOR) operation on the first bit stored in the first master latch and the first bit stored in the first slave latch to generate a first XOR output; and is

The comparison of the second bit comprises performing an XOR operation on the second bit stored in the second master latch and the second bit stored in the second slave latch to generate a second XOR output.

5. The SRAM of claim 4, wherein the comparator is further configured to perform a NOR operation on the first XOR output and the second XOR output to generate the control signal.

6. The SRAM of claim 1, wherein:

the first flip-flop is further configured to receive a third row address input indicative of a third row address of an access request to a third memory cell of the array of memory cells;

in response to receiving the third row address input, the first master latch is configured to store a first bit of the third row address input and the first slave latch is configured to store the first bit of the second row address input.

7. The SRAM of claim 6, wherein the comparator is further configured to:

comparing the first bit stored in the first master latch with the first bit stored in the first slave latch; and

8. A method for reducing power consumption in a Static Random Access Memory (SRAM), comprising:

receiving a first row address input indicative of a first row address of an access request to a first memory cell of an array of memory cells arranged as rows and columns;

receiving a second row address input indicating a second row address of an access request to a second memory cell of the array of memory cells;

in response to receiving the second row address input, storing a first bit of the second row address input in a master latch of a first flip-flop and storing a first bit of the first row address input in a slave latch of the first flip-flop;

comparing the first row address input with the second row address input; and

precharging a plurality of bit lines of the memory cell array based on the first row address input being different from the second row address input; and

based on the first row address input being the same as the second row address input, the first memory cell and the second memory cell are read without precharging the bit line between reads of the first and second memory cells.

9. The method of claim 8, wherein the comparing the first row address input and the second row address input comprises: comparing the first bit stored in the master latch of the first flip-flop to the first bit stored in the slave latch of the first flip-flop.

10. The method of claim 8, further comprising:

in response to receiving the second row address input, storing a second bit of the second row address input in a master latch of a second flip-flop and storing a second bit of the first row address input in a slave latch of the second flip-flop.

11. The method of claim 10, wherein the comparing the first row address input and the second row address input comprises:

performing an exclusive-OR (XOR) operation on the first bit stored in the master latch of the first flip-flop and the first bit stored in the slave latch of the first flip-flop to generate a first XOR output;

performing an XOR operation on the second bit stored in the master latch of the second flip-flop and the second bit stored in the slave latch of the second flip-flop to generate a second XOR output; and

performing a NOR operation on the first XOR output and the second XOR output.

12. The method of claim 8, further comprising:

receiving a third row address input indicating a third row address of an access request to a third memory cell of the array of memory cells;

in response to receiving the third row address input, storing a first bit of the third row address input in the master latch of the first flip-flop and storing a first bit of the second row address input in the slave latch of the first flip-flop;

comparing the second row address input with the third row address input; and

precharging a plurality of bit lines of the memory cell array based on the second row address input being different from the third row address input.

13. A Static Random Access Memory (SRAM) read controller, comprising:

a first flip-flop configured to store a first row address input indicative of a first row address of an access request to a first memory cell of an array of memory cells arranged as rows and columns and a second row address input indicative of a second row address of an access request to a second memory cell of the array of memory cells;

a second flip-flop configured to store the first and second row address inputs; and

a comparator configured to compare the first and second row address inputs and to output a control signal based on the comparison; and

wherein based on the first row address input being the same as the second row address input, the read controller is configured to read the first memory cell and the second memory cell without precharging bit lines corresponding to the columns of the memory cell array between the reads of the first and second memory cells.

14. The SRAM read controller of claim 13, wherein:

the first flip-flop comprises a first master latch and a first slave latch, and in response to receiving the second row address input, the first master latch is configured to store a first bit of the second row address input, and the first slave latch is configured to store a first bit of the first row address input; and is

The second flip-flop includes a second master latch and a second slave latch, and in response to receiving the second row address input, the second master latch is configured to store a second bit of the second row address input, and the second slave latch is configured to store a second bit of the first row address input.

15. The SRAM read controller of claim 14, wherein the comparator comprises:

a first exclusive-OR (XOR) gate configured to perform an XOR operation on the first bit stored in the first master latch and the first bit stored in the first slave latch to generate a first XOR output;

a second XOR gate configured to perform an XOR operation on the second bit stored in the second master latch and the second bit stored in the second slave latch to generate a second XOR output; and

a NOR gate configured to perform a NOR operation on the first XOR output and the second XOR output to generate the control signal.

16. The SRAM read controller of claim 14, wherein the control signal is high based on the first bit in the first master latch being equal to the first bit in the first slave latch and the second bit in the second master latch being equal to the second bit in the second slave latch.

17. The SRAM read controller of claim 13, further comprising: a precharge circuit configured to receive the control signal and precharge bit lines corresponding to the columns of the memory cell array based on the first row address input being different from the second row address input.