CN107025930A - The address detection device read for the burst mode being switched on/off in SRAM - Google Patents
The address detection device read for the burst mode being switched on/off in SRAM Download PDFInfo
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- CN107025930A CN107025930A CN201611025525.6A CN201611025525A CN107025930A CN 107025930 A CN107025930 A CN 107025930A CN 201611025525 A CN201611025525 A CN 201611025525A CN 107025930 A CN107025930 A CN 107025930A
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- row address
- memory cell
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- address input
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/418—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Abstract
The present invention relates to the address detection device that a kind of burst mode for being used to be switched on/off in SRAM is read.Static RAM SRAM Read Controllers include the first trigger (402), the second trigger (404) and comparator (420).The first row address that first trigger (402) is configured to store the first row address of the access request for the first memory cell for indicating the memory cell array to being arranged as rows and columns inputs and indicated that the second row address of the second row address of the access request to the second memory cell of the memory cell array is inputted.Second trigger (404) is configured to storage first and second row address input.The comparator (420) is configured to first and second row address described in comparison and inputs and be based on described comparing output control signal (222).
Description
Technical field
The present invention relates to static RAM (SRAM) technical field, and in particular, the present invention relates to one
Plant SRAM, SRAM Read Controller and the method for reducing the power consumption in SRAM.
Background technology
Static RAM (SRAM) is to utilize to latch to store the memory of each.Because SRAM is static
, so without periodically refreshing memory, and therefore, its generally than dynamic random access memory (DRAM) faster, it is close
Degree is low and more expensive.SRAM speed is attributed to, SRAM is generally used for needing to be used for CPU (CPU), outside burst
The fast storage of Mode S RAM cache, hard disk buffering area, router buffering area, cpu register file etc. is (for example at a high speed
Buffer memory) computer application in.Although SRAM is very fast, it also consumes the level dynamic power of most of system.
In certain situation, SRAM can consume up to 90% system level dynamic power.
The content of the invention
The problem of being proposed above for reducing the electric power in static RAM (SRAM) largely by disappearing
The system and method for consumption is solved.In certain embodiments, a kind of SRAM is included：It is arranged to the memory cell array of rows and columns
And management is from the Read Controller of the reading of the memory cell.The memory cell array includes the wordline corresponding to the row
And corresponding to the bit line of the row.The Read Controller includes pre-charge circuit and address detection device.The address detection device
Include the first trigger and comparator.First trigger is comprising main latch and from latch.The first trigger warp
Configure to receive the first row for the first row address for indicating the access request to the first memory cell of the memory cell array
Address inputs and indicated the second row of the second row address of the access request to the second memory cell of the memory cell array
Address is inputted.In response to receiving the second row address input, first main latch is configured to storage second row
First of address input, and described first be configured to first of storage first row address input from latch.Institute
State comparator and be configured to described in comparison the input of the first row address and inputted with second row address and be based on described being compared output
Control signal.The pre-charge circuit is configured to receive the control signal, and inputs difference based on first row address
The bit line is pre-charged in second row address input.
Another illustrative embodiment is a kind of method for being used to reduce the power consumption in SRAM.Methods described may include：
Receive the of the first row address for indicating the access request to the first memory cell of the memory cell array that is arranged as rows and columns
A line address is inputted.Methods described may also include：Receive and indicate the access to the second memory cell of the memory cell array
The second row address input of second row address of request.Methods described may also include：It is defeated in response to receiving second row address
Enter, first that second row address is inputted is stored in the main latch of the first trigger and by first row address
Input first be stored in first trigger from latch.Methods described may also include：Compare the first row
Address is inputted to be inputted with second row address.Methods described may also include：Institute is different from based on first row address input
The input of the second row address is stated, multiple bit lines of the memory cell array are pre-charged.
Another illustrative embodiment is a kind of SRAM Read Controllers, and it includes the first trigger, the second trigger and ratio
Compared with device.First trigger is configured to storage and indicated to the first memory cell of the memory cell array for being arranged as rows and columns
Access request the first row address the input of the first row address and indicate to the second memory cell of the memory cell array
Access request the second row address the second row address input.Second trigger is configured to storage described first and the
Two row addresses are inputted.The comparator is configured to first and second row address described in comparison and inputs and be based on described comparing output
Control signal.
Brief description of the drawings
For various examples are described in detail, let us now refer to the figures, wherein：
Fig. 1 shows the block diagram of the integrated circuit according to various embodiments；
Fig. 2 shows the block diagram of the static RAM (SRAM) according to various embodiments；
Fig. 3 shows the block diagram of the memory cell array according to various embodiments；
Fig. 4 shows the block diagram of the address detection device according to various embodiments；
Fig. 5 shows the circuit diagram of the comparator according to various embodiments；
Fig. 6 shows the flow chart for being used to reduce the method for the power consumption in SRAM according to various embodiments；And
Fig. 7 shows the flow chart for comparing the method that the input of the first row address is inputted with the second row address.
Symbol and term
Through following description and claims using some terms to refer to particular system components.Such as the skill of art
Art personnel will be appreciated that company may use different names to refer to component.This document is not intended in name difference but not acted as
It is distinguish between component.In discussion below and claims, term "comprising" and " bag are used in open mode
Include ", and therefore it should be construed as to imply that " including (but not limited to) ".In addition, term " coupling " mean indirectly or
It is directly connected to.Therefore, if first device is coupled to second device, then the connection can be by being directly connected to, or to pass through
Via being indirectly connected with for other devices and connection.Narration " being based on " means " being at least partially based on ".Therefore, if X is
Based on Y, then X can be based on Y and any number other factors.
Embodiment
Discussion below is related to various embodiments of the present invention.Although one or more of these embodiments can be preferred,
But disclosed embodiment should not be construed or be otherwise used as the model of the invention that limitation includes claims
Enclose.In addition, those skilled in the art will appreciate that, description below has wide application, and the discussion of any embodiment is only anticipated
Taste be the embodiment demonstration, and be not intended to imply and be limited to the implementation comprising the scope of the present invention of claims
Example.
Static RAM (SRAM) is to utilize to latch to store the memory of each.Because SRAM is static
, so without periodically refreshing memory, and therefore, its generally than dynamic random access memory (DRAM) faster, it is close
Degree is low and than more expensive.SRAM speed is attributed to, SRAM is generally used for needing to dash forward for CPU (CPU), outside
The fast storage for sending out Mode S RAM cache, hard disk buffering area, router buffering area, cpu register file etc. is (such as high
Fast buffer memory) computer application in.Therefore, SRAM is the basic building block of many systems.Although SRAM is very fast, its
The level dynamic power of the most of system of consumption.In some cases, SRAM can consume the up to 90% dynamic work(of system level
Rate.Accordingly, it would be desirable to reduce SRAM power consumption.
Each difference of bit line in row of the conventional SRAM design generally in each reading access to memory array
Divide to precharge.Therefore, whenever by the memory cell in memory cell array is read, the precharge to bit line is started.Once
Bit line is precharged in conventional SRAM, wordline of the activation corresponding to the row of memory cell wherein to be read.This is containing being read
Differential voltage is produced in the row of the memory cell taken, so as to allow the content of sense amplifier reading memory cell.If will read
Take another memory cell, then process repeats to start from being pre-charged bit line.This repetition precharge to bit line produces high electric power
Consumption level.
Instead of being pre-charged in each reading, each precharge is optionally completed.Make when performing linear burst reading
Obtaining identical row address (that is, activating same word line) is used to not being pre-charged bit line when continuously reading.For example, in storage
After the first of unit is read, if next memory cell to be read is in same word line, but in storage array not
When in same column, precharge may not be performed.However, being pre-charged before continuous read and afterwards to bit line.Therefore, address detected
Device can be used for determining whether row address reads change from one and read to next.If row address has changed, then to bit line
Start precharge.If row address not yet changes, then do not perform precharge.
Conventional SRAM generally comprises row address input and column address input, and it is used to indicate which memory cell SRAM asks
Access.Conventional SRAM row address input can include main latch, and it stores the row ground of the memory cell access for being asked
Location is inputted.Alternatively, multiple main latch can each store the one of the row address input of the memory cell access for being asked
Individual position.In addition, majority routine SRAM includes the ability of built-in self-test (BIST).Therefore, in addition to main latch, in conventional SRAM
It can include for each main latch from latch.Every a pair of main latch and it may include trigger from latch.To utilize
This circuit, address detection device can input current row address the position that storage is asked into main latch and/or by row address
Store in each of main latch.The row address input of previous row access request can be then stored from latch.Compare
Device then may compare the current line access request stored in main latch and be stored in and asked from the previous line access in latch
Ask.If current line access request is identical with previous row access request, then next memory cell to be read is in same word
On line and without precharge.If however, current line access request is different from previous row Address requests, then to be read is next
Memory cell is in different wordline, and Read Controller can start the bit line precharge to storage array.
Fig. 1 shows the block diagram of the integrated circuit 100 according to various embodiments.Integrated circuit 100 can comprising processor 102 and
SRAM 104, in certain embodiments, SRAM 104 can be coupled to processor 102.Integrated circuit 100 can also be comprising various extra
Component, such as transceiver, clock generator, port etc.；However, for clarity, having been omitted from these components.Processor 102
Can be control processor, signal processor, central processing unit or any other types of processor.Processor 102 can be (example
As) general purpose microprocessor, digital signal processor, microcontroller or be configured to perform be used for perform operation instruction its
Its appropriate device.Processor architecture generally comprises execution unit (for example, fixed point, floating-point, integer etc.), instruction decoding, periphery
Equipment (for example, interrupt control unit, timer, DMA controller etc.), input/output are (for example, serial end
Mouth, parallel port etc.) and various other components and subsystem.
SRAM 104 is static RAM, its can provide data to that can be handled by processor 102 and/or
The storage of instruction.SRAM 104 is designed so that it shows data remanence and using latch cicuit to store each data bit.
SRAM 104 is coupled to processor 102 so that processor 102 can read data and/or instruction and/or by data from SRAM 104
And/or instruction is written to SRAM 104 for storage.In certain embodiments, SRAM 104 is the part of processor 102, and
In alternative embodiments, SRAM 104 is different from processor 102.In addition, multiple SRAM 104 can be included in integrated circuit 100.
Fig. 2 shows the block diagram of the SRAM 104 according to various embodiments.SRAM 104 can comprising memory cell array 202,
Read Controller 204, column decoder 206 and sense amplifier 208.Memory cell array 202 can be arranged to memory cell
Rows and columns, sometimes referred to as bit location, each memory cell store a data bit.
Fig. 3 shows the block diagram of the memory cell array 202 according to various embodiments.Memory cell array 202 can include word
Line 302 to 312, it corresponds to the rows and columns 322 to 328 of memory cell array 202.Each of row 322 to 328 can be by position
The differential pair composition of line.For example, row 322 can be made up of bit line 332 to 334；Row 324 can be made up of bit line 336 to 338；
Row 326 can be made up of bit line 340 to 342；And row 328 can be made up of bit line 344 to 346.Memory cell is (for example, memory cell
352nd, 354 and 356, it constitutes memory cell array 202) intersecting in each of wordline 302 to 312 and row 322 to 328
Place.
Each of memory cell in storage array 202 (for example, memory cell 352,354 and 356) can be arranged
To store individual data position.In certain embodiments, each of memory cell is included by a pair of cross coupled inverters shape
Into six transistors (" 6T ") sram cell.Each phase inverter includes p-channel transistor and n-channel transistor.First transmission grid
The source electrode of gated transistors is connected to the gate node of the first phase inverter and the drain node of the second phase inverter.Similarly, second pass
The source electrode for passing gridistor is connected to the gate node of the second phase inverter and the drain node of the first phase inverter.Transmit grid brilliant
The grid of body pipe is connected to common word line, such as the wordline 302 of memory cell 352 and 354 and for memory cell 356
Wordline 308, and the drain electrode for transmitting gridistor is connected to the differential pair of bit line, such as position for memory cell 352 and 356
Line 332 and 334 and the bit line 336 and 338 for memory cell 354.In alternative embodiments, the storage list of storage array 202
Member can be any type of SRAM bit cell, for example, four transistors (" 4T ") sram cell, eight transistors (" 8T ") SRAM are mono-
Member, ten transistors (" 10T ") sram cell or any other SRAM memory cells.
Fig. 2 is returned to, Read Controller 204 is coupled to memory cell array 202 and is configured to manage memory cell array
The reading of contained memory cell in 202.Read Controller 204 may include pre-charge circuit 210 and address detection device 212.Read
It can be any type of Memory Controller to take controller, and it is managed enters and enter storage list from memory cell array 202
The data flow of element array 202.When reading circulation beginning, pre-charge circuit 210 is configured to cause in the differential pair of bit line
Each (both positive signal and negative signal) is pre-charged to common voltage.In order to read any one of memory cell, activation pair
Should be in the wordline of the memory cell to be read.For example, if memory cell 352 will be read, then activation wordline
302.In certain embodiments, line control unit (not showing) can cause wordline to be activated.Once wordline is activated, enable to hang oneself
Each of transmission gridistor of each of memory cell in activation wordline.For example, if wordline 302
It is activated, then enable the transmission gridistor in memory cell 352 and 354 and any for being connected to wordline 302
The transmission gridistor of other memory cell.Two differences of the bit line for being connected to each of memory cell are used in greetings
Point to one of bit-line voltage based on be connected to the differential pair the memory cell store 0 or 1 and decline.Citing
For, once wordline 302 is activated, along the voltage of bit line 332 or 334 0 or 1 will be stored based on memory cell 352 and under
Drop.Similarly, it will be declined along the voltage of bit line 336 or 338 based on memory cell 354 containing 0 or 1.
Column decoder 206 determines which one in the row 322 to 328 from Fig. 3 contains memory cell to be read.More
For body, column decoder 206 is configured to receive output signal and from corresponding to being read from each of row 322 to 328
Memory cell row in select output signal.Each of output signal corresponds to the difference carried in the differential pair of bit line
Voltage.For example, if memory cell 352 will be read, then the alternative column 322 of column decoder 206 and its bit line 322 to 334
Differential pair.Sense amplifier 208 then can be in the selected differential pair of sense bit line any one have by amplification it is higher
Voltage, it is thus determined that memory cell storage 0 or 1.In other words, sense amplifier 208 is configured to sense column voltage
Difference determines the state of selected row.Continue prior example, once the alternative column 322 of column decoder 206, sense amplifier will be felt
Survey or determine which one in bit line 322 and 334 has high voltage.Once being determined, it is possible to determine memory cell 352
State.
Read Controller 204 then can recognize that the continuous reading from the memory cell accessed via same word line.Citing
For, if the reading from memory cell 352 followed by from the identical wordline of memory cell 352, i.e. word
The reading of memory cell 354 on line 302, then Read Controller 204 makes this identification.Different from conventional SRAM, if done
Go out identified below：Continuous reading from the memory cell accessed via same word line is carried out by Read Controller 204, then
The two are not pre-charged between reading to bit line 332 to 346.Because the activation of particular word line is in the memory cell in wordline
Each produce represent memory cell each in position state difference, so to read same word line on it is other
For memory cell, precharge is unnecessary.Therefore, before continuously reading or when continuous reading starts, once with connecting
Resume studies to take and combine and only bit line 332 to 346 can be pre-charged.By reducing the number of precharge (that is, by after each reading
The differential pair of bit line is not pre-charged), reduce the electric power consumed by SRAM 104.
At the end of circulation is read (once continuous read is terminated), pre-charge circuit 210 is configured to cause bit line again
Each of differential pair be pre-charged to common voltage.More particularly, address detection device 212, which is configured to determine, (that is, examines
Survey) any row address change request in SRAM 104.In other words, whether address detection device 212 is configured to determine request
Constituted and asked by SRAM 104 when to be made up of SRAM 104 to read the wordline for being not in currently reading in storage array 202
On memory cell.Once address detection device 212, which detects row address, changes request, then instruction has been received by row address request
Control signal 222 be sent to pre-charge circuit 210.Bit line is caused using the Read Controller 204 of pre-charge circuit 210
Each of 332 to 346 differential pair is pre-charged to allow to read the memory cell in different wordline.For example, such as
Fruit memory cell 352 is read, then wordline 302 is activated.If however, address detection device 212 detects row address change
Request so that memory cell 356 will be read, then need to activate wordline 306.Because wordline 306 is to be different from wordline 302
Wordline (on not going together), so pre-charge circuit 210 causes the differential pair of bit line 332 to 346 to be pre-charged.Therefore, read
Controller 204 can store the instruction which wordline is finally asserted (being wordline 302 in this example).Based on what is be currently asserted
Or the wordline (wordline 302) for being different from finally asserting by the wordline asserted (being wordline 306 in this example), pre-charge circuit
210 cause the precharge of bit line 332 to 346.
Fig. 4 shows the block diagram of the address detection device 212 according to various embodiments.Address detection device 212 may include row address
Trigger 402 and 404 (each of which person may correspond to the single position of row address) and comparator 420.Trigger 402 and 404
Between ellipsis indicate address detection device 212 can support corresponding to row address position any proper number trigger, so
And two triggers are only shown for clarity.Trigger 402 to 404 can receive instruction will be in the internal memory of memory cell array 202
The row address input of the row address of the memory cell taken.For example, trigger 402 can receive the one of the row address of wordline 302
Individual position (being shown as input 442), and trigger 404 can also receive the row address of wordline 302 a position (be shown as input
444) so that memory cell 352 can be accessed and read (that is, the first access).Trigger 402 can be by the row of wordline to be accessed
One position of address is stored in main latch 406, and trigger 404 can deposit a position of the row address of wordline to be accessed
It is stored in main latch 410.
At the end of reading circulation first (that is, after designated memory cell has been accessed and is read), trigger 402 is arrived
404 can receive instruction then by the second row address input (that is, the second access) of the row address of the memory cell of access.Citing comes
Say, trigger 402 can receive a position (being shown as input 442) of the row address of wordline 306, and trigger 404 can also be received
One position (being shown as input 444) of the row address of wordline 306 so that memory cell 356 can be accessed and read.Trigger
402 to 404 are stored respectively in the row address to the memory cell of the second access request in main latch 406 and 410.For preceding
One row address for reading (that is, the first access) is stored in for trigger 402 from latch 408 and for trigger 404
From latch 412.Continue prior example, after the second access request is received, access is read from latch 408 for second
A position of the row address of wordline 302 is stored, and also stores from latch 412 position of the row address of wordline 302.Therefore,
Trigger 402 includes：Main latch 406, it stores a position of the row address of current read requests；And from latch 408, its
Store a position of the row address of previous read requests.Similarly, trigger 404 includes：Main latch 410, it stores current
One position of the row address of read requests；And from latch 412, it stores a position of the row address of previous read requests.
The content of main latch 406 and 410 can be received for the comparator 420 of any type of signal comparator and from lock
The content of storage 408 and 412.For example, received in main latch 406 for nearest access request (for example, the second access please
Ask) row address input 442 after, main latch 406 be based on row address input 442 store particular states (for example, HIGH or
LOW).The state is also provided to comparator 420 by signal 432.The previous state of main latch 406 is (for example, be attributed to
First access request and the state being stored in main latch 406) it is then stored in from latch 408.The state
Comparator 420 is also provided to by signal 434.In a similar manner, main latch 410 is received for nearest access request (example
Such as, the second access request) row address input 444 and based on row address input 444 store particular states.State passes through signal
436 are also provided to comparator 420.The previous state of main latch 410 is (for example, being attributed to the first access request and being stored in
State in main latch 410) it is then stored in from latch 412 and comparator 420 is also provided to by signal 438.
Main latch 406 and 410 is being received and after the state of latch 408 and 412 by signal 432 to 438,
Comparator 420 is used to compare the state to determine whether the state keeps identical.In other words, comparator 420, which compares, works as
The state that preceding row address input 442 to 444 is inputted with previous row address.Comparator 420 is then exportable by pre-charge circuit 210
The control signal 222 received.If comparator 420 determines that current row address input 442 to 444 inputs phase with previous row address
Together, then the exportable control signal 222 for causing pre-charge circuit 210 not to be pre-charged to bit line 332 to 346 of comparator 420.So
And, if comparator 420 determines current row address, input 442 to 444 is different from the input of previous row address, then comparator 420
The exportable control signal 222 for causing pre-charge circuit 210 to be pre-charged bit line 332 to 346.
Fig. 5 shows the circuit diagram of the comparator 420 according to various embodiments, and comparator 420 may include XOR (XOR) door
502 to 504 and or non-(NOR) door 506.XOR gate 502 can be configured receives signal 432 to 434 and to that with slave flipflop 402
A little signals perform xor operation.More particularly, XOR gate 502 can receive the signal 432 for the state for indicating main latch 406 and refer to
Show the signal 434 from the state of latch 408.If signal 432 to 434 is in equal state (if i.e., signal 432 is
HIGH and signal 434 are HIGH, or if signal 432 is LOW and signal 434 is LOW), then the output XOR outputs of XOR gate 502
522 are used as LOW signals.If however, signal 432 to 434 is in different conditions (if i.e., signal 432 is HIGH and signal
434 be LOW, or if signal 432 is LOW and signal 434 is HIGH), then the output of XOR gate 502 XOR exports 522 conducts
HIGH signals.Similarly, XOR gate 504 can receive the signal 436 for the state for indicating main latch 410 and indicate from latch 412
State signal 438.If signal 436 to 438 is in equal state (if i.e., signal 436 is HIGH and signal 438
For HIGH, or if signal 436 is LOW and signal 438 is LOW), then the output XOR of XOR gate 504 outputs 524 are believed as LOW
Number.If however, signal 436 to 438 be in different conditions in (if i.e., signal 436 is HIGH and signal 438 is LOW, or
If signal 436 is LOW and signal 438 is HIGH), then the output XOR of XOR gate 504 outputs 524 are used as HIGH signals.
NOR-gate 506 can be configured to receive XOR outputs 522 to 524 and those signals performed with NOR operations.It is more specific next
Say, if XOR outputs 522 to 524 are all LOW, then the output HIGH of NOR-gate 506 control signals 222.However, all other
In situation (if i.e., XOR outputs 522 to 524 are all HIGH, if XOR outputs 522 are HIGH and XOR outputs 524 are LOW,
Or if XOR outputs 522 are LOW and XOR outputs 524 are HIGH), then the output LOW of NOR-gate 506 control signals 222.Therefore,
Control signal 222 is only equal to from the state of latch 408 and the state of main latch 410 in the state of main latch 406 and is equal to
From the state of latch 412 when be HIGH.Therefore, HIGH control signals 222 can cause pre-charge circuit 210 not to bit line 332
To 346 precharge, and LOW control signals 22 can cause pre-charge circuit 210 to be pre-charged bit line 332 to 346.
Fig. 6 shows the method for being used to reduce the power consumption in SRAM (for example, SRAM 104) according to various embodiments
600 flow chart.Fig. 7 shows the side for being used to compare the input of the first row address and the input of the second row address according to various embodiments
The flow chart of method 700.Although sequentially describing for convenience, at least part action shown in method 600 and 700 can not
Perform and/or be executed in parallel with order.In addition, some embodiments can only perform some actions or executable extra shown
Action.In certain embodiments, at least some operations of method 600 and 700 and other operations described herein can be by
SRAM 104 and/or the processor or state machine that are stored in the instruction in non-transitory computer-readable storage medium by execution are real
The Read Controller 204 applied is performed.
Method 600 originates in reception and indicated to the first memory cell (for example, being arranged as the storage of rows and columns in block 602
The memory cell 352 of cell array (for example, storage array 202)) access the first row address the first row address input.Lift
For example, address detection device 212 can receive the row address input corresponding to the access request to wordline 302 so as to memory cell
352 enter line access.In block 604, method 600 continues to indicate to the second memory cell (for example, memory cell array is deposited
Storage unit 354 or 356) access request the second row address the second row address input.For example, address detection device 212
The row address that can be received corresponding to the access request to wordline 302 inputs to enter memory cell 354 line access or receive correspondence
Inputted in the row address of the access request to wordline 306 to enter line access to memory cell 356.
Method 600 continues in frame 606 in response to receiving second row address input, that the second row address is inputted
One is stored in the main latch of the first trigger (for example, trigger 402) (for example, main latch 406), and by the first row
First of address input be stored in the first trigger from latch (for example, from latch 408).For example, main lock
Storage 406 can be stored corresponding to the second access request (for example, to the access request of wordline 302 to be deposited to memory cell 354
Take or line access entered to memory cell 356 to the access request of wordline 306) row address input a position, and from latch
Device 408 may be in response to receive the input storage of the second row address corresponding to the first or previous access request (for example, to wordline 302
Access request to memory cell 352 to enter line access) row address input a position.Similarly, in block 608, method 600
Proceed to respond in receiving the input of the second row address, the second that the second row address is inputted is stored in the second trigger (for example, touching
Send out device 404) main latch (for example, main latch 410) in, and the second that the first row address is inputted is stored in second and touches
Send out device from latch (for example, from latch 412).
Method 600 continues to determine whether the input of the first row address is identical with the second row address input in block 610.Citing comes
Say, may compare the input of the first row address and inputted with the second row address.In block 610, if it is determined that the first row address is inputted and the
The input of two row addresses is identical, then in frame 612, and method 600 continues to read the first memory cell and the second memory cell and nothing
The bit line of storage array need to be pre-charged.For example, if the input of the first row address is identical with the second row address input, then
The memory cell 352 and 354 resided in same word line 302 be read without between the reading to bit line 332 to 346
Precharge.However, in block 610, if it is determined that the first row address is inputted to be differed or different from the input of the second row address, then
Method 600 continues the bit line precharge to storage array in frame 614.For example, if the first row address input and second
Row address input is identical, then the memory cell 352 resided in wordline 302 can be read, then pre- to bit line 332 to 346
Charging.Then the memory cell 356 resided in wordline 306 can be read.Method then can in a similar manner repeat for
Extra access request.
Fig. 7 displayings are inputted and the method 700 of the second row address input according to the row address of comparison first of various embodiments
Flow chart.Method 700 originates in the main latch (example to being stored in the first trigger (for example, trigger 402) in block 702
Such as, main latch 406) and from the position in latch (for example, from latch 408) xor operation is performed, it is defeated to produce the first XOR
Go out (for example, XOR outputs 522).Continue from Fig. 6 example, the position from the row address input for current access request is deposited
It is stored in main latch 406, and the position from the row address input for previous access request is stored in from latch 408
In.Xor operation can be performed to that two positions (being shown as signal 432 to 434) to produce XOR outputs 522 by XOR gate 502.
Similarly, in block 704, method 700 continues the main lock to being stored in the second trigger (for example, trigger 404)
Storage (for example, main latch 410) and perform xor operation to produce second from the position in latch (for example, from latch 412)
XOR outputs (for example, XOR outputs 524).Continue prior example, the position quilt from the row address input for current access request
It is stored in main latch 410, and the position from the row address input for previous access request is stored in from latch 412
In.Xor operation can be performed to that two positions (being shown as signal 436 to 438) to produce XOR outputs 524 by XOR gate 504.
Method 700 continues that first and second XOR outputs are performed NOR operations to produce control signal (example in frame 706
Such as, control signal 222).For example, NOR-gate 506 can perform NOR operations to produce control signal to XOR outputs 522 to 524
222.HIGH control signals 222 can cause pre-charge circuit 210 not to be pre-charged to bit line 332 to 346, and LOW control signals 22
Pre-charge circuit 210 can be caused to be pre-charged bit line 332 to 346.
Discussed above is to illustrate the principle and various embodiments of the present invention.Those skilled in the art is complete
Numerous changes and modification are just readily apparent that after solution the disclosure above content.Wish to explain that claims below is all such to cover
Change and change.
Claims (20)
1. a kind of static RAM SRAM, it includes：
Memory cell array, it is arranged to rows and columns, and including the wordline corresponding to the row and the position corresponding to the row
Line；And
Read Controller, it is used to manage from the reading of the memory cell, the Read Controller include pre-charge circuit and
Address detection device, the address detection device is included：
First trigger, it includes the first main latch and first from latch, and first trigger is configured to reception and referred to
Show the first row address input of the first row address of the access request to the first memory cell of the memory cell array and refer to
Show that the second row address of the second row address of the access request to the second memory cell of the memory cell array is inputted, wherein
In response to receiving the second row address input, first main latch is configured to storage the second row address input
First, and described first be configured to first of storage first row address input from latch；
Comparator, it is configured to the first row address input described in comparison and is inputted with second row address and be based on described compared
Output control signal；
Wherein described pre-charge circuit is configured to receive the control signal, and is different from based on first row address input
The second row address input, is pre-charged to the bit line.
2. SRAM according to claim 1, wherein the Read Controller is further configured to be based on second row
Address input is identical with the first row address input and reads first memory cell and second memory cell, and nothing
The bit line need to be pre-charged between the reading of first and second memory cell.
3. SRAM according to claim 1, wherein the address detection device further includes the second trigger, it includes the
Two main latch and second are from latch, and second trigger is configured to receive first row address input and described the
Two row addresses are inputted, and are inputted in response to receiving second row address, and it is described that second main latch is configured to storage
The second of second row address input, and described second be configured to the second of storage first row address input from latch
Position.
4. SRAM according to claim 3, wherein the comparator is further configured to：
Compare described first be stored in first main latch be stored in described second from latch described in
First；And
Compare the second being stored in second main latch and be stored in described second described in from latch
Second.
5. SRAM according to claim 4, wherein：
It is described primary described to compare including to described first be stored in first main latch and being stored in institute
First is stated to perform XOR xor operation from described first in latch to produce the first XOR outputs；And
It is described deputy described to compare including to the second being stored in second main latch and being stored in institute
Second is stated to perform xor operation from the second in latch to produce the 2nd XOR outputs.
6. SRAM according to claim 5, wherein the comparator be further configured to the first XOR outputs and
The 2nd XOR outputs perform or non-NOR operate to produce the control signal.
7. SRAM according to claim 1, wherein：
First trigger, which is further configured to receive, indicates depositing to the 3rd memory cell of the memory cell array
Take the third line address input of the third line address of request；
In response to receiving the third line address input, first main latch is configured to store the third line address defeated
First entered, and described first be configured to described first of storage second row address input from latch.
8. SRAM according to claim 7, wherein the comparator is further configured to：
Compare described first be stored in first main latch be stored in described first from latch described in
First；And
Compare the second being stored in second main latch and be stored in described second described in from latch
Second.
9. a kind of method for being used to reduce the power consumption in static RAM SRAM, it includes：
Receive the first row address of the access request for the first memory cell for indicating the memory cell array to being arranged as rows and columns
The first row address input；
With receiving the second row of the second row address for indicating the access request to the second memory cell of the memory cell array
Location is inputted；
In response to receiving the second row address input, the first trigger is stored in by first of second row address input
Main latch in and by first row address input first be stored in first trigger from latch；
Compare the first row address input to input with second row address；And
Second row address input is different from based on first row address input, to multiple positions of the memory cell array
Line is pre-charged.
10. method according to claim 9, wherein the comparison the first row address input and second row address
Input includes：Compare described first be stored in the main latch of first trigger and be stored in described first
Described first from latch of trigger.
11. method according to claim 9, it further comprises：Based on first row address input and described second
Row address input is identical, reads first memory cell and second memory cell without being deposited in described first and second
The bit line is pre-charged between the reading of storage unit.
12. method according to claim 11, it further comprises：
In response to receiving the second row address input, the second that second row address is inputted is stored in the second trigger
Main latch in and by first row address input second be stored in second trigger from latch.
13. method according to claim 12, wherein the comparison the first row address input and second row
Location input includes：
To described first be stored in the main latch of first trigger and it is stored in first trigger
It is described from latch it is described first perform XOR xor operation with produce the first XOR output；
To the second being stored in the main latch of second trigger and it is stored in second trigger
The second from latch xor operation is performed to produce the 2nd XOR outputs；And
First XOR outputs and the 2nd XOR outputs are performed or non-NOR operations.
14. method according to claim 9, it further comprises：
With receiving the third line for the third line address for indicating the access request to the 3rd memory cell of the memory cell array
Location is inputted；
In response to receiving the third line address input, it is stored in described first by first of the third line address input and touches
Send out in the main latch of device and first of second row address input is stored in described in first trigger
From latch；
Compare the second row address input to input with the third line address；And
The third line address input is different from based on second row address input, to multiple positions of the memory cell array
Line is pre-charged.
15. a kind of static RAM SRAM Read Controllers, it includes：
First trigger, it is configured to store the first memory cell for indicating the memory cell array to being arranged as rows and columns
First row address of the first row address of access request is inputted and indicated to the second memory cell of the memory cell array
The second row address input of second row address of access request；
Second trigger, it is configured to storage first and second row address input；And
Comparator, it is configured to first and second row address described in comparison and inputs and be based on described comparing output control signal.
16. SRAM Read Controllers according to claim 15, wherein：
First trigger includes the first main latch and first from latch, and defeated in response to receiving second row address
Enter, first main latch is configured to first of storage second row address input, and described first from latch
It is configured to first of storage the first row address input；And
Second trigger includes the second main latch and second from latch, and defeated in response to receiving second row address
Enter, second main latch is configured to store the second of second row address input, and described second from latch
It is configured to store the second of the first row address input.
17. SRAM Read Controllers according to claim 16, wherein the comparator includes：
First XOR XOR gate, it is configured to be stored in first main latch described first and is stored in institute
First is stated to perform xor operation from described first in latch to produce the first XOR outputs；
Second XOR gate, it is configured to the second to being stored in second main latch and is stored in described
Two perform xor operation to produce the 2nd XOR outputs from the second in latch；And
Or non-NOR-gate, it is configured to perform NOR operations to the first XOR outputs and the 2nd XOR outputs to produce
State control signal.
18. SRAM Read Controllers according to claim 16, wherein the control signal is based on first main latch
Described first in device is equal to described first described in from described first in latch and second main latch
It is high that second, which is equal to described second from the second in latch,.
19. SRAM Read Controllers according to claim 15, it further comprises：Pre-charge circuit, it is configured to
The control signal is received, and second row address input is different from based on first row address input, to corresponding to institute
State the bit line precharge of the row of memory cell array.
20. SRAM Read Controllers according to claim 15, wherein based on first row address input and described the
The input of two row addresses is identical, and the Read Controller is configured to read first memory cell and second storage is single
Member, without between the reading of first and second memory cell to corresponding to described in the memory cell array
The bit line precharge of row.
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| US201514942137A | 2015-11-16 | 2015-11-16 | |
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| US5600601A (en) * | 1994-02-16 | 1997-02-04 | Fujitsu Limited | Semiconductor memory device with reduced consumption power for bit line precharge |
| US6288959B1 (en) * | 2000-08-04 | 2001-09-11 | Dmel Incorporated | Controlling the precharge operation in a DRAM array in a SRAM interface |
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