CN107016954A

CN107016954A - A kind of display panel

Info

Publication number: CN107016954A
Application number: CN201710379437.4A
Authority: CN
Inventors: 陈晓梦; 吴常志; 王伟鹏; 杨康鹏; 许育民
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2017-05-25
Filing date: 2017-05-25
Publication date: 2017-08-04
Anticipated expiration: 2037-05-25
Also published as: CN107016954B

Abstract

The present invention discloses a kind of display panel, including 2N register group, a plurality of grid line and data wire, multiple pixels, in same row pixel, the half-pix data wire different from the connection of another half-pix in the corresponding pixel connection identical data wire of shift register of same register group, same row pixel；Each register group includes the shift register of multiple cascades, the grid line of each shift register correspondence connection interval rows of 2N 1 in each register group, each shift register is cooperated by shifting latch module, control output module and anti-phase output module, the grid line of connection is scanned, and one register group work of control, the grid line for being spaced the rows of 2N 1 is scanned successively；Whole register group sequential workings are controlled in a vertical interval once, complete the scanning of all grid lines, and when grid line is scanned, the data wire of pixel connection corresponding to the grid line inputs the relatively low row flip displays signal of power consumption, with the display effect for showing a picture and realizing point upset.

Description

A kind of display panel

Technical field

The present invention relates to display technology field, more particularly to a kind of display panel.

Background technology

With developing rapidly for Display Technique, direction of the display panel increasingly towards high integration and low cost is developed. Wherein, array base palte row drives (Gate Driver on Array, GOA) technology by thin film transistor (TFT) (Thin Film Transistor, TFT) gate switch circuit is integrated on the array base palte of display panel and driven with forming scanning to display panel It is dynamic, so as to save binding (Bonding) region of grid integrated circuits (Integrated Circuit, IC) and be fanned out to (Fan-out) wiring space in region, not only can be in material cost and the aspect reduction product cost of preparation technology two, Er Qieke So that display panel accomplishes symmetrical and narrow frame the design for aesthetic in both sides.General gate driving circuit is by multiple cascades Shift register is constituted, and the drive signal output end of shift registers at different levels is connected respectively a grid line, is moved by different levels Bit register realize from top to bottom successively to connection grid line input scanning signal to progressively scan, while source electrode drive circuit to Pieces of data line loads corresponding data-signal, to complete to show a picture.

For example, as shown in figure 1, inside the display panel using the pixel arrangement of zig-zag type (Rainbow Zigzag) when, Be connected respectively with the pixel of both sides according to the zig-zag type dotted line shown in Fig. 1 per data line Data, due in grid line line by line During scanning, during to pure color pictures such as display red, green, blues, the current potential of the display signal loaded per data line Every row is needed to be continually changing, the problem of causing to be unfavorable for saving the power consumption of display panel.

The content of the invention

The embodiment of the present invention provides a kind of display panel, to solve in the prior art due to when grid line is progressively scanned, During to the display pure color picture such as red, green, blue, the current potential of the display signal loaded per data line needs often to go continuous change Change, cause to be unfavorable for saving power problemses.

Therefore, the embodiments of the invention provide a kind of display panel, including a plurality of grid line, with grid line insulation intersect and set The color of each pixel in a plurality of data lines put, the multiple pixels limited by the grid line and the data wire, same row It is identical, and the connection only corresponding with a pixel in same a line of any data wire, the display panel also includes：2N are posted Storage group, each register group includes the shift register of multiple cascades；Each shift LD in the same register group Device be connected by drive signal output end with being spaced the grid line of 2N-1 rows respectively, and each register group is correspondingly different described Grid line, N is positive integer；In the same row pixel, belong to the corresponding pixel connection of shift register of same register group A half-pix in identical data wire, and the same row pixel data wire different from the connection of another half-pix；

In the same register group, the input signal end of first order shift register is connected with frame start signal end, its Cascade signal of the input signal end of each remaining shift register respectively with shift register described in respective adjacent upper level is defeated Go out end to be connected；

The shift register includes：Shift latch module, control output module and anti-phase output module；Wherein, institute State displacement latch module respectively with the input signal end of the shift register, cascade signal output end and the first clock signal End is connected, under the co- controlling for the signal that the input signal end and first clock signal terminal are exported, making described Cascade signal output end output cascade signal；It is described control output module respectively with the cascade signal output end, second clock Signal end, scan control signal end and the anti-phase output module are connected, in the cascade signal, the second clock Under the co- controlling of signal end and the signal of scan control signal end output anti-phase scanning is exported to the anti-phase output module Signal；The anti-phase output module is connected with the drive signal output end of the shift register, for being swept to the anti-phase of reception Retouch signal and carry out anti-phase output to the drive signal output end.

Preferably, in above-mentioned display panel provided in an embodiment of the present invention, the displacement latch module includes：First is anti- Phase device, the second phase inverter, the first tri-state NAND gate, the second tri-state NAND gate；Wherein,

The input of first phase inverter is connected with first clock signal terminal, the output end of first phase inverter It is connected with the first control end of the first tri-state NAND gate；

The input of the first tri-state NAND gate is connected with the input signal end, and the of the first tri-state NAND gate Two control ends are connected with first clock signal terminal, the output end of the first tri-state NAND gate and second phase inverter Input is connected；

The output end of second phase inverter is connected with the cascade signal output end；

First control end of the second tri-state NAND gate is connected with first clock signal terminal, second tri-state with The input of NOT gate is connected with the cascade signal output end, the second control end of the second tri-state NAND gate and described first The output end of phase inverter is connected, and the output end of the second tri-state NAND gate is connected with the input of second phase inverter.

Preferably, in above-mentioned display panel provided in an embodiment of the present invention, the shift register also includes：Reset brilliant Body pipe；Wherein, the control pole of the reset transistor is connected with reset signal end, and the first pole is connected with reference signal end, and second Pole is connected with the input of second phase inverter.

Preferably, in above-mentioned display panel provided in an embodiment of the present invention, the control output module includes：Three inputs NAND gate；Wherein,

The first input end of three input nand gate is connected with the cascade signal output end, the second input with it is described Second clock signal end is connected, and the 3rd input is connected with the scan control signal end, output end and the anti-phase output mould Block is connected.

Preferably, in above-mentioned display panel provided in an embodiment of the present invention, the anti-phase output module includes：3rd is anti- Phase device；The input of wherein described 3rd phase inverter is connected with the control output module, output end and corresponding drive signal Output end is connected.

Preferably, in above-mentioned display panel provided in an embodiment of the present invention, N=1, the scan control signal end bag Include：First scan control signal end and the second scan control signal end；Wherein, each shift register in the 1st register group connects Each shift register connect in the first scan control signal end, the 2nd register group connects second scan control signal End.

Preferably, in above-mentioned display panel provided in an embodiment of the present invention, N=1, each displacement in the 1st register group Register connects the scan control signal end；

The display panel also includes：Each shift register in anti-phase control module, the 2nd register group passes through institute Anti-phase control module is stated with the scan control signal end to be connected.

Preferably, in above-mentioned display panel provided in an embodiment of the present invention, at least two phases in the 2nd register group Adjacent shift register is connected by same anti-phase control module with the scan control signal end；Or,

Each shift register passes through one-to-one anti-phase control module and the scanning in the 2nd register group Control signal end is connected.

Preferably, in above-mentioned display panel provided in an embodiment of the present invention, the anti-phase control module includes：4th is anti- Phase device；Wherein, the input of the 4th phase inverter is connected with the scan control signal end, and output end is posted with corresponding displacement Storage is connected.

Preferably, in above-mentioned display panel provided in an embodiment of the present invention, the display panel also includes：With it is each described The source electrode drive circuit of data wire connection；Wherein,

When the display panel shows pure color picture, each shift register work in each register group In time, the same colored pixels institute that the source electrode drive circuit is used in multiple pixels only for each grid line connection of scanning The data wire loading data-signal of connection；Wherein, the polarity of the data-signal loaded on the same data wire is identical；

When the display panel shows colour picture, each shift register work in each register group In time, the source electrode drive circuit is used for the data-signal to loading opposed polarity per adjacent two data line；Wherein, it is same The polarity of the data-signal loaded on the data wire is identical.

Preferably, in above-mentioned display panel provided in an embodiment of the present invention, each shift register is included and set respectively Left side shift register and right side shift register in same grid line two ends；And in each shift register work, Left side shift register and right side shift register positioned at same grid line both sides work simultaneously.

The present invention has the beneficial effect that：

Display panel provided in an embodiment of the present invention, including 2N register group, a plurality of grid line, intersect with grid line insulation and set The a plurality of data lines put, each register group includes the shift register of multiple cascades；In same register group, first order displacement is posted The input signal end of storage is connected with frame start signal end, the input signal end of remaining each shift register respectively with respective phase The cascade signal output end of adjacent upper level shift register is connected；Each shift register in same register group passes through respectively Drive signal output end is connected with being spaced the grid line of 2N-1 rows, and the different grid line of each register group correspondence, and N is positive integer； During one register group work, each shift register in the register group can successively be swept to the grid line for being spaced 2N-1 rows Retouch, therefore each register group sequential working is controlled once in a vertical interval, complete the scanning of all grid lines to realize Show a picture.And because the corresponding pixel of the shift register in same row pixel, belonging to same register group connects Connect a half-pix in identical data wire, the same row pixel data wire different from the connection of another half-pix；So as in grid line When being scanned, the data wire of pixel connection corresponding to the grid line inputs the relatively low row flip displays signal of power consumption, can make The picture of display realizes the display effect of point upset.And each shift register can include：Shift latch module, control output Three modules of module and anti-phase output module, wherein, displacement latch module is used at input signal end and the first clock signal Hold under the co- controlling of signal of output, make cascade signal output end output cascade signal；Output module is controlled to be used in cascade Exported under the co- controlling of the signal of signal, second clock signal end and the output of scan control signal end to anti-phase output module Anti-phase scanning signal；Anti-phase output module is used to export the anti-phase scanning signal progress anti-phase output of reception to drive signal End, therefore by the mutual cooperations of these three modules shift register can be made to realize the output of scanning signal.

Brief description of the drawings

Fig. 1 is a kind of structural representation of pixel arrangements of display panel of the prior art；

Fig. 2 a are one of structural representation of display panel provided in an embodiment of the present invention；

Fig. 2 b are the two of the structural representation of display panel provided in an embodiment of the present invention；

Fig. 2 c are the three of the structural representation of display panel provided in an embodiment of the present invention；

Fig. 2 d are the four of the structural representation of display panel provided in an embodiment of the present invention；

Fig. 3 is the structural representation of shift register provided in an embodiment of the present invention；

Fig. 4 a are data wire when display panel provided in an embodiment of the present invention shows pure color picture in a vertical interval The schematic diagram of loaded and displayed signal；

Fig. 4 b are data wire when display panel provided in an embodiment of the present invention shows colour picture in a vertical interval The schematic diagram of loaded and displayed signal；

Fig. 5 a are one of concrete structure schematic diagram of shift register provided in an embodiment of the present invention；

Fig. 5 b are the two of the concrete structure schematic diagram of shift register provided in an embodiment of the present invention；

Fig. 6 is the concrete structure schematic diagram of three input nand gate provided in an embodiment of the present invention；

Fig. 7 a are the corresponding input and output sequential chart of shift register shown in Fig. 5 a；

Fig. 7 b are the corresponding input and output sequential chart of shift register shown in Fig. 5 b；

Fig. 8 is the corresponding input and output sequential chart of display panel in embodiment three.

Embodiment

In order that the purpose of the present invention, technical scheme and advantage are clearer, below in conjunction with the accompanying drawings, to the embodiment of the present invention The embodiment of the display panel of offer is described in detail.It should be appreciated that preferred embodiment disclosed below is only For instruction and explanation of the present invention, it is not intended to limit the present invention.And in the case where not conflicting, the embodiment in the application And the feature in embodiment can be mutually combined.

The embodiments of the invention provide a kind of display panel, with reference to Fig. 2 a to Fig. 3, (Fig. 2 a to Fig. 2 c including 2 to post Exemplified by storage group, Fig. 2 d are exemplified by including 4 register groups) shown in structural representation, as shown in Fig. 2 a to Fig. 2 d, display surface Plate can include：A plurality of grid line Gate_x (X, X are positive integer for x=1,2,3 ...), with grid line Gate_x insulate intersect setting it is many Data line Data_m (M, M are positive integer for m=1,2,3 ...), the multiple pictures limited by grid line Gate_x and data wire Data_m The color of each pixel is identical in element, same row, and any data line Data_m connections only corresponding with a pixel in same a line, Display panel also includes：2N register group 100_n (2N of n=1,2,3 ...), each register group 100_n includes multiple cascades Shift registerEach shift register SR (y) in same register group 100_n _ N is connected with being spaced the grid line of 2N-1 rows respectively by drive signal output end Out1, and each register group 100_n correspondences are different Grid line, N is positive integer；In same row pixel, shift register SR (the y) _ n for belonging to same register group 100_n is corresponding The half-pix data wire different from the connection of another half-pix in pixel connection identical data wire, and same row pixel；

In same register group 100_n, first order shift register SR (1) _ n input signal end Input and frame are originated Signal end STV is connected, and remaining each shift register SR (y) _ n input signal end Input is respectively with each adjacent upper one Level shift register SR (y-1) _ n cascade signal output end Out2 is connected；

As shown in figure 3, shift register SR (y) _ n can specifically include：Shift latch module 110, control output module 120 and anti-phase output module 130；Wherein,

Input signal end Input, the cascade signal of latch module 110 respectively with shift register SR (y) _ n is shifted to export Out2 and the first clock signal terminal CK1 is held to be connected, in input signal end Input and the first clock signal terminal CK1 outputs Signal co- controlling under, make cascade signal output end Out2 output cascade signals；

Output module 120 is controlled to believe respectively with cascade signal output end Out2, second clock signal end CK2, scan control Number end CIN and anti-phase output module 130 be connected, for cascade signal, second clock signal end CK2 and scan control letter Number end CIN output signal co- controlling under export anti-phase scanning signal to anti-phase output module 130；

Anti-phase output module 130 is connected with shift register SR (y) _ n drive signal output end Out1, for receiving Anti-phase scanning signal carry out anti-phase output give drive signal output end Out1.

Above-mentioned display panel provided in an embodiment of the present invention, including 2N register group, a plurality of grid line, insulate phase with grid line The a plurality of data lines set is handed over, each register group includes the shift register of multiple cascades；In same register group, the first order is moved The input signal end of bit register is connected with frame start signal end, the input signal end of remaining each shift register respectively with respectively It is connected from the cascade signal output end of adjacent upper level shift register；Each shift register difference in same register group It is connected by drive signal output end with being spaced the grid line of 2N-1 rows, and the different grid line of each register group correspondence, N is just whole Number；In a register group job, each shift register in the register group can be to being spaced the grid line of 2N-1 rows successively It is scanned, therefore each register group sequential working is controlled once in a vertical interval, completes the scanning of all grid lines A picture is shown to realize.And because the shift register in same row pixel, belonging to same register group is corresponding Pixel connects identical data wire, the data wire different from the connection of another half-pix of the half-pix in same row pixel；So as to When grid line is scanned, the data wire of pixel connection corresponding to the grid line inputs the relatively low row flip displays signal of power consumption, The picture of display can be made to realize the display effect of point upset.And each shift register can include：Shift latch module, control Three modules of output module processed and anti-phase output module, wherein, displacement latch module is used for when input signal end is with first Under the co- controlling of the signal of clock signal end output, make cascade signal output end output cascade signal；Control output module is used for To anti-phase output mould under the co- controlling for the signal that cascade signal, second clock signal end and scan control signal end are exported Block exports anti-phase scanning signal；Anti-phase output module is used to carry out anti-phase output to drive signal to the anti-phase scanning signal of reception Output end, therefore by the mutual cooperations of these three modules shift register can be made to realize the output of scanning signal.

In the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, in same row pixel, belong to same A half-pix in the shift register of one register group corresponding pixel connection identical data wire, and same row pixel with Another half-pix connects different data wires.For example, being to include 2 register groups as shown in Fig. 2 a to Fig. 2 c；Wherein, along number The row pixel arranged according to line Data_1 bearing of trends, each shift register SR (1) _ 1, SR (2) with register group 100_1 _ The pixel of 1 ... correspondence row, the i.e. pixel of odd-numbered line is connected with data wire Data_1；Each displacement with register group 100_2 is posted The pixel of storage SR (1) _ 2, SR (2) _ 2 ... correspondence row, the i.e. pixel of even number line is connected with data wire Data_2.Such as 2d institutes Show, be to include 4 register groups；Wherein, the row pixel arranged along data wire Data_1 bearing of trends, with register group 100_ 1 each shift register SR (1) _ 1, the pixel of SR (2) _ 1 ... correspondence rows are connected with data wire Data_1；With register group 100_2 each shift register SR (1) _ 2, the pixel of SR (2) _ 2 ... correspondence rows are connected with data wire Data_2；With register Group 100_3 each shift register SR (1) _ 3, the pixel of SR (2) _ 3 ... correspondence rows are connected with data wire Data_1；With deposit Device group 100_4 each shift register SR (1) _ 4, the pixel of SR (2) _ 4 ... correspondence rows are connected with data wire Data_2.When So, when display panel includes 4 register groups, each shift register SR (1) _ 1, SR in register group 100_1 can also be made (2) _ 1 ... the picture of the corresponding row of pixel and each shift register SR (1) _ 2 in register group 100_2 of correspondence row, SR (2) _ 2 ... Element is connected with data wire Data_1, each shift register SR (1) _ 3, the picture of SR (2) _ 3 ... correspondence rows in register group 100_3 The pixel of element row corresponding with each shift register SR (1) _ 4 in register group 100_4, SR (2) _ 4 ... with data wire Data_ 2 are connected, and are not limited thereto.Also, when display panel is including 6,8,10 ... individual register group, the rest may be inferred, does not make herein It is described in detail.

It is preferred that in the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, in same row pixel, It can make to connect different data wires per two neighboring pixel.For example, as shown in Fig. 2 a to Fig. 2 d, extending along data wire Data_1 A row pixel, the pixel of odd-numbered line is connected with data wire Data_1, and the pixel of even number line is connected with data wire Data_2.

In the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, as shown in Figure 2 a, 2 can be included Individual register group, i.e. N=1, scan control signal end CIN can specifically include：First scan control signal end Cin_1 and second Scan control signal end Cin_2；Wherein, each shift register SR (y) in the 1st register group 100_1 _ 1 connects first and scanned Each shift register SR (y) _ 2 in control signal end Cin_1, the 2nd register group 100_2 connect the second scan control signal end Cin_2.First scan control signal end Cin_1 and the second scan control signal end Cin_2 signal phase is on the contrary, and first sweep The signal for retouching control signal end Cin_1 is high potential in the preceding field of a vertical interval, is low potential in rear field.

Or, as shown in Figure 2 d, 4 register groups can also be included, i.e. N=2, scan control signal end CIN is specifically wrapped Include：First scan control signal end Cin_1, the second scan control signal end Cin_2, the 3rd scan control signal end Cin_3 with And the 4th scan control signal end Cin_4；Wherein, the connection of each shift register SR (y) in the 1st register group 100_1 _ 1 the Each shift register SR (y) _ 2 in one scan control signal end Cin_1, the 2nd register group 100_2 connect the second scan control Signal end Cin_2.Each shift register SR (y) _ 3 in 3rd register group 100_3 connect the 3rd scan control signal end Cin_ Each shift register SR (y) _ 4 in 3, the 4th register group 100_4 connect the 4th scan control signal end Cin_4.Also, one In vertical interval, the first scan control signal end Cin_1 is only at firstIt is high potential in frame time, remaining time is Low potential.Second scan control signal end Cin_2 is only at secondIt is high potential in frame time, remaining time is low electricity Position.3rd scan control signal end Cin_3 is only at the 3rdIt is high potential in frame time, remaining time is low potential.The Four scan control signal end Cin_4 are only at the 4thIt is high potential in frame time, remaining time is low potential.Similarly, exist During including 6,8 ... individual register group, the rest may be inferred, is not described in detail here.

In order to reduce the setting of signal wire in display panel, in the specific implementation, provided in an embodiment of the present invention above-mentioned In display panel, as shown in Figure 2 b, each displacement that can include in 2 register groups, i.e. N=1, the 1st register group 100_1 is posted Storage SR (y) _ 1 can connect scan control signal end CIN；

The display panel also includes：Each shift register SR in the anti-phase register group 100_2 of control module the 200, the 2nd (y) _ 2 it is connected by anti-phase control module 200 with scan control signal end CIN.Only with a signal line and it can so lead to Over-scan control signal end CIN, you can each shift register SR (y) _ 1 and the 2nd deposit in the 1st register group 100_1 of control Each shift register SR (y) _ 2 in device group 100_2 export scanning signal.The signal at scan control signal end is in a frame scan Between preceding field in be high potential, in rear field be low potential.

In order to further reduce space-consuming, in the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention In, as shown in Figure 2 b, all shift register SR (y) _ 2 in the 2nd register group 100_2 pass through an anti-phase control module 200 are connected with scan control signal end CIN.

In order to accurately control each shift register SR (y) _ 2 in the 2nd register group 100_2, in the specific implementation, at this In the above-mentioned display panel that inventive embodiments are provided, as shown in Figure 2 c, each shift register SR in the 2nd register group 100_2 (y) _ 2 it is connected by one-to-one anti-phase control module 200 with scan control signal end CIN.

It is of course also possible to when ensureing to be precisely controlled, the setting of anti-phase control module be reduced as far as possible, such as makes at least two Shift register is connected by an anti-phase control module with scan control signal end, in the specific implementation, in present invention implementation In the above-mentioned display panel that example is provided, at least two adjacent shift registers pass through same anti-phase control in the 2nd register group Molding block is connected with scan control signal end.

In the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, it can make in a register group All shift registers be set together, can also be arranged alternately each shift register in each register group, with reality The effect now scanned successively to the grid line for being spaced 2N-1 rows, is not limited thereto.

When each pixel in display panel loads data-signal, using a display effect of upset preferably, i.e., often go The positive-negative polarity for the data-signal that adjacent and two adjacent sub-pixels of row are loaded is different.In the specific implementation, of the invention real In the above-mentioned display panel for applying example offer, as shown in Fig. 2 a to Fig. 2 d, display panel specifically also includes：It is connected with each data wire Source electrode drive circuit 400；Wherein,

When display panel shows pure color picture, in each shift register working time in each register group, source electrode The data wire that the same colored pixels that drive circuit 400 is used in multiple pixels only for each grid line connection of scanning are connected Load data-signal；Wherein, the polarity of the data-signal loaded on same data wire is identical；

When display panel shows colour picture, in each shift register working time in each register group, source electrode Drive circuit 400 is used for the data-signal to loading opposed polarity per adjacent two data line；Wherein, loaded on same data wire Data-signal polarity it is identical.

General display panel includes red pixel, green pixel and blue pixel, as shown in Fig. 4 a and Fig. 4 b, display surface Plate includes：Red pixel R, green pixel G and blue pixel B.Exemplified by including 2 register groups, as shown in fig. 4 a, the 1st Register group 100_1 and the grid line of odd-numbered line are connected, and the grid line of the 2nd register group 100_2 and even number line is connected.In display panel During the red pure color picture of display, in a vertical interval, the order of each shift register SR (y) in the 1st register group 100_1 _ 1 Work, the then sequential working of each shift register SR (y) in the 2nd register group 100_2 _ 2.In each shift register SR (y) _ 1 During sequential working, grid line Gate_1, Gate_3, grid line Gate_5 are scanned successively.Source electrode drive circuit can only need to be directed to The data-signal 310 of the positive polarity of data wire Data_1 input row upsets, the negative pole for arranging upset is inputted for data wire Data_4 The data-signal 320 of property.In each shift register SR (y) _ 2 sequential working, successively to grid line Gate_2, Gate_4, grid line Gate_6 is scanned.Source electrode drive circuit can only need to input the data-signal of the negative polarity of row upset for data wire Data_2 320, the data-signal 310 for the positive polarity for arranging upset is inputted for data wire Data_5, you can so that display panel is showing red The effect of dot inversion is realized during colour purity color picture.And because the data-signal in a vertical interval on every data line is not required to Carry out change in polarity, you can realize the display effect of whole display panel point upset.So can ensure display effect compared with In the case of good, the positive-negative polarity switching times of data-signal are reduced, so as to reduce the power consumption of display panel.Similarly, exist When display panel display green or blue pure color picture, the operation principle of shift register and source electrode drive circuit and above-mentioned display Operation principle during red pure color picture is essentially identical, and therefore not to repeat here.Also, due to provided in an embodiment of the present invention above-mentioned Display panel can realize red, green, blue pure color picture, therefore polaroid, driving chip (IC), print can be assembled in display panel It is inclined in assembling so as to avoid before the equipment such as printed circuit board, you can the detection process of pure color picture is carried out to display panel After the equipment such as mating plate, driving chip (IC), printed circuit board (PCB), when carrying out the detection of pure color picture, display panel does not conform to Lattice and cause additionally to consume equipment, cause the problem of cost is improved.

When display panel shows colour picture, in a vertical interval, each displacement is posted in the 1st register group 100_1 The sequential working of storage SR (y) _ 1, the then sequential working of each shift register SR (y) in the 2nd register group 100_2 _ 2.Such as Fig. 4 b It is shown, in each shift register SR (y) _ 1 sequential working, grid line Gate_1, Gate_3, grid line Gate_5 are scanned successively. Source electrode drive circuit can only need to input data wire Data_1, Data_3, Data_5 in the data letter of the positive polarity of row upset Numbers 330, the data-signal 340 for the negative polarity for arranging upset is inputted to data wire Data_2, Data_4, Data_6.Posted in each displacement During storage SR (y) _ 2 sequential working, grid line Gate_2, Gate_4, grid line Gate_6 are scanned successively.Source electrode drive circuit can be with Only need to input data wire Data_1, Data_3, Data_5 the data-signal 330 for arranging the positive polarity overturn, to data wire The data-signal 340 of the negative polarity of Data_2, Data_4, Data_6 input row upset, you can so that display panel is color in display The effect of dot inversion is realized during color picture.And because the data-signal in a vertical interval on every data line need not enter Row change in polarity, you can realize the display effect of whole display panel point upset.Can so display effect ensured preferably In the case of, the positive-negative polarity switching times of data-signal are reduced, so as to reduce the power consumption of display panel.

Can be by the way of unilateral driving in display panel, i.e., the shift register in each register group is arranged on respectively The same side of grid line, you can be provided only on the left side or right side of each grid line simultaneously, each grid line can also be provided only on simultaneously Upside or downside, are not limited thereto.Certainly, the shift register in each register group can also be arranged on component register The side of each grid line, makes another part register group be arranged on the opposite side of each grid line, and this needs is set according to actual application environment Meter is determined.

Can be by the way of bilateral driving in display panel, it is particularly possible to adopted in the display panel of big-and-middle molded dimension With the mode of bilateral driving so that display effect more preferably.In the specific implementation, in above-mentioned display surface provided in an embodiment of the present invention In plate, each shift register includes the left side shift register and right side shift LD for being respectively arranged at same grid line two ends Device；And when each shift register works, left side shift register and right side shift register positioned at same grid line both sides Work simultaneously.

In the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, in each register group Each shift register of cascade, wherein, the first clock signal terminal and 2m grades of shift LDs of 2m-1 grades of shift registers The second clock signal end of device is connected with same Clock control end, i.e. the first Clock control end；2m-1 grades of shift LDs The second clock signal end of device and the first clock signal terminal of 2m grades of shift registers with same Clock control end, i.e., Two Clock control ends are connected.For example, as shown in Fig. 2 a to Fig. 2 d, CKV1 represents the first Clock control end, when CKV2 represents second Clock control end, k is the integer more than or equal to 1.

With reference to specific embodiment, the present invention is described in detail.It should be noted that be in the present embodiment in order to The present invention is preferably explained, but does not limit the present invention.

In the specific implementation, it is anti-phase as shown in Fig. 2 b and Fig. 2 c in above-mentioned display panel provided in an embodiment of the present invention Control module 200 can specifically include：4th phase inverter N4；Wherein,

4th phase inverter N4 input is connected with scan control signal end CIN, output end and corresponding shift register SR (y) _ 2 are connected.

In the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, the 4th phase inverter can make its defeated The signal for going out end output is opposite with the current potential of the signal of its input.

In the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, as shown in Fig. 5 a and Fig. 5 b, displacement Latch module 110 can specifically include：First phase inverter N1, the second phase inverter N2, the first tri-state NAND gate D1, the second tri-state with NOT gate D2；Wherein,

First phase inverter N1 input is connected with the first clock signal terminal CK1, the first phase inverter N1 output end and the One tri-state NAND gate D1 the first control end is connected；

First tri-state NAND gate D1 input is connected with input signal end Input, and the second of the first tri-state NAND gate D1 Control end is connected with the first clock signal terminal CK1, the first tri-state NAND gate D3 output end and the second phase inverter N2 input It is connected；

Second phase inverter N2 output end is connected with cascade signal output end Out2；

Second tri-state NAND gate D2 the first control end is connected with the first clock signal terminal CK1, the second tri-state NAND gate D2 Input be connected with cascade signal output end Out2, the second tri-state NAND gate D2 the second control end is with the first phase inverter N1's Output end is connected, and the second tri-state NAND gate D2 output end is connected with the second phase inverter N2 input.

In the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, the first phase inverter and second anti-phase The signal that device can export its output end is opposite with the current potential of the signal of its input.First tri-state NAND gate is in its first control When the signal at end processed is low potential and the first control end opposite with the current potential of the signal of the second control end, its output end is exported and it The opposite signal of the current potential of the signal of input.Second tri-state NAND gate is low potential and first in the signal of its first control end When control end is opposite with the current potential of the signal of the second control end, the output of its output end is opposite with the current potential of the signal of its input Signal.

In the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, the first tri-state NAND gate and second The structure of tri-state NAND gate can be identical with the structure of tri-state NAND gate of the prior art, and can for those skilled in the art Have to understand, therefore not to repeat here, can not be used as limitation of the present invention.

In the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, as shown in Fig. 5 a and Fig. 5 b, control Output module 120 can specifically include：Three input nand gate TN；Wherein,

Three input nand gate TN first input end A is connected with cascade signal output end Out2, the second input B and second Clock signal terminal CK2 is connected, and the 3rd input C is connected with scan control signal end CIN, output end Y and anti-phase output module 130 It is connected.

In the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, three input nand gates only its When the signal of one input, the second input and the 3rd input is high potential, its output end exports the signal of low potential.

In the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, as shown in fig. 6, three input with it is non- Door can specifically include：First switch transistor M1, second switch transistor M2, the 3rd switching transistor M3, the 4th switch are brilliant Body pipe M4, the 5th switching transistor M5 and the 6th switching transistor M6；Wherein,

First switch transistor M1 control pole is connected with cascade signal output end Out2, for being used as three input nand gates First input end, the first pole is connected with high-potential voltage end VGH, the second pole as three input nand gates output end Y.

Second switch transistor M2 control pole is connected with second clock signal end CK2, for being used as three input nand gates The second input, the first pole is connected with high-potential voltage end VGH, the second pole as three input nand gates output end Y.

3rd switching transistor M3 control pole is connected with scan control signal end CIN, for being used as three input nand gates The 3rd input, the first pole is connected with high-potential voltage end VGH, the second pole as three input nand gates output end Y.

4th switching transistor M4 control pole is connected with cascade signal output end Out2, the first pole and the 5th switch crystal The second of pipe M5 extremely be connected, the second pole as three input nand gates output end Y.

5th switching transistor M5 control pole is connected with second clock signal end CK2, the first pole and the 6th switch crystal The second of pipe M6 is extremely connected.

6th switching transistor M6 control pole is connected with scan control signal end CIN, the first pole and low-potential voltage end VGL is connected.

In the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, as shown in fig. 6, first switch is brilliant Body pipe M1, second switch transistor M2 and the 3rd switching transistor M3 can be P-type transistor, the 4th switching transistor M4, 5th switching transistor M5 and the 6th switching transistor M6 can be N-type transistor.

In the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, three input nand gates can pass through Above-mentioned first switch transistor, second switch transistor and the 3rd switching transistor, the 4th switching transistor, the 5th switch are brilliant The mutual cooperation of body pipe and the 6th switching transistor, makes three input nand gates realize the letter only exported in cascade signal output end Number current potential, the current potential of the signal of second clock signal end output and the current potential of signal of scan control signal end output be During high potential, its output end is set to export the signal of low potential.Certainly, the structure of three input nand gates can also for it is other can be real The structure of existing function of the present invention.In actual applications, this needs designs determination according to actual application environment, does not limit herein It is fixed.

In the specific implementation, it is anti-phase as shown in Fig. 5 a and Fig. 5 b in above-mentioned display panel provided in an embodiment of the present invention Output module 130 can specifically include：3rd phase inverter N3；Wherein,

3rd phase inverter N3 input is connected with control output module 120, and output end is exported with corresponding drive signal Out1 is held to be connected.

Further, for the intensity of the drive signal that strengthens output, in the specific implementation, provided in the embodiment of the present invention Above-mentioned display panel in, shift register can also include：Amplifier；Wherein, the 3rd phase inverter passes through amplifier and driving Signal output part is connected；

The input of amplifier is connected with the output end of the 3rd phase inverter, the output end of amplifier and the drive of shift register Dynamic signal output part is connected.

In the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, amplifier is used for the drive to input Dynamic signal is exported after being amplified gives drive signal output end.

Further, in order to strengthen the 3rd phase inverter output drive signal cushioning effect, as shown in Figure 5 b, display surface Anti-phase output module 130 in plate can also specifically include：5th phase inverter N5 and hex inverter N6；Wherein, the 3rd is anti-phase Device N3 is connected by the 5th phase inverter N5 with hex inverter N6 with corresponding drive signal output end Out1；

5th phase inverter N5 input is connected with the 3rd phase inverter N3 output end, the 5th phase inverter N5 output end with Hex inverter N6 input is connected, and hex inverter N6 output end is connected with corresponding drive signal output end Out1.

In the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, the 3rd phase inverter, the 5th phase inverter And hex inverter can make the signal of its output end opposite with the current potential of the signal of its input.

Further, in order to being resetted after the completion of shift register output, in the specific implementation, in present invention implementation In the above-mentioned display panel that example is provided, as shown in Figure 5 b, shift register can also include：Reset transistor M0；Wherein,

Reset transistor M0 control pole is connected with reset signal end Re, and the first pole is connected with reference signal end Vref, the Two poles are connected with the second phase inverter N2 input.

In the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, as shown in Figure 5 b, reset transistor M0 can be P-type transistor.Certainly, reset transistor can also be N-type transistor, be not limited thereto.

In the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, reset transistor is in reset signal The signal at reference signal end is supplied to the input of the second phase inverter under the control of the signal at end.

In the specific implementation, in above-mentioned display panel provided in an embodiment of the present invention, the electricity of the signal at reference signal end Position is high potential.

In the specific implementation, N-type transistor is turned under high potential effect, is ended under low potential effect；P-type transistor End under high potential effect, turned under low potential effect.

In the specific implementation, each transistor in above-mentioned display panel provided in an embodiment of the present invention can be film crystal Manage (TFT, Thin Film Transistor) or metal oxide semiconductor field effect tube (MOS, Metal Oxide Scmiconductor), it is not limited thereto.In specific implementation, the control pole of each transistor can be used as its grid, and Can be according to type and the difference of the signal of input, using the first pole as source electrode or drain electrode, and it regard the second pole as drain electrode Meeting source electrode, these needs design determination according to actual application environment, are not limited thereto.

It the above is only the concrete structure for illustrating each module in shift register provided in an embodiment of the present invention, specific During implementation, the concrete structure of above-mentioned each module is not limited to said structure provided in an embodiment of the present invention, can also be this area skill Other structures knowable to art personnel, are not limited thereto.

In the specific implementation, above-mentioned display panel provided in an embodiment of the present invention can be：Mobile phone, tablet personal computer, TV Any product or part with display function such as machine, display, notebook computer, DPF, navigator.For the display Other essential parts of panel are it will be apparent to an ordinarily skilled person in the art that have, not do superfluous herein State, also should not be taken as limiting the invention.

Below by taking the structure of the shift register shown in Fig. 5 a and Fig. 5 b as an example, combined circuit timing diagram is implemented to the present invention The course of work of shift register in the above-mentioned display panel that example is provided is described.In described below high potential is represented with 1 Signal, 0 represents low-potential signal, wherein, 1 and 0 represents its logic level, merely to preferably explaining that the embodiment of the present invention is carried The course of work of shift register in the above-mentioned display panel supplied, rather than the voltage applied in the specific implementation.

Embodiment one,

By taking the shift register shown in Fig. 5 a as an example, Fig. 7 a are corresponding input and output sequential chart.Specifically, it is main to choose T1, T2 and T3 three phases in input and output sequential chart shown in Fig. 7 a.Scan control signal end CIN current potential is high electricity Position.

In the T1 stages, Input=1, CK1=1, CK2=0.

Due to CK1=1, therefore the second tri-state NAND gate D2 ends, the first phase inverter N1 output end output low potential Signal, turns on the first tri-state NAND gate D1.And because Input=1, therefore the first tri-state NAND gate D1 output end are exported The signal of low potential, therefore the second phase inverter N2 exports the cascade signal of high potential to cascade signal output end Out2.Due to CK2 =0, Out2=1, CIN=1, thus input from three input nand gate TN to the 3rd phase inverter N3 output the anti-phase of high potential sweep Signal is retouched, the 3rd phase inverter N3 is exported the drive signal of low potential to drive signal output end Out1.

Afterwards, Input=1, CK1=0, CK2=0.

Due to CK1=0, therefore the second tri-state NAND gate D2 is turned on, the first phase inverter N1 output end output high potential Signal, ends the first tri-state NAND gate D1.And because Out2=1, therefore the second tri-state NAND gate D2 output end are exported The signal of low potential, therefore the second phase inverter N2 exports the cascade signal of high potential to cascade signal output end Out2.Due to CK2 =0, Out2=1, CIN=1, thus input from three input nand gate TN to the 3rd phase inverter N3 output the anti-phase of high potential sweep Signal is retouched, the 3rd phase inverter N3 is exported the drive signal of low potential to drive signal output end Out1.

In T2 stages, Input=0, CK1=0, CK2=1.

Due to CK1=0, therefore the second tri-state NAND gate D2 is turned on, the first phase inverter N1 output end output high potential Signal, ends the first tri-state NAND gate D1.And because Out2=1, therefore the second tri-state NAND gate D2 output end are exported The signal of low potential, therefore the second phase inverter N2 exports the cascade signal of high potential to cascade signal output end Out2.Due to CK2 =1, Out2=1 and CIN=1, therefore three input nand gate TN export the anti-of low potential to the 3rd phase inverter N3 input Scanning phase signal, makes the 3rd phase inverter N3 export the drive signal of high potential to drive signal output end Out1.

Afterwards, Input=0, CK1=0, CK2=0.

In T3 stages, Input=0, CK1=1, CK2=0.

Due to CK1=1, therefore the second tri-state NAND gate D2 ends, the first phase inverter N1 output end output low potential Signal, turns on the first tri-state NAND gate D1.And because Input=0, therefore the first tri-state NAND gate D1 output end are exported The signal of high potential, therefore the second phase inverter N2 exports the cascade signal of low potential to cascade signal output end Out2.Due to CK2 =0, Out2=0, CIN=1, thus input from three input nand gate TN to the 3rd phase inverter N3 output the anti-phase of high potential sweep Signal is retouched, the 3rd phase inverter N3 is exported the drive signal of low potential to drive signal output end Out1.

Afterwards, Input=0, CK1=0, CK2=0.

Due to CK1=0, therefore the second tri-state NAND gate D2 is turned on, the first phase inverter N1 output end output high potential Signal, ends the first tri-state NAND gate D1.And because Out2=0, therefore the second tri-state NAND gate D2 output end are exported The signal of high potential, therefore the second phase inverter N2 exports the cascade signal of low potential to cascade signal output end Out2.Due to CK2 =0, Out2=0, CIN=1, thus input from three input nand gate TN to the 3rd phase inverter N3 output the anti-phase of high potential sweep Signal is retouched, the 3rd phase inverter N3 is exported the drive signal of low potential to drive signal output end Out1.

After the T3 stages, due to Out2=0, no matter the first clock signal terminal CK1 and second clock signal end CK2 letter Number how to change, the anti-phase scanning that three input nand gate TN can export high potential to the 3rd phase inverter N3 input always is believed Number, the 3rd phase inverter N3 is exported the drive signal of low potential to drive signal output end Out1；Also, due to input signal end Signal current potential be low potential, i.e. Input=0, and with the interaction of the first clock signal terminal CK1 signal, can make Cascade signal output end Out2 exports the cascade signal of low potential always, until input signal end Input signal and first Untill when clock signal terminal CK1 signal is high potential again.

The shift register provided in the embodiment of the present invention one, can realize the defeated of scanning signal by simple structure Go out, so as to save cost.

Embodiment two,

By taking the shift register shown in Fig. 5 b as an example, Fig. 7 b are corresponding input and output sequential chart.Specifically, it is main to choose T1, T2 and T3 three phases in input and output sequential chart shown in Fig. 7 b.Scan control signal end CIN current potential is high electricity Position.

In T1 stages, Input=1, CK1=1, CK2=0, Re=1；Input=1, CK1=0, CK2=0, Re=afterwards 1.Wherein, due to Re=1, therefore reset transistor ends.And due to the addition of the 5th phase inverter N5 and hex inverter N6, The intensity enhancing of the signal of the 3rd phase inverter N3 outputs can be made.Remaining course of work with embodiment one the T1 stages it is worked Journey is essentially identical, is not described in detail here.

In T2 stages, Input=0, CK1=0, CK2=1, Re=1；Afterwards, Input=0, CK1=0, CK2=0, Re =1.Wherein, due to Re=1, therefore reset transistor ends.And due to the addition of the 5th phase inverter N5 and hex inverter N6, can make the intensity enhancing of the signal of the 3rd phase inverter N3 outputs.Remaining course of work and the work in T2 stages in embodiment one Make process essentially identical, be not described in detail here.

In T3 stages, Input=0, CK1=1, CK2=0, Re=0.Due to Re=0, therefore reset transistor M0 is turned on And the reference voltage end Vref of high potential signal is supplied to the second phase inverter N2 input, further make the second phase inverter N2 exports the cascade signal of low potential to cascade signal output end Out2.Afterwards, Input=0, CK1=0, CK2=0, Re=1, Due to Re=1, therefore reset transistor M0 ends.And, can be with due to the addition of the 5th phase inverter N5 and hex inverter N6 Make the intensity enhancing of the signal of the 3rd phase inverter N3 outputs.Remaining course of work and the course of work base in T3 stages in embodiment one This is identical, is not described in detail here.

After the T3 stages, due to Re=0, therefore reset transistor M0 ends.And due to the addition of the 5th phase inverter N5 and hex inverter N6, can make the intensity enhancing of the signal of the 3rd phase inverter N3 outputs.Remaining course of work and embodiment The course of work in one after the T3 stages is essentially identical, is not described in detail here.

The shift register provided in the embodiment of the present invention, can be with the basis of the shift register that embodiment one is provided By adding reset transistor, the 5th phase inverter and hex inverter, so that the working condition of shift register is more stable, And make the shock-absorbing capacity of the scanning signal of output preferable.

Below by taking the structure of the display panel shown in Fig. 2 c as an example, the timing diagram with reference to shown in Fig. 8, to the embodiment of the present invention The course of work of the display panel of offer is described.Wherein, in a vertical interval, in first half frame time S1, scan control Signal end CIN current potential is high potential；In later half frame time S2, scan control signal end CIN current potential is low potential.

Embodiment three,

As shown in Figure 2 c, including 2 shift register groups, i.e. the 1st register group 100_1 and the 2nd register group 100_2.

In first half frame time S1, each shift register SR (y) _ 1 correspondence receiving frame in the 1st register group 100_1 is tactile Signalling end STV signal, the first Clock control end CKV1 signal, second clock control end CKV2 signal and scanning Control signal end CIN signal, with sequential working.

The cascade signal of the cascade signal output end Out2 outputs of 1st grade of shift register SR (1) _ 1 is SR (1) _ 1- Out2.The cascade signal of the cascade signal output end Out2 outputs of 2nd grade of shift register SR (2) _ 1 is SR (2) _ 1-Out2. The cascade signal of 3rd level shift register SR (3) _ 1 cascade signal output end Out2 outputs is SR (3) _ 1-Out2.Remaining is moved The cascade signal of the cascade signal output end Out2 outputs of bit register SR (y) _ 1 by that analogy, is not described in detail here.So as to logical The effect of cascade signal is crossed, allows each shift register SR (y) _ 1 in the 1st register group 100_1 sequential working successively.

The drive signal that the drive signal output end Out1 of 1st grade of shift register SR (1) _ 1 is exported to grid line Gare_1 For SR (1) _ 1-Out1.The drive that the drive signal output end Out1 of 2nd grade of shift register SR (2) _ 1 is exported to grid line Gare_3 Dynamic signal is SR (2) _ 1-Out1.3rd level shift register SR (3) _ 1 drive signal output end Out1 is defeated to grid line Gare_5 The drive signal gone out is SR (3) _ 1-Out1.The drive signal output end Out1 of remaining shift register SR (y) _ 1 is strange to remaining The drive signal of several rows of grid line output by that analogy, is not described in detail here.It is defeated to the grid line of odd-numbered line successively so as to realize Enter the effect of drive signal.

Because scan control signal end CIN current potential is high potential, by the effect of anti-phase control module 200, the 2nd is set to post The drive signal of the drive signal output end Out1 outputs of each shift register SR (y) _ 2 in storage group 100_2 is low electricity Position.And the displacement latch module of each shift register SR (y) _ 2 can also may work, export cascade signal output end Out2 Cascade signal and corresponding shift register SR (y) _ 1 the cascade signals that export of cascade signal output end Out2 it is identical, should Part is not shown in fig. 8.

In later half frame time S2, each shift register SR (y) _ 2 correspondence receiving frames in the 2nd register group 100_2 are tactile Signalling end STV signal, the first Clock control end CKV1 signal, second clock control end CKV2 signal and scanning Control signal end CIN signal, with sequential working.

The cascade signal of the cascade signal output end Out2 outputs of 1st grade of shift register SR (1) _ 2 is SR (1) _ 2- Out2.The cascade signal of the cascade signal output end Out2 outputs of 2nd grade of shift register SR (2) _ 2 is SR (2) _ 2-Out2. The cascade signal of 3rd level shift register SR (3) _ 2 cascade signal output end Out2 outputs is SR (3) _ 2-Out2.Remaining is moved The cascade signal of the cascade signal output end Out2 outputs of bit register SR (y) _ 2 by that analogy, is not described in detail here.So as to logical The effect of cascade signal is crossed, allows each shift register SR (y) _ 2 in the 2nd register group 100_2 sequential working successively.

The drive signal that the drive signal output end Out1 of 1st grade of shift register SR (1) _ 2 is exported to grid line Gare_2 For SR (1) _ 2-Out1.The drive that the drive signal output end Out1 of 2nd grade of shift register SR (2) _ 2 is exported to grid line Gare_4 Dynamic signal is SR (2) _ 2-Out1.3rd level shift register SR (3) _ 2 drive signal output end Out1 is defeated to grid line Gare_6 The drive signal gone out is SR (3) _ 2-Out1.The drive signal output end Out1 of remaining shift register SR (y) _ 2 is to remaining idol The drive signal of several rows of grid line output by that analogy, is not described in detail here.It is defeated to the grid line of even number line successively so as to realize Enter the effect of drive signal.

Because scan control signal end CIN current potential is posted for each displacement in low potential, therefore the 1st register group 100_1 The drive signal of the drive signal output end Out1 outputs of storage SR (y) _ 1 is low potential.Each shift register SR (y) _ 1 Displacement latch module can also may work, the cascade signal and corresponding shift register for exporting cascade signal output end Out2 The cascade signal of the cascade signal output end Out2 outputs of SR (y) _ 2 is identical, and the part is not shown in fig. 8.

The display panel provided in the embodiment of the present invention three, is divided into 2 register groups, and lead to by all shift registers Scan control signal end CIN control is crossed, so as to realize interleaved drive pattern.

In addition, provided in an embodiment of the present invention when all shift registers are divided into 4 register groups, it is possible to achieve interval The pattern of 3 row grid lines scanning, principle and embodiment three are essentially identical, are not described in detail here.

It is provided in an embodiment of the present invention all shift registers are divided into 6 register groups when, it is possible to achieve interval 5 rows The pattern of grid line scanning, principle and embodiment three are essentially identical, are not described in detail here.When including 8,10 ... individual register group, The rest may be inferred, is not described in detail here.

Display panel provided in an embodiment of the present invention, can be in a vertical interval due to including 2N register group Make each register group sequential working, and due to each shift register correspondence connection interval 2N-1 rows in each register group Grid line, in a register group job, each shift register in the register group is by sequential working with to interval 2N-1 The effect that capable grid line is scanned successively.And each shift register can include：Shift latch module, control output module and Three modules of anti-phase output module, wherein, displacement latch module is used for what is exported at input signal end and the first clock signal terminal Under the co- controlling of signal, make cascade signal output end output cascade signal；Output module is controlled to be used in cascade signal, second Under the co- controlling of clock signal terminal and the signal of scan control signal end output anti-phase scanning is exported to anti-phase output module Signal；The anti-phase scanning signal progress anti-phase output that anti-phase output module is used for reception gives drive signal output end, therefore can By the mutual cooperation of these three modules, shift register can be made to realize the output of scanning signal.

Obviously, those skilled in the art can carry out the essence of various changes and modification without departing from the present invention to the present invention God and scope.So, if these modifications and variations of the present invention belong to the scope of the claims in the present invention and its equivalent technologies Within, then the present invention is also intended to comprising including these changes and modification.

Claims

1. a kind of display panel, including a plurality of grid line, insulated with the grid line and intersect a plurality of data lines of setting, by the grid line The multiple pixels limited with the data wire, the color of each pixel is identical in same row, and any data wire only with Connected with the pixel correspondence in a line, it is characterised in that the display panel also includes：2N register group, it is each described Register group includes the shift register of multiple cascades；Each shift register in the same register group passes through driving respectively Signal output part is connected with being spaced the grid line of 2N-1 rows, and the different grid line of each register group correspondence, and N is just whole Number；In pixel described in same row, belong to the corresponding pixel connection identical data wire of shift register of same register group, And the data wire different from the connection of another half-pix of the half-pix in pixel described in same row；

In the same register group, the input signal end of first order shift register is connected with frame start signal end, and remaining is each The cascade signal output end of the input signal end of individual shift register respectively with shift register described in respective adjacent upper level It is connected；

The shift register includes：Shift latch module, control output module and anti-phase output module；Wherein, it is described to move Position latch module respectively with the input signal end of the shift register, cascade signal output end and the first clock signal terminal phase Even, under the co- controlling for the signal that the input signal end and first clock signal terminal are exported, making the cascade Signal output part output cascade signal；It is described control output module respectively with the cascade signal output end, second clock signal End, scan control signal end and the anti-phase output module are connected, in the cascade signal, the second clock signal Under the co- controlling of the signal of end and the output of scan control signal end anti-phase scanning signal is exported to the anti-phase output module； The anti-phase output module is connected with the drive signal output end of the shift register, for the anti-phase scanning signal to reception Anti-phase output is carried out to the drive signal output end.

2. display panel as claimed in claim 1, it is characterised in that the displacement latch module includes：First phase inverter, Two phase inverters, the first tri-state NAND gate, the second tri-state NAND gate；Wherein,

The input of first phase inverter is connected with first clock signal terminal, the output end of first phase inverter and institute The first control end for stating the first tri-state NAND gate is connected；

The input of the first tri-state NAND gate is connected with the input signal end, the second control of the first tri-state NAND gate End processed is connected with first clock signal terminal, the output end of the first tri-state NAND gate and the input of second phase inverter End is connected；

First control end of the second tri-state NAND gate is connected with first clock signal terminal, the second tri-state NAND gate Input be connected with the cascade signal output end, the second control end of the second tri-state NAND gate and described first anti-phase The output end of device is connected, and the output end of the second tri-state NAND gate is connected with the input of second phase inverter.

3. display panel as claimed in claim 2, it is characterised in that the shift register also includes：Reset transistor；Its In, the control pole of the reset transistor is connected with reset signal end, and the first pole is connected with reference signal end, the second pole with it is described The input of second phase inverter is connected.

4. display panel as claimed in claim 1, it is characterised in that the control output module includes：Three input nand gates； Wherein,

The first input end of three input nand gate is connected with the cascade signal output end, the second input and described second Clock signal terminal is connected, and the 3rd input is connected with the scan control signal end, output end and the anti-phase output module phase Even.

5. display panel as claimed in claim 1, it is characterised in that the anti-phase output module includes：3rd phase inverter；Its Described in the 3rd phase inverter input with it is described control output module be connected, output end and corresponding drive signal output end phase Even.

6. display panel as claimed in claim 1, it is characterised in that N=1, the scan control signal end includes：First sweeps Retouch control signal end and the second scan control signal end；Wherein, each shift register connection described first in the 1st register group Each shift register in scan control signal end, the 2nd register group connects the second scan control signal end.

7. each shift register in display panel as claimed in claim 1, it is characterised in that N=1, the 1st register group connects Connect the scan control signal end；

The display panel also includes：Each shift register in anti-phase control module, the 2nd register group passes through described anti- Phase control module is connected with the scan control signal end.

8. display panel as claimed in claim 7, it is characterised in that at least two adjacent shiftings in the 2nd register group Bit register is connected by same anti-phase control module with the scan control signal end；Or,

Each shift register passes through one-to-one anti-phase control module and the scan control in the 2nd register group Signal end is connected.

9. display panel as claimed in claim 7, it is characterised in that the anti-phase control module includes：4th phase inverter；Its In, the input of the 4th phase inverter is connected with the scan control signal end, output end and corresponding shift register phase Even.

10. display panel as claimed in claim 1, it is characterised in that the display panel also includes：With each data wire The source electrode drive circuit of connection；Wherein,

When the display panel shows pure color picture, each shift register working time in each register group Interior, the same colored pixels that the source electrode drive circuit is used in multiple pixels only for each grid line connection of scanning are connected Data wire loading data-signal；Wherein, the polarity of the data-signal loaded on the same data wire is identical；

When the display panel shows colour picture, each shift register working time in each register group Interior, the source electrode drive circuit is used for the data-signal to loading opposed polarity per adjacent two data line；Wherein, it is same described The polarity of the data-signal loaded on data wire is identical.

11. the display panel as described in claim any one of 1-10, it is characterised in that each shift register is included to be set respectively It is placed in the left side shift register and right side shift register at same grid line two ends；And worked in each shift register When, left side shift register and right side shift register positioned at same grid line both sides work simultaneously.