CN106992178A - Memory component and its manufacture method - Google Patents
Memory component and its manufacture method Download PDFInfo
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- CN106992178A CN106992178A CN201610033445.9A CN201610033445A CN106992178A CN 106992178 A CN106992178 A CN 106992178A CN 201610033445 A CN201610033445 A CN 201610033445A CN 106992178 A CN106992178 A CN 106992178A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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Abstract
The present invention provides a kind of memory component and its manufacture method, wherein, memory component includes：Substrate, at least two stacked structures, conductor structure and sunk structure.Stacked structure is located on substrate.Conductor structure is located between stacked structure.Sunk structure is located on conductor structure.Top surface of the bottom surface of sunk structure at least below stacked structure.Therefore, the present invention can solve the problem of word line leakage, bitline short circuits and high-temperature data keep not good, can reduce process costs and lift product yield.
Description
Technical field
The present invention relates to a kind of semiconductor element and its manufacture method, more particularly to a kind of memory component and
Its manufacture method.
Background technology
As science and technology is maked rapid progress, improve the integration of memory component and reduce critical size already gradually
As a kind of trend.Under this trend, memory component often meet with word line leakage (WL leakage),
Bitline short circuits (BL short) and high-temperature data keep (high-temperature data retention,
HTDR) not good the problem of.
For example, as shown in figure 1, between wordline 12 formed source configuration 34 when, due to source electrode
The top critical size of structure 34 is more than its bottom critical dimension, and it causes the side wall of source configuration 34 to hold
Easily form wedge angle 10.The tip of the wedge angle 10 is protruded toward the direction of wordline 12, and it easily produces leakage current,
And then cause word line leakage problem to produce.In addition, titanium residual or gold on dielectric layer between bit line
The problem of category oxide particle is also easily caused bitline short circuits.
The content of the invention
The present invention provides a kind of memory component and its manufacture method with sunk structure, and it can solve word
The problem of line electric leakage, bitline short circuits and high-temperature data keep not good.
The present invention provides a kind of memory component and its manufacture method with sunk structure, and it can reduce work
Skill cost simultaneously lifts product yield.
The present invention, which provides a kind of memory component, to be included：Substrate, at least two stacked structures, conductor structure
And sunk structure.Stacked structure is located on substrate.Conductor structure is located between stacked structure.Depression knot
Structure is located on conductor structure.Top surface of the bottom surface of sunk structure at least below stacked structure.
In one embodiment of this invention, the top surface of the sunk structure to the thickness of bottom surface between 80nm
To between 120nm.
In one embodiment of this invention, the memory component, in addition to：Two cap layers and
Gap wall.Cap layer is located on stacked structure respectively.Clearance wall is located between stacked structure and conductor structure..
In one embodiment of this invention, the top surface of the top surface of the sunk structure and cap layer is copline.
In one embodiment of this invention, the sunk structure at least exposes the surface of clearance wall.
In one embodiment of this invention, the thickness of each cap layer between 30nm between 70nm.
In one embodiment of this invention, each stacked structure sequentially includes tunneling dielectric layer, floating grid
Dielectric layer, control gate and dielectric layer between pole, grid.
In one embodiment of this invention, the bottom surface of sunk structure is higher than the top surface of control gate.
In one embodiment of this invention, the sunk structure is shaped as semicircle, rectangle or its combination.
In one embodiment of this invention, the sunk structure includes single layer structure, double-layer structure or multilayer
Structure.
In one embodiment of this invention, the material of the sunk structure include silicon nitride, silica or its
Combination.
In one embodiment of this invention, the conductor structure is source configuration.
In one embodiment of this invention, the memory component also includes metal interconnecting, positioned at depression
In structure.
The present invention provides a kind of manufacture method of memory component, and its step is as follows.In formed on substrate to
Few two stacked structures.In two cap layers are formed on stacked structure respectively.Formed between stacked structure
Conductor structure.Clearance wall is formed between stacked structure and conductor structure.It is recessed in being formed on conductor structure
Structure.Top surface of the bottom surface of sunk structure at least below stacked structure.
In one embodiment of this invention, the step of forming the conductor structure is as follows.In formation on substrate
Conductor material layer.Space and the surface of covering cap layer that conductor material layer is inserted between stacked structure.Enter
Row flatening process, to remove part conductor material layer and part cap layer.
In one embodiment of this invention, the flatening process includes cmp (CMP) work
Skill, etch back process or its combination.
In one embodiment of this invention, the step of forming the sunk structure is as follows.In formation on substrate
Patterned mask layer.Patterned mask layer has opening.Opening at least exposes the top surface of conductor structure.Enter
Row etch process, removes part conductor structure and part cap layer, to form recessed openings.Recessed openings
At least expose the surface of clearance wall.Form an at least dielectric materials layer and insert in recessed openings.
The present invention separately provides a kind of manufacture method of memory component, and its step is as follows.In formation on substrate
Multiple conductor structures.Multiple dielectric layers are formed between conductor structure.In shape on conductor structure and dielectric layer
Into metal level.In forming patterned mask layer on metal level.Patterned mask layer has multiple openings.Open
Mouth corresponds to the top surface of dielectric layer respectively.The layer by curtain of patterned mask layer, removes part of dielectric layer so that
The top surface of dielectric layer is less than the top surface of conductor structure.
In one embodiment of this invention, between the top surface of the dielectric layer and the top surface of conductor structure away from
From between 10nm between 40nm.
In one embodiment of this invention, the conductor structure is bit line.
Based on above-mentioned, the present invention is by the sunk structure in source configuration, and it can be removed of the prior art
Wedge angle, to solve the problems, such as word line leakage.In addition, in the present invention, sunk structure in source configuration with
Cap layer in wordline can increase high-temperature data and keep (HTDR) ability, and and then lifting yield.This
Outside, the present invention removes the processing step of contact hole of the prior art, and it can be not only solved between bit line
Caused by titanium residual on dielectric layer the problem of bitline short circuits, process costs can be also reduced.
For the features described above and advantage of the present invention can be become apparent, special embodiment below, and coordinate
Accompanying drawing is described in detail below.
Brief description of the drawings
Fig. 1 is a kind of diagrammatic cross-section of existing memory component；
Fig. 2A to Fig. 2 J is the section of the manufacturing process of the memory component according to first embodiment of the invention
Schematic diagram；
Fig. 3 A to Fig. 3 B are the sections of the manufacturing process of the memory component according to second embodiment of the invention
Schematic diagram.
Description of reference numerals：
10：Wedge angle；
12：Wordline；
34：Source configuration；
100：Substrate；
101：Isolation structure；
102：Stacked structure；
104：Tunneling dielectric layer；
106：Floating grid；
108：Dielectric layer between grid；
110：First control gate；
112：Second control gate；
114、116、126c、126d：Dielectric layer；
118、118a：Clearance wall；
120、120a、124、124a、136、136a：Oxide layer；
122、122a：Nitration case；
126、126a、126b：Cap layer；
128、128a：Barrier layer；
130：Conductor material layer；
132：Drain electrode structure, conductor structure；
134：Source configuration, conductor structure；
134a：Source configuration；
138、158a：Patterned mask layer；
140、160：Opening；
142：Recessed openings；
144、144a、146、146b：Dielectric materials layer；
145：Sunk structure；
148：Depression；
150、150a、154、154a：Conductor layer；
152、152a：Metal level；
156、158：Mask layer；
162：Protuberance；
CT：Contact hole；
D：Depth；
H：Distance；
M1：Metal interconnecting；
T1、T2：Thickness；
W：Width；
AA：Active area.
Embodiment
With reference to the accompanying drawing of the present embodiment more fully to illustrate the present invention.However, the present invention can also be various
Different forms embodies, and should not necessarily be limited by embodiments described herein.The thickness of layer and region in accompanying drawing
Degree can for the sake of clarity amplify.Same or analogous reference represents same or analogous element,
Paragraphs below will be repeated no longer one by one.
Fig. 2A to Fig. 2 J is the section of the manufacturing process of the memory component according to first embodiment of the invention
Schematic diagram.
Fig. 2A is refer to, the first embodiment of the present invention provides a kind of manufacture method of memory component, its
Step is as follows.There is provided substrate 100 first.In the present embodiment, substrate 100 may be, for example, semiconductor
There is Semiconductor substrate (SOI) on substrate, semiconducting compound substrate or insulating barrier.
Then, in forming multiple stacked structures 102 on substrate 100.In detail, stacked structure 102
Dielectric layer 108, the first control gate 110, between tunneling dielectric layer 104, floating grid 106, grid
Two control gates 112 and dielectric layer 114,116 are sequentially stacked and formed.In the present embodiment, it is tunneling to be situated between
The material of electric layer 104 can be for example silica, and its forming method can be chemical vapour deposition technique, hot oxygen
Change method etc..The material of floating grid 106 can be for example DOPOS doped polycrystalline silicon, un-doped polysilicon or its combination,
Its forming method can be chemical vapour deposition technique.Dielectric layer 108 can be for example by oxide layer/nitridation between grid
The composite bed that layer/oxide layer (Oxide/Nitride/Oxide, ONO) is constituted, this composite bed can be three layers
Or more layer, the present invention is not limited thereto, and its forming method can be for example chemical vapour deposition technique.First
The material of control gate 110 can be for example DOPOS doped polycrystalline silicon, un-doped polysilicon or its combination, and it is formed
Method can be chemical vapour deposition technique.The material of second control gate 112 can be for example metal silicide,
The metal silicide can be for example tungsten silicide (WSix), its forming method can be chemical vapor deposition
Method.Dielectric layer 114,116 can be for example single layer structure, double-decker or sandwich construction.In the present embodiment
In, the material of dielectric layer 114 can be for example silicon nitride；The material of dielectric layer 116 can be for example silica,
Tetraethoxysilane (TEOS) oxide or its combination.The forming method of dielectric layer 114,116 can be with
It is chemical vapour deposition technique.
Afterwards, clearance wall 118 is formed in the both sides of stacked structure 102.In detail, clearance wall 118
It can be for example single layer structure, double-decker or sandwich construction.In the present embodiment, clearance wall 118 can example
Three-decker in this way, it can be sequentially oxide layer 120, nitridation to extend outward from the inner side of stacked structure 102
Layer 122 and oxide layer 124.The material of oxide layer 120 can be for example high-temperature oxide (HTO)；
The material of nitration case 122 can be for example silicon nitride；The material of oxide layer 124 can be for example tetraethoxy-silicane
Alkane (TEOS) oxide.The forming method of oxide layer 120, nitration case 122 and oxide layer 124 is
It is known to one of skill in the art, just no longer it is described in detail in this.
Then, cap layer 126 is formed respectively on stacked structure 102.The material of cap layer 126 can example
Silicon nitride, oxide or its combination in this way, its forming method can be chemical vapour deposition technique.
Then, it is conformally formed barrier layer 128 on stacked structure 102 and cap layer 126.Barrier layer 128
Material can be for example titanium (Ti), titanium nitride (TiN) or its combination, its forming method can be chemistry
Vapour deposition process, physical vaporous deposition or atomic layer deposition method (ALD).
Afterwards, in formation conductor material layer 130 on substrate 100.Conductor material layer 130 inserts stacking knot
The surface in space and covering stacked structure 102 and cap layer 126 between structure 102.Conductor material layer 130
Material can be for example tungsten (W), its forming method can be physical vaporous deposition.
Fig. 2A and Fig. 2 B are refer to, flatening process is carried out, part conductor material layer 130, portion is removed
Divide barrier layer 128 and part cap layer 126, to form conductor knot respectively between stacked structure 102
Structure 132,134.In one embodiment, the flatening process can be for example chemical mechanical milling tech,
Etch back process or its combination.In the present embodiment, it can be lost by adjusting crossing for chemical mechanical milling tech
Step is carved, to control cap layer 126a thickness.When the thickness for the cap layer 126a being made up of silicon nitride
Degree is thicker, and the high-temperature data holding capacity of affiliated memory component is better.In one embodiment, cap layer
126a thickness T1 can be between 30nm between 70nm.
It is worth noting that, in the present embodiment, conductor structure 132 can be considered drain electrode structure (hereinafter referred to as
Be drain electrode structure 132)；And conductor structure 134 can be considered source configuration (hereinafter referred to as source junction
Structure 134).Although Fig. 2A does not show that the layout of drain electrode structure 132 and source configuration 134, from upper
From the point of view of apparent direction, drain electrode structure 132 can for example multiple column structures, along perpendicular to the direction of paper arrange
Row.From the point of view of upper apparent direction, source configuration 134 can be for example laminated structure, along perpendicular to paper
Direction extends, and wherein source configuration 134 is mutually arranged with drain electrode structure 132 along the direction parallel to paper
Row.In the present embodiment, 1 laminated structure of correspondence of drain electrode structure 132 of every 128 column structures
Source configuration 134.There is the source of 1 column structure between the source configuration 134 of each two laminated structure
Pole structure 134, to be electrically connected in follow-up metal interconnecting.On the other hand, conductor knot
Structure 132 can be considered bit line (Bit Line)；And stacked structure 102 then can be considered wordline (Word Line).
Fig. 2 B and Fig. 2 C are refer to, in sequentially forming oxide layer 136 and patterned mask on substrate 100
Layer 138.Patterned mask layer 138 has opening 140.Opening 140 at least exposes source configuration 134
Top surface.In one embodiment, the width W of opening 140 can be exposed by the critical size of lithographic exposure bench
Light ability is adjusted.It was found from Fig. 2 C, this width W is also greater than the top surface of source configuration 134
Width.In one embodiment, the material of patterned mask layer 138 can be for example photoresist or compare
There is the material of high degree of etch selection ratio in oxide layer 136.The forming method of patterned mask layer 138 can
E.g. method of spin coating or chemical vapour deposition technique.
Fig. 2 C and Fig. 2 D are refer to, is mask with patterned mask layer 138, technique is etched, moved
Except portion of oxide layer 136, part source configuration 134 and part cap layer 126a, to form recessed openings
142.In one embodiment, etch process can be for example dry etch process, and the dry etch process can
To be reactive ion-etching (Reactive Ion Etching, RIE).In detail, recessed openings
142 are located at the lower section of opening 140, and recessed openings 142 at least expose clearance wall 118a (or nitration cases
Surface 122a).The bottom surface of recessed openings 142 can at least below stacked structure 102 top surface；It is another
Aspect, the bottom surface of recessed openings 142 can also be higher than the top surface of the second control gate 112.In an embodiment
In, the depth D of this recessed openings 142 is (i.e. from cap layer 126b top surface to the bottom of recessed openings 142
The distance between face) can be between 80nm between 120nm.In one embodiment, recessed openings 142
Shape can be for example semicircle, rectangle or its combination.It is worth noting that, in the present embodiment, it is recessed
Fall into opening 142 and wedge angle 10 (as shown in Figure 1) of the prior art can be removed, asked with solving word line leakage
Topic.
Fig. 2 E and Fig. 2 F are refer to, after patterned mask layer 138 is removed, in common on substrate 100
Shape formation dielectric materials layer 144, and covering recessed openings 142 and oxide layer 136a surface.It is real one
Apply in example, dielectric materials layer 144 can be for example silicon nitride, its thickness can be for exampleExtremely
Between.The forming method of dielectric materials layer 144 can be chemical vapour deposition technique or atomic layer deposition method
(ALD).Afterwards, in formation dielectric materials layer 146 on dielectric materials layer 144.In one embodiment,
Dielectric materials layer 146 can be for example silica, TEOS silica, spin-coating silica (Spin-on silicon
Oxide), silicon nitride or its combination, its thickness can be for exampleExtremelyBetween.Dielectric material
The forming method of the bed of material 146 can be chemical vapour deposition technique.Incidentally, due to dielectric material
Layer 146 is inserted in recessed openings 142 so that dielectric materials layer 146 corresponds to the top of recessed openings 142
Surface on have depression 148.
Fig. 2 F and Fig. 2 G are refer to, flatening process is carried out, part dielectric materials layer 146 is removed, with
Expose the surface of dielectric materials layer 144.In one embodiment, can be for example of flatening process
Learn mechanical milling tech, etch back process or its combination.
Fig. 2 H and Fig. 2 I are refer to, the first etching step is carried out, part dielectric materials layer 144,146a is removed,
To expose oxide layer 136a surface.In one embodiment, the first etching step can be for example dry type erosion
The etching selectivity of lithography, its oxide and nitride is about 1：1.Then, the second etching step is carried out,
Oxide layer 136a is removed, to expose cap layer 126b surface.In one embodiment, the second etching step
Suddenly dry etching method is can be for example, the etching selectivity of its oxide and nitride is about 3：1.
It is worth noting that, dielectric materials layer 144a, 146b for inserting in recessed openings 142 can be considered recessed
Fall into structure 145.Although the not shown source configuration 134a of Fig. 2 I layout, recessed from the point of view of upper apparent direction
Sunken structure 145 is also similar to source configuration 134a, and it can be for example list structure, and it is located at laminated structure
Source configuration 134a on, and along perpendicular to the direction of paper extend.Because sunk structure 145 is located at
On source configuration 134a between adjacent stacked structure 102, its adjacent stacked structure that can be electrically insulated
102, to solve the problems, such as word line leakage.In addition, the dielectric materials layer 144a of sunk structure 145 can be such as
It is silicon nitride, it can increase high-temperature data and keep (HTDR) ability, and and then lifting yield.
Refer to Fig. 2 I and Fig. 2 J, in sequentially formed on sunk structure 145 conductor layer 150, metal level 152,
Conductor layer 154 and mask layer 156,158.In one embodiment, conductor layer 150, metal level 152
And conductor layer 154 can be for example metal interconnecting.In detail, the material of conductor layer 150 can be such as
It is titanium (Ti), its forming method can be physical vaporous deposition.The material of metal level 152 can be such as
It is aluminium, copper or its combination, its forming method can be physical vaporous deposition.The material of conductor layer 154
Titanium (Ti), titanium nitride (TiN) or its combination are can be for example, its forming method can be that physical vapor is sunk
Area method or chemical vapour deposition technique.The material of mask layer 156,158 can be for example silicon oxynitride, photoresistance material
Material or its combination, its forming method can be chemical vapour deposition technique.
Fig. 2 J are gone back to, first embodiment of the invention, which provides a kind of memory component, to be included：Substrate 100,
Multiple stacked structures 102, clearance wall 118a, cap layer 126b, drain electrode structure 132, source configuration 134a
And sunk structure 145.Stacked structure 102 is located on substrate 100.Drain electrode structure 132, source configuration
134a is located between stacked structure 102 respectively.In other words, drain electrode structure 132 and source configuration 134a
Between have stacked structure 102.Sunk structure 145 is located on source configuration 134a.Sunk structure 145
Top surface of the bottom surface at least below stacked structure 102, and sunk structure 145 bottom surface also can be higher than second
The top surface of control gate 112.In one embodiment, the thickness T2 of sunk structure 145 can be between 80nm
To between 120nm, the top surface of the wherein top surface of sunk structure 145 and cap layer 126b is copline.
In addition, the memory component of the present embodiment also includes conductor layer 150, metal level 152 and conductor layer 154
(can be for example metal interconnecting) is located on sunk structure 145.
Fig. 3 A to Fig. 3 B are the sections of the manufacturing process of the memory component according to second embodiment of the invention
Schematic diagram.
Fig. 3 A and Fig. 3 B are refer to, the method according to above-described embodiment is carried out to the mask layer for forming Fig. 2 J
156、158.To simplify accompanying drawing, in Fig. 3 A to Fig. 3 B, only it is showing along perpendicular to the direction of paper
The diagrammatic cross-section of Fig. 2 J drain electrode structure 132, and not shown Fig. 2 J stacked structure 102 and source electrode
Structure 134a.On this section, there are multiple isolation structures 101 in substrate 100.Adjacent isolation structures
Substrate 100 between 101 can be considered active area AA.In one embodiment, the material of isolation structure 101
It can be for example doped or undoped silica, high density plasma oxide, silicon oxynitride, spin-coating oxygen
SiClx (Spin-on silicon oxide), low dielectric constant dielectric materials (Low-k dielectric) or its
Combination.Isolation structure 101 can be for example shallow slot isolation structure.
Drain electrode structure 132 is located on active area AA respectively.There is dielectric layer between drain electrode structure 132
126c.In the present embodiment, dielectric layer 126c is formed simultaneously with Fig. 2A cap layer 126.Due to
Drain electrode structure 132, dielectric layer 126c material, forming method illustrated in above-mentioned paragraph, in this just
Repeat no more.
It refer to Fig. 2 J and Fig. 3 A, conductor layer 150, metal level 152, conductor layer 154 and mask layer
156th, 158 it is sequentially formed at from bottom to up on dielectric layer 126c and drain electrode structure 132.Then, pattern
The mask layer 158, to form multiple openings 160.Opening 160 corresponds to dielectric layer 126c top surface.
Ground it is worth noting that, being remained in the chemical mechanical milling tech for carrying out above-mentioned Fig. 2 F to Fig. 2 I
Easily accumulation is on dielectric layer 126c top surface for the particle or metal oxide particle of grinding fluid, so entering
After row subsequent deposition process so that part of dielectric layer 126c, part conductor layer 150, partial metal layers 152,
The protrusion of part conductor layer 154 and part mask layer 156, and protuberance 162 is formed (such as Fig. 3 A institutes
Show).
Afterwards, Fig. 3 A and Fig. 3 B are refer to, layer, is etched work by curtain of patterned mask layer 158a
Skill, to remove part mask layer 156, part conductor layer 154, partial metal layers 152, part conductor layer
150 and part of dielectric layer 126c so that dielectric layer 126d top surface is less than the top surface of drain electrode structure 132.
In one embodiment, the distance between top surface of dielectric layer 126d top surface and drain electrode structure 132 is (or high
Degree is poor) H can be between 10nm between 40nm.In one embodiment, etch process can be for example dry
Formula etch process.As shown in Figure 3 B, conductor layer 150a, metal level 152a and conductor layer 154a can
E.g. metal interconnecting M1.In other words, the drain electrode structure 132 of the present embodiment is and metal interconnecting
M1 is directly contacted, and between drain electrode structure 132 and metal interconnecting M1 and without contact hole or its class
Like structure.
In the present embodiment, it can be removed by overetch (over etching) step in etch process
The protuberance 162.Consequently, it is possible to which the present embodiment can solve conductor layer 150 by above-mentioned overetch step
The problem of drain electrode structure 132 (bit line) caused by (titanium) residual is short-circuit.
In addition, contact hole CT of the prior art processing step can be removed in the present embodiment, it not only may be used
The conductor layer 150 (titanium) solved on the dielectric layer 126d between drain electrode structure 132 (bit line) is residual
Caused by staying the problem of bitline short circuits, it can also reduce process costs and increase yield.
In summary, the present invention is by the sunk structure in source configuration, and it can be removed of the prior art
Wedge angle, to solve the problems, such as word line leakage.In addition, in the present invention, sunk structure in source configuration with
Cap layer in wordline can increase high-temperature data holding capacity, and and then lifting yield.In addition, of the invention
The processing step of contact hole of the prior art is removed, it can be not only solved on the dielectric layer between bit line
Caused by titanium residual the problem of bitline short circuits, process costs can be also reduced.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than right
It is limited；Although the present invention is described in detail with reference to foregoing embodiments, this area it is common
Technical staff should be understood：It can still modify to the technical scheme described in foregoing embodiments,
Or equivalent substitution is carried out to which part or all technical characteristic；And these modifications or replacement, and
The essence of appropriate technical solution is not set to depart from the scope of various embodiments of the present invention technical scheme.
Claims (20)
1. a kind of memory component, it is characterised in that including：
At least two stacked structures, on substrate；
Conductor structure, between at least two stacked structure；And
Sunk structure, on the conductor structure, wherein the bottom surface of the sunk structure is at least below institute
State the top surface of at least two stacked structures.
2. memory component according to claim 1, it is characterised in that the top of the sunk structure
The thickness of face to the bottom surface is between 80nm between 120nm.
3. memory component according to claim 1, it is characterised in that also include：
Two cap layers, respectively at least two stacked structure；
Clearance wall, between at least two stacked structure and the conductor structure.
4. memory component according to claim 3, it is characterised in that the top of the sunk structure
The top surface of face and described two cap layers is copline.
5. memory component according to claim 3, it is characterised in that the sunk structure is at least
Expose the surface of the clearance wall.
6. memory component according to claim 3, it is characterised in that the thickness of each cap layer
Degree is between 30nm between 70nm.
7. memory component according to claim 1, it is characterised in that each stacked structure according to
Sequence includes dielectric layer, control gate and dielectric layer between tunneling dielectric layer, floating grid, grid.
8. memory component according to claim 7, it is characterised in that the institute of the sunk structure
State the top surface that bottom surface is higher than the control gate.
9. memory component according to claim 1, it is characterised in that the shape of the sunk structure
Shape is semicircle, rectangle or its combination.
10. memory component according to claim 1, it is characterised in that the sunk structure includes
Single layer structure, double-layer structure or sandwich construction.
11. memory component according to claim 1, it is characterised in that the material of the sunk structure
Material includes silicon nitride, silica or its combination.
12. memory component according to claim 1, it is characterised in that the conductor structure is source
Pole structure.
13. memory component according to claim 1, it is characterised in that also including metal interconnecting,
On the sunk structure.
14. a kind of manufacture method of memory component, it is characterised in that including：
In forming at least two stacked structures on substrate；
In two cap layers are formed at least two stacked structure respectively；
Conductor structure is formed between at least two stacked structure；
Clearance wall is formed between at least two stacked structure and the conductor structure；And
In forming sunk structure on the conductor structure, wherein the bottom surface of the sunk structure is at least below institute
State the top surface of at least two stacked structures.
15. the manufacture method of memory component according to claim 14, it is characterised in that formed
The step of conductor structure, includes：
In forming conductor material layer on the substrate, the conductor material layer inserts at least two stacking
The surface in space and the described two cap layers of covering between structure；And
Flatening process is carried out, to remove the part conductor material layer and the described two cap layers in part.
16. the manufacture method of memory component according to claim 15, it is characterised in that described
Flatening process includes chemical mechanical milling tech, etch back process or its combination.
17. the manufacture method of memory component according to claim 14, it is characterised in that formed
The step of sunk structure, includes：
In forming patterned mask layer on the substrate, the patterned mask layer has opening, described to open
Mouth at least exposes the top surface of the conductor structure；
Technique is etched, the part conductor structure and the described two cap layers in part are removed, to be formed
Recessed openings, the recessed openings at least expose the surface of the clearance wall；And
Form an at least dielectric materials layer and insert in the recessed openings.
18. a kind of manufacture method of memory component, it is characterised in that including：
In forming multiple conductor structures on substrate；
Multiple dielectric layers are formed between the multiple conductor structure；
In the multiple conductor structure with forming metal level on the multiple dielectric layer；
In forming patterned mask layer on the metal level, the patterned mask layer has multiple openings,
The multiple opening corresponds to the top surface of the multiple dielectric layer respectively；And
The layer by curtain of the patterned mask layer, removes the multiple dielectric layer in part so that the multiple
The top surface of dielectric layer is less than the top surface of the multiple conductor structure.
19. the manufacture method of memory component according to claim 18, it is characterised in that described
The distance between the top surface of multiple dielectric layers and the top surface of the multiple conductor structure are between 10
Nm is between 40nm.
20. the manufacture method of memory component according to claim 18, it is characterised in that described
Multiple conductor structures are bit line.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610033445.9A CN106992178B (en) | 2016-01-19 | 2016-01-19 | Memory element and manufacturing method thereof |
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| CN201610033445.9A CN106992178B (en) | 2016-01-19 | 2016-01-19 | Memory element and manufacturing method thereof |
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| CN106992178A true CN106992178A (en) | 2017-07-28 |
| CN106992178B CN106992178B (en) | 2020-07-14 |
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| CN113782490A (en) * | 2021-08-31 | 2021-12-10 | 上海华力集成电路制造有限公司 | Preparation method of flash memory device |
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| CN104377202A (en) * | 2013-08-12 | 2015-02-25 | 华邦电子股份有限公司 | Embedded storage component and manufacturing method thereof |
| US20150187781A1 (en) * | 2013-12-30 | 2015-07-02 | Semiconductor Manufacturing International (Shanghai) Corporation | Memory device and method for forming the same |
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| CN104377202A (en) * | 2013-08-12 | 2015-02-25 | 华邦电子股份有限公司 | Embedded storage component and manufacturing method thereof |
| US20150187781A1 (en) * | 2013-12-30 | 2015-07-02 | Semiconductor Manufacturing International (Shanghai) Corporation | Memory device and method for forming the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113782490A (en) * | 2021-08-31 | 2021-12-10 | 上海华力集成电路制造有限公司 | Preparation method of flash memory device |
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