CN106992123A - Lateral diffusion metal oxide semiconductor element and manufacturing method thereof - Google Patents
Lateral diffusion metal oxide semiconductor element and manufacturing method thereof Download PDFInfo
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- CN106992123A CN106992123A CN201610079339.4A CN201610079339A CN106992123A CN 106992123 A CN106992123 A CN 106992123A CN 201610079339 A CN201610079339 A CN 201610079339A CN 106992123 A CN106992123 A CN 106992123A
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- semiconductor element
- oxide semiconductor
- grid structure
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 52
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 32
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 32
- 238000009792 diffusion process Methods 0.000 title abstract description 36
- 239000004020 conductor Substances 0.000 claims abstract description 101
- 239000000758 substrate Substances 0.000 claims abstract description 94
- 238000000034 method Methods 0.000 claims description 56
- 239000000463 material Substances 0.000 claims description 43
- 238000002955 isolation Methods 0.000 claims description 38
- 239000011248 coating agent Substances 0.000 claims description 23
- 238000000576 coating method Methods 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000007769 metal material Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000000059 patterning Methods 0.000 abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 22
- 150000002500 ions Chemical class 0.000 description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 239000011159 matrix material Substances 0.000 description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 238000004380 ashing Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a lateral diffusion metal oxide semiconductor element and a manufacturing method thereof, wherein the manufacturing method of the lateral diffusion metal oxide semiconductor element comprises the following steps: a substrate is provided, on which a dielectric layer, a first conductive layer, an adhesion layer and a second conductive layer are sequentially formed. And patterning the second conductor layer to form a conductor structure. A first trench is formed in the first conductive layer and the dielectric layer on one side of the conductive structure. And removing the exposed part of the substrate of the first conductor layer and the first groove by taking the conductor structure as a mask so as to form a gate structure and a second groove. A first well region of a first conductivity type is formed in the substrate at one side of the gate structure. And forming a second well region of the second conductivity type in the substrate on the other side of the gate structure. And forming a gap wall on the side wall of the grid structure, wherein the gap wall fills the second groove. And forming a drain region and a source region in the substrate at two sides of the gate structure.
Description
Technical field
The present invention relates to a kind of semiconductor element and its manufacture method, and more particularly to a kind of horizontal proliferation
Metal-oxide-semiconductor element and its manufacture method.
Background technology
Lateral diffusion metal-oxide-semiconductor (laterally diffused metal oxide semiconductor,
LDMOS) element is a kind of typical high voltage device, and it can be whole with CMOS manufacture craft
Close, thus manufacture control, logic and power switch on one chip.LDMOS elements are in operation
Shi Bixu has high-breakdown-voltage (breakdown voltage) and low opening resistor (on-state
Resistance, Ron).LDMOS elements with high-breakdown-voltage and low opening resistor should in high pressure
Used time has relatively low power attenuation.In addition, relatively low opening resistor can then cause transistor in saturation
Thus increase the service speed of element during state with higher drain current.
However, the breakdown voltage of current ldmos transistor can not further up and opening resistor
Can not further it decline, to obtain more preferably element characteristic.Therefore pole needs one kind to have high-breakdown-voltage at present
And/or the ldmos transistor of low opening resistor, to lift the element characteristic of ldmos transistor.
The content of the invention
It is an object of the invention to provide a kind of manufacture method of lateral diffusion metal-oxide-semiconductor element, it can make
The lateral diffusion metal-oxide-semiconductor element with high-breakdown-voltage and/or low opening resistor is made, and makes work
Skill is easy.
Another object of the present invention is to provide a kind of lateral diffusion metal-oxide-semiconductor element, puncture with height
Voltage and/or low opening resistor.
For up to above-mentioned purpose, the manufacture method of lateral diffusion metal-oxide-semiconductor element of the invention, its step
It is as follows.Substrate is provided, dielectric layer, the first conductor layer, adhesion coating and the have been sequentially formed in substrate
Two conductor layers.The second conductor layer is patterned, to form conductor structure.In the first side of conductor structure
One conductor layer in dielectric layer with forming first groove.Using conductor structure as mask, the first conductor layer is removed
The part of substrate exposed with first groove, to form grid structure and second groove, second groove is formed
In the substrate of the first side of grid structure.First is formed in the substrate of the first side of grid structure conductive
First well region of type.The second well region of the second conductivity type is formed in the substrate of the second side of grid structure,
Wherein the second side is relative with the first side.In the side wall formation clearance wall of grid structure, clearance wall fills up second
Groove.Drain region is formed in the substrate of the first side of grid structure, and in the second side of grid structure
Source area is formed in substrate.
In one embodiment of this invention, the first conductor layer of above-mentioned the first side in conductor structure is with being situated between
The step of first groove is formed in electric layer is as follows.Clearance wall is sacrificed in the side wall formation of conductor structure.Remove
The sacrifice clearance wall and part adhesion coating of first side of conductor structure, are open with being formed in adhesion coating.
Remove the sacrifice clearance wall of the second side of conductor structure.Remove opening exposed the first conductor layer and dielectric
Layer.
In one embodiment of this invention, the material of above-mentioned sacrifice clearance wall includes silicon oxynitride, oxidation
Silicon or silicon nitride.
In one embodiment of this invention, the manufacturer of above-mentioned lateral diffused metal-oxide semiconductor element
The step of method, further includes and the first light doped region is formed in the substrate between grid structure and drain region, and in
The second light doped region is formed in substrate between grid structure and source area.
In one embodiment of this invention, the first above-mentioned light doped region is around second groove.
In one embodiment of this invention, the first above-mentioned conductivity type is N-type, and the second conductivity type is P
Type.Or first conductivity type be p-type, the second conductivity type be N-type.
In one embodiment of this invention, the manufacturer of above-mentioned lateral diffused metal-oxide semiconductor element
The step of method, is additionally included in before forming clearance wall, in formation on the both sides of grid structure and second groove
Lining oxide layer.
In one embodiment of this invention, the manufacturer of above-mentioned lateral diffused metal-oxide semiconductor element
The step of method further includes forms at least one isolation structure in the substrate.
In one embodiment of this invention, the material of above-mentioned clearance wall include silicon oxynitride, silica or
Silicon nitride.
In one embodiment of this invention, the material of the first above-mentioned conductor layer includes polysilicon.
In one embodiment of this invention, the material of the second above-mentioned conductor layer includes metal material.
In one embodiment of this invention, the material of above-mentioned adhesion coating includes metal silicide.
The lateral diffusion metal-oxide-semiconductor element of the present invention, including：Substrate, grid structure, the first well region,
Second well region, clearance wall, drain region and source area.There is groove in substrate.Grid structure is arranged at
In substrate.First well region has the first conductivity type, and is arranged in the substrate of the first side of grid structure.
Second well region has the second conductivity type, and the second side of grid structure is arranged in substrate.Clearance wall is set
In the side wall of grid structure, and it is arranged at the clearance wall of the first side of grid structure and more fills up groove.Drain electrode
Area is arranged in the substrate of the first side of grid structure.Source area is arranged at the base of the second side of grid structure
In bottom.
In one embodiment of this invention, above-mentioned grid structure includes the first conductor layer, adhesion coating, the
Two conductor layers and dielectric layer.
In one embodiment of this invention, above-mentioned lateral diffused metal-oxide semiconductor element further includes
One light doped region and the second light doped region.First light doped region is arranged between grid structure and drain region
Substrate in.Second light doped region is arranged in the substrate between grid structure and source area.
In one embodiment of this invention, the first above-mentioned light doped region is around groove.
In one embodiment of this invention, the material of above-mentioned clearance wall include silicon oxynitride, silica or
Silicon nitride.
In one embodiment of this invention, above-mentioned lateral diffused metal-oxide semiconductor element further include to
A few isolation structure.Isolation structure is arranged in substrate.
In one embodiment of this invention, above-mentioned lateral diffused metal-oxide semiconductor element further includes lining
Oxide layer.Lining oxide layer is arranged between grid structure and clearance wall, and be arranged at the first well region and
Between gap wall.
In one embodiment of this invention, the first above-mentioned conductivity type is N-type, and the second conductivity type is P
Type.Or first conductivity type be p-type, the second conductivity type be N-type.
Based on above-mentioned, in the manufacture method of lateral diffusion metal-oxide-semiconductor element proposed by the present invention, to lead
Body structure is as self-aligned mask, while the first conductor layer and the groove in substrate are formed, due to not
Extra lithographic fabrication process is needed, therefore manufacture craft is relatively simple.Due to making between drain region
Gap wall down extends and inserted in the groove of substrate, and is used as item isolation structure.Item isolation junction
The depth (i.e. the depth of groove) of structure is controlled by autoregistration manufacture craft, and therefore, it helps avoid filling out
The depth for entering clearance wall (being used as item isolation structure) in groove is too deep, so that reduction is horizontal
To the opening resistor of diffusion metal-oxide-semiconductor element.In addition, being formed between grid structure and drain region secondary
Component isolation structure, it helps to reduce the electric field between grid structure and drain region, so that lifting is horizontal
To the breakdown voltage of diffusion metal-oxide-semiconductor element.
In the lateral diffusion metal-oxide-semiconductor element of the present invention, the clearance wall close to drain electrode down extends simultaneously
In the groove for inserting substrate, and as item isolation structure, this time component isolation structure is advantageously reduced
The opening resistor of lateral diffusion metal-oxide-semiconductor element.Moreover, item isolation structure is arranged at grid knot
Between structure and drain region, it helps to reduce the electric field between grid structure and drain region, in favor of lifting
The breakdown voltage of lateral diffusion metal-oxide-semiconductor element.
For the features described above and advantage of the present invention can be become apparent, special embodiment below, and coordinate
Appended accompanying drawing is described in detail below.
Brief description of the drawings
Figure 1A~Fig. 1 H are according to the lateral diffusion metal-oxide-semiconductor element depicted in one embodiment of the invention
Manufacturing process diagrammatic cross-section.
Symbol description
10：Lateral diffusion metal-oxide-semiconductor element
100：Substrate
102：Isolation structure
104、104a：Dielectric layer
106、106a、106b：First conductor layer
108、108a、108b：Adhesion coating
110、110a：Second conductor layer
112：Sacrifice clearance wall
114：Photoresist layer
116、118：Groove
116a：Opening
120：Grid structure
122：First well region
124：Second well region
126：First light doped region
128：Second light doped region
130：Lining oxide layer
132：Clearance wall
134：Drain region
136：Source area
138：Matrix pole
Embodiment
Figure 1A~Fig. 1 H are according to the lateral diffusion metal-oxide-semiconductor element depicted in one embodiment of the invention
Manufacturing process diagrammatic cross-section.
Hereinafter, will be using the first conductivity type as N-type, the second conductivity type is that p-type is example to illustrate, but this
Invention is not limited thereto.One skilled in the art is it will be appreciated that can also put the first conductivity type
Change p-type into, the second conductivity type is replaced as N-type.Wherein, N-type admixture is, for example, phosphorus or arsenic；P-type
Admixture is, for example, boron.
Figure 1A be refer to there is provided substrate 100, there is at least one isolation structure 102 in substrate 100.
Substrate 100 is, for example, P-type semiconductor substrate.Isolation structure 102 is, for example, fleet plough groove isolation structure.So
Afterwards, in sequentially formed in substrate 100 dielectric layer 104, the first conductor layer 106, adhesion coating 108 and
Second conductor layer 110.
The material of dielectric layer 104 is, for example, silica.The forming method of dielectric layer 104 is, for example, thermal oxide
Method or chemical vapour deposition technique.
The material of first conductor layer 106 includes conductor material, e.g. polysilicon or DOPOS doped polycrystalline silicon etc..
The forming method of first conductor layer 106 is, for example, chemical vapour deposition technique.The material of adhesion coating 108 includes
Metal, metal silicide or metal nitride, e.g. tungsten, titanium/titanium nitride.The formation of adhesion coating 108
Method is, for example, physical vaporous deposition or chemical vapour deposition technique.The material of second conductor layer 110 includes
Metal material, e.g. tungsten etc..The forming method of second conductor layer 110 is, for example, physical vaporous deposition
Or chemical vapour deposition technique.In the present embodiment, the material of the first conductor layer 106 is, for example, polysilicon,
And second the material of conductor layer 110 be, for example, tungsten.Therefore, when forming the second conductor layer 110, it can lead to
It is gold to cross metal silication reaction and material is formed between the first conductor layer 106 and the second conductor layer 110
Belong to the adhesion coating 108 of silicide, to increase the convenience of manufacture craft.
Figure 1B is refer to, first, the second conductor layer 110 is patterned, to form conductor structure 110a.
Patterning the method for the second conductor layer 110 includes photoetching process.For example, first second
Patterned mask layer (not illustrating) is formed in conductor layer 110, to expose the second conductor layer of part 110.
Afterwards, using patterned mask layer as mask, system is etched to the second conductor layer of part 110 exposed
Make technique.Then, patterned mask layer is removed.
Then, clearance wall 112 is sacrificed in formation on conductor structure 110a side.Sacrifice clearance wall 112
Material need to have appropriate etching selectivity with the material of the first conductor layer 106, in addition have no especially
Limitation, the material for sacrificing clearance wall 112 is, for example, silicon oxynitride, silica or silicon nitride.Sacrifice gap
The forming method of wall 112 is, for example, in formation gap wall material in substrate 100 first with chemical vapour deposition technique
The bed of material (is not illustrated), then carries out anisotropic etching manufacture craft to remove the portion gap wall material bed of material.
Fig. 1 C are refer to, in the photoresist layer 114 that patterning is formed in substrate 100.Patterning
Photoresist layer 114 at least exposes the sacrifice clearance wall 112 on conductor structure 110a the first side.
In one embodiment, the photoresist layer 114 of patterning only exposes the first of conductor structure 110a
Sacrifice clearance wall 112 on side.In another embodiment, the photoresist layer 114 of patterning exposes
Go out on conductor structure 110a the first side and sacrifice clearance wall 112 and part conductor structure 110a top
Face.The photoresist layer 114 of this patterning is, for example, to be formed via exposed and developed.To pattern
Photoresist layer 114 be mask, remove positioned at conductor structure 110a the first side on sacrifice between
Gap wall 112, further removes part adhesion coating 108 afterwards, to form the adhesion coating with opening 116a
108a.Removing the method for sacrifice clearance wall 112 and adhesion coating 108 includes wet etching or dry-etching
Method.In the making of sacrifice clearance wall 112 of the above-mentioned removal on conductor structure 110a the first side
In technique, if the photoresist layer 114 of patterning exposes part conductor structure 110a top surface,
The part conductor structure 110a then exposed also can be as mask, and therefore, it can be considered a kind of autoregistration
Manufacture craft.
Fig. 1 D are refer to, the photoresist layer 114 of patterning is removed, the photoresist of patterning is removed
The method of oxidant layer 114 is, for example, to carry out wet type to go the manufacture crafts such as photoresist, ashing.Then, move
Except the sacrifice clearance wall 112 on conductor structure 110a the second side.Remove and sacrifice clearance wall 112
Method includes wet etching or dry etching method.Clearance wall 112 is sacrificed when being removed with wet etching
When, its etching solution is, for example, selected from hydrofluoric acid (HF) and phosphoric acid (H3PO4) group that is constituted.For example,
When the material for sacrificing clearance wall 112 is silica, removes and sacrifice clearance wall 112 e.g. with hydrofluoric acid
(HF) as etching solution；And when the material for sacrificing clearance wall 112 is silicon nitride, removes and sacrifice clearance wall
112 be, for example, with phosphoric acid (H3PO4) it is used as etching solution with hydrofluoric acid (HF).
Fig. 1 E are refer to, using conductor structure 110a and adhesion coating 108a as mask, part first is removed and leads
Body layer 106 and part of dielectric layer 104, with the first conductor layer of conductor structure 110a the first side
106 with forming groove 116 in dielectric layer 104.Groove 116 exposes the top surface of substrate 100.One
In embodiment, conductor structure 110a one side can align with the one side of groove 116.Remove part
First conductor layer 106 and the method for part of dielectric layer 104 include dry etching method or wet etching.
Fig. 1 F are refer to, are mask with conductor structure 110, part adhesion coating 108a, part the is removed
The part of substrate 100 that one conductor layer 106a is exposed with groove 116, to form grid structure 120 and ditch
Groove 118.Grid structure 120 includes being led by the dielectric layer 104a of the first conductor layer 106b coverings, first
Body layer 106b, adhesion coating 108b and conductor structure 110a.First conductor layer 106b is located at conductor knot
Below structure 110a.Adhesion coating 108b is located between the first conductor layer 106b and conductor structure 110a.Ditch
Groove 118 is formed in the substrate 100 of the first side of grid structure 120.Removal part adhesion coating 108a,
The method for the part of substrate 100 that part the first conductor layer 106a is exposed with groove 116 is lost including dry type
Lithography or wet etching.
In the present invention, using conductor structure 110a as mask, and groove 118 is formed in substrate 100,
That is, groove 118 is formed using autoregistration manufacture craft, due to extra optical graving need not be used
Make technique, therefore manufacture craft can be simplified.In addition, when removing the first conductor layer 106a, in the lump
Remove part of substrate 100 to form groove 118, the depth of groove 118 can be made by the first conductor layer 106b
Height control.In one embodiment, the depth of groove 118 is equal to the first conductor layer 106b height
Degree.In another embodiment, the depth of groove 118 is less than the first conductor layer 106b height.
Fig. 1 G are refer to, first, first are formed in the substrate 100 of the first side of grid structure 120
First well region 122 of conductivity type.In the present embodiment, the generation type of the first well region 122 is, for example, first
A pattern layers photoresist layer (not illustrating) is formed in substrate, grid structure 120 is at least covered
The substrate 100 of second side.Then, to pattern photoresist layer as mask, ion implanting system is carried out
Make technique.This ion implanting manufacture craft includes being positioned at an angle the inclination of (0~90 degree) relative to substrate 100
The ion implanting manufacture craft of angle.By ion implanting manufacture craft, the first well region 122 to be formed can be made
Intactly around groove 118, and the first partial well region 122 extends to the lower section of grid structure 120.
In one embodiment, the first well region 122 is, for example, n-type doping area.In the present embodiment, the first well region
122 as lateral diffusion metal-oxide-semiconductor element drift region (Drift region).First well region 122 can subtract
Few electric current can lift the breakdown potential of lateral diffusion metal-oxide-semiconductor element in the lower section clustering of groove 118
Pressure.Then, patterning photoresist layer is removed.Remove the method for patterning photoresist layer for example
It is to carry out wet type to go the manufacture crafts such as photoresist, ashing.
Then, in forming another pattern layers photoresist layer (not illustrating) in substrate 100, at least cover
The substrate 100 of first side of lid grid structure 120.It is, for example, via exposure to pattern photoresist layer
And develop and formed.To pattern photoresist layer as mask, ion implanting manufacture craft is carried out, in
The second well region 124 of the second conductivity type is formed in the substrate 100 of second side of grid structure 120.This from
Son injection manufacture craft includes being positioned at an angle the ion note at the angle of inclination of (0~90 degree) relative to substrate 100
Enter manufacture craft.By ion implanting manufacture craft, the second well region 124 of part extends to grid structure
120 lower sections, make the second well region 124 adjacent with the first well region 122.In one embodiment, the second well region
124 be, for example, p-type doped region.In the present embodiment, the second well region 124 is used as lateral diffusion metal-oxide half
The matrix area (Body region) of conductor element.The conduct of the second well region 124 below grid structure 120
The passage area of lateral diffusion metal-oxide-semiconductor element.In one embodiment, the second well region 124 contact the
One well region 122, but the present invention is not limited thereto.Then, patterning photoresist layer is removed.Move
Except the method for patterning photoresist layer is, for example, to carry out wet type to go photoresist, ashing etc. to make work
Skill.
Afterwards, it is mask with grid structure 120, sequentially carries out ion implanting manufacture craft, respectively at the
In one well region 122 and the second well region 124 formed with the first conductivity type the first light doped region 126 and
The second light doped region 128 with the first conductivity type, wherein the first light doped region 126 is around groove 118
Around.In one embodiment, the first light doped region 128 of light doped region 126 and second is, for example, N
The light doped region of type.In the present embodiment, the first light doped region 126 is used as lateral diffusion metal-oxide-semiconductor member
The drift region of part.Due to above-mentioned ion implanting manufacture craft be using grid structure 120 as mask, because
This is also a kind of autoregistration manufacture craft.
Then, lining oxide layer 130 is formed on the side wall and groove 118 of grid structure 120.Serve as a contrast oxygen
Changing the material of layer 130 includes dielectric material, e.g. silica.The generation type example of lining oxide layer 130
Thermal oxidation method or chemical vapour deposition technique in this way.In one embodiment, lining oxide layer 130 is covered in grid
The side wall of structure 120 and the surface of groove 118, but the present invention is not limited.
Fig. 1 H are refer to, first, clearance wall 132, and clearance wall are formed in the side wall of grid structure 120
132 fill up groove 118.The material of clearance wall 132 is, for example, silicon oxynitride, silica or silicon nitride.
The generation type of clearance wall 132 is, for example, in forming gap in substrate 100 first with chemical vapour deposition technique
The wall material bed of material (is not illustrated), and the groove 118 that spacer material layer can be substantially filled up in substrate 100.
Then, anisotropic etching manufacture craft is carried out, the portion gap wall material bed of material is removed, leaves positioned at grid
The clearance wall 132 of the side wall of structure 120.Clearance wall 132 in the side of grid structure 120 first down extends
And insert in the groove 118 of substrate 100, and it is used as the dimension of lateral diffusion metal-oxide-semiconductor element 10
Part isolation structure, this component isolation structure advantageously reduces lateral diffusion metal-oxide-semiconductor element 10
Opening resistor.
Afterwards, it is mask with grid structure 120 and clearance wall 132, in the first side of grid structure 120
Substrate 100 in form drain region 134, and the shape in the substrate 100 of the second side of grid structure 120
Into source area 136.The generation type of drain region 134 and source area 136 is, for example, that ion implanting makes work
Skill.Drain region 134 is located at the substrate 100 of the first side of the first light doped region 126 and grid structure 120
In isolation structure 102 between.Source area 136 is located at the second light doped region 128 and grid structure 120
The second side substrate 100 in isolation structure 102 between.In one embodiment, drain region 134 and
Source area 136 is, for example, n-type doping area.
Come again, the matrix pole 138 with the second conductivity type is formed in the second well region 124.Matrix pole 138
Generation type be, for example, ion implanting manufacture craft.Matrix pole 138 is adjacent with source area 136.One
In embodiment, matrix pole 138 is, for example, p-type doped region.
In the present embodiment, using conductor structure 110a as self-aligned mask, while forming the first conductor
Layer 106b is with the groove 118 in substrate 100, the extra lithographic fabrication process due to not needing, because
This manufacture craft is relatively simple.Moreover, the depth of groove 118 can by the first conductor layer 106b height
To control, therefore the depth of clearance wall 132 (being used as isolation structure) being located in groove 118 can be avoided
Spend depth.If the depth of the clearance wall 132 in groove 118 is shallower, carrier can be shortened from source
Polar region 136 arrives the path of drain region 134, thus reduces opening for lateral diffusion metal-oxide-semiconductor element 10
Open resistance.Further, since the clearance wall 132 (being used as item isolation structure) in groove 118 is set
It is placed in the first well region 122, therefore item isolation structure is between grid structure 120 and drain region 134
Between, it helps to reduce the electric field between grid structure 120 and drain region 134, to lift horizontal expansion
Dissipate the breakdown voltage of metal-oxide-semiconductor element 10.
Then, the lateral diffusion metal-oxide-semiconductor element depicted in one embodiment of the invention is illustrated.
Refer to Fig. 1 H, the lateral diffusion metal-oxide-semiconductor element 10 of the present embodiment include substrate 100,
Isolation structure 102, dielectric layer 104a, grid structure 120, the first well region 122, the second well region 124,
First light doped region 126, the second light doped region 128, lining oxide layer 130, clearance wall 132, drain region
134th, source area 136 and matrix pole 138.
There is groove 118 in substrate 100, and with isolation structure 102.Substrate 100 is, for example, p-type
Semiconductor base.Isolation structure 102 is, for example, fleet plough groove isolation structure.
Grid structure 120 is arranged in substrate 100.Grid structure 120 includes conductor structure 110a, glued
Layer 108b, the first conductor layer 106b and dielectric layer 104a.Conductor structure 110a material includes
Metal material, e.g. tungsten etc..Adhesion coating 108b material includes metal, metal silicide or metal
Nitride, e.g. tungsten, titanium/titanium nitride.First conductor layer 106b material includes conductor material, example
Polysilicon or DOPOS doped polycrystalline silicon etc. in this way.Dielectric layer 104a material includes dielectric material, e.g. oxygen
SiClx.
First well region 122 has the first conductivity type, and is arranged at the substrate of the first side of grid structure 120
In 100, wherein groove 118 is arranged in the first well region 122.
Second well region 124 has the second conductivity type, is arranged at the second side of grid structure 120 and is arranged at
In substrate 100.
Lining oxide layer 130 is arranged between grid structure 120 and clearance wall 132, and is arranged at first
Between well region 122 and clearance wall 132.The material of lining oxide layer 130 includes dielectric material, e.g. oxygen
SiClx.
Clearance wall 132 is arranged at the side wall of grid structure 120, and is arranged at the first of grid structure 120
The clearance wall 132 of side more fills up groove 118.The material of clearance wall 132 is, for example, silicon oxynitride, oxidation
Silicon or silicon nitride.Clearance wall 132 in the side of grid structure 120 first down extends and inserts substrate 100
Groove 118 in, and as the item isolation structure of lateral diffusion metal-oxide-semiconductor element 10, this
Item isolation structure advantageously reduces the opening resistor of lateral diffusion metal-oxide-semiconductor element 10.
Drain region 134 is arranged in the substrate 100 of the first side of grid structure 120.Source area 136 is set
In the substrate 100 for being placed in the second side of grid structure 120.
First light doped region 126 is arranged in the substrate 100 between grid structure 120 and drain region 134,
And around groove 118.Second light doped region 128 is arranged at grid structure 120 and source area 136
Between substrate 100 in.
In the present embodiment, the clearance wall 132 close to drain region 134 down extends and inserts substrate 100
Groove 118 in, and be used as item isolation structure.(the dimension of clearance wall 132 in groove 118
Part isolation structure) if depth it is shallower, carrier can be shortened from source area 136 to drain region 134
Path, thus the opening resistor of reduction lateral diffusion metal-oxide-semiconductor element 10.Moreover, item every
From structure setting between grid structure 120 and drain region 134, it helps to reduce grid structure 130
With the electric field between drain region 134, in favor of lifted lateral diffusion metal-oxide-semiconductor element breakdown voltage.
In summary, in the manufacture method of lateral diffusion metal-oxide-semiconductor element proposed by the present invention, to lead
Body structure is as self-aligned mask, while the first conductor layer and the groove in substrate are formed, due to not
Extra lithographic fabrication process is needed, therefore manufacture craft is relatively simple.Due to making between drain region
Gap wall down extends and inserted in the groove of substrate, and is used as item isolation structure.Item isolation junction
The depth (i.e. the depth of groove) of structure is controlled by autoregistration etching process, and therefore, it helps to keep away
The depth for exempting to fill in clearance wall (being used as item isolation structure) in groove is too deep, in favor of drop
Low cross spreads the opening resistor of metal-oxide-semiconductor element.In addition, between grid structure and drain region shape
Into item isolation structure, it helps to reduce the electric field between grid structure and drain region, in favor of carrying
Rise the breakdown voltage of lateral diffusion metal-oxide-semiconductor element.
In the lateral diffusion metal-oxide-semiconductor element of the present invention, the clearance wall close to drain region down extends
And insert in the groove of substrate, and as item isolation structure, this time component isolation structure is conducive to drop
Low cross spreads the opening resistor of metal-oxide-semiconductor element.Moreover, item isolation structure is arranged at grid
Between structure and drain region, it helps to reduce the electric field between grid structure and drain region, in favor of carrying
Rise the breakdown voltage of lateral diffusion metal-oxide-semiconductor element.
Although disclosing the present invention with reference to above example, but it is not limited to the present invention, any
Skilled person in art, without departing from the spirit and scope of the present invention, can make a little
Change and retouching, therefore protection scope of the present invention should be by being defined that the claim enclosed is defined.
Claims (20)
1. a kind of manufacture method of lateral diffused metal-oxide semiconductor element, including：
Substrate is provided, sequentially formed in the substrate dielectric layer, the first conductor layer, adhesion coating and
Second conductor layer；
Second conductor layer is patterned, to form conductor structure；
First is formed in first conductor layer and the dielectric layer of the first side of the conductor structure
Groove；
Using the conductor structure as mask, remove first conductor layer and exposed with the first groove
The part substrate, to form grid structure and second groove, the second groove is formed at the grid
In the substrate of first side of pole structure；
The first trap of the first conductivity type is formed in the substrate of first side of the grid structure
Area；
The second well region of the second conductivity type is formed in the substrate of the second side of the grid structure, its
Described in the second side it is relative with first side；
In the side wall formation clearance wall of the grid structure, the clearance wall fills up the second groove；With
And
Drain region is formed in the substrate of first side of the grid structure, and in the grid
Source area is formed in the substrate of second side of structure.
2. the manufacture method of lateral diffused metal-oxide semiconductor element as claimed in claim 1, its
In form institute in first conductor layer and the dielectric layer of first side of the conductor structure
First groove is stated, including：
Clearance wall is sacrificed in the side wall formation of the conductor structure；
Remove the sacrifice clearance wall and the part adhesion of first side of the conductor structure
Layer, is open with being formed in the adhesion coating；
Remove the sacrifice clearance wall of second side of the conductor structure；And
Remove first conductor layer exposed and the dielectric layer of being open.
3. the manufacture method of lateral diffused metal-oxide semiconductor element as claimed in claim 2, its
Described in sacrifice clearance wall material include silicon oxynitride, silica or silicon nitride.
4. the manufacture method of lateral diffused metal-oxide semiconductor element as claimed in claim 1, also
Including：
The first light doped region is formed in the substrate between the grid structure and the drain region, and
The second light doped region is formed in the substrate between the grid structure and the source area.
5. the manufacture method of lateral diffused metal-oxide semiconductor element as claimed in claim 4, its
Described in the first light doped region around the second groove.
6. the manufacture method of lateral diffused metal-oxide semiconductor element as claimed in claim 1, its
Described in the first conductivity type be N-type, second conductivity type be p-type；Or first conductivity type is P
Type, second conductivity type is N-type.
7. the manufacture method of lateral diffused metal-oxide semiconductor element as claimed in claim 1, also
Including：
Before the clearance wall is formed, in shape on the both sides of the grid structure and the second groove
Into lining oxide layer.
8. the manufacture method of lateral diffused metal-oxide semiconductor element as claimed in claim 1, also
Including：
At least one isolation structure is formed in the substrate.
9. the manufacture method of lateral diffused metal-oxide semiconductor element as claimed in claim 1, its
Described in the material of clearance wall be to include silicon oxynitride, silica or silicon nitride.
10. the manufacture method of lateral diffused metal-oxide semiconductor element as claimed in claim 1, its
Described in the first conductor layer material include polysilicon or DOPOS doped polycrystalline silicon.
11. the manufacture method of lateral diffused metal-oxide semiconductor element as claimed in claim 1, its
Described in the second conductor layer material include metal material.
12. the manufacture method of lateral diffused metal-oxide semiconductor element as claimed in claim 1, its
Described in adhesion coating material include metal, metal silicide or metal nitride.
13. a kind of lateral diffused metal-oxide semiconductor element, including：
There is groove in substrate, the substrate；
Grid structure, is arranged in the substrate；
First well region, with the first conductivity type, is arranged at the substrate of the first side of the grid structure
In, the groove is arranged in first well region；
Second well region, with the second conductivity type, is arranged at the substrate of the second side of the grid structure
In；
Clearance wall, is arranged at the side wall of the grid structure, is provided with described in the grid structure
The clearance wall of first side also fills up the groove；
Drain region, is arranged in the substrate of first side of the grid structure；And
Source area, is arranged in the substrate of second side of the grid structure.
14. lateral diffused metal-oxide semiconductor element as claimed in claim 13, wherein the grid
Pole structure includes the first conductor layer, adhesion coating, the second conductor layer and dielectric layer.
15. lateral diffused metal-oxide semiconductor element as claimed in claim 13, in addition to：
First light doped region, is arranged in the substrate between the grid structure and the drain region；
And
Second light doped region, is arranged in the substrate between the grid structure and the source area.
16. lateral diffused metal-oxide semiconductor element as claimed in claim 15, wherein described
One light doped region is around the groove.
17. lateral diffused metal-oxide semiconductor element as claimed in claim 13, wherein between described
The material of gap wall includes silicon oxynitride, silica or silicon nitride.
18. lateral diffused metal-oxide semiconductor element as claimed in claim 13, in addition at least
One isolation structure, is arranged in the substrate.
19. lateral diffused metal-oxide semiconductor element as claimed in claim 13, in addition to lining oxygen
Change layer, be arranged between the grid structure and the clearance wall, and be arranged at first well region with
Between the clearance wall.
20. lateral diffused metal-oxide semiconductor element as claimed in claim 13, wherein described
One conductivity type is N-type, and second conductivity type is p-type；Or first conductivity type is p-type, institute
The second conductivity type is stated for N-type.
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| TW105101741 | 2016-01-20 | ||
| TW105101741A TWI571939B (en) | 2016-01-20 | 2016-01-20 | Lateral diffused metal oxide semiconductor device and method for fabricating the same |
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|---|---|---|---|---|
| CN113380627A (en) * | 2021-08-12 | 2021-09-10 | 晶芯成(北京)科技有限公司 | LDMOS transistor and forming method thereof |
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| CN101625998A (en) * | 2008-07-09 | 2010-01-13 | 东部高科股份有限公司 | Lateral double diffused metal oxide semiconductor device and manufacturing method of lateral double diffused metal oxide semiconductor device |
| US8138559B2 (en) * | 2007-04-03 | 2012-03-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Recessed drift region for HVMOS breakdown improvement |
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| US6876035B2 (en) * | 2003-05-06 | 2005-04-05 | International Business Machines Corporation | High voltage N-LDMOS transistors having shallow trench isolation region |
| KR100488196B1 (en) * | 2003-09-29 | 2005-05-09 | 삼성전자주식회사 | Transistor having Raised Drain and Method of forming the same |
| EP1577952B1 (en) * | 2004-03-09 | 2018-07-04 | STMicroelectronics Srl | Method of making a high voltage insulated gate field-effect transistor |
| US7781292B2 (en) * | 2007-04-30 | 2010-08-24 | International Business Machines Corporation | High power device isolation and integration |
| TWI548090B (en) * | 2012-02-07 | 2016-09-01 | 聯華電子股份有限公司 | Semiconductor device and method of fabricating the same |
| US20150145034A1 (en) * | 2013-11-24 | 2015-05-28 | United Microelectronics Corporation | Ldmos structure and manufacturing method thereof |
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|---|---|---|---|---|
| US5491099A (en) * | 1994-08-29 | 1996-02-13 | United Microelectronics Corporation | Method of making silicided LDD with recess in semiconductor substrate |
| US8138559B2 (en) * | 2007-04-03 | 2012-03-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Recessed drift region for HVMOS breakdown improvement |
| CN101625998A (en) * | 2008-07-09 | 2010-01-13 | 东部高科股份有限公司 | Lateral double diffused metal oxide semiconductor device and manufacturing method of lateral double diffused metal oxide semiconductor device |
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| CN113380627A (en) * | 2021-08-12 | 2021-09-10 | 晶芯成(北京)科技有限公司 | LDMOS transistor and forming method thereof |
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| TWI571939B (en) | 2017-02-21 |
| TW201727756A (en) | 2017-08-01 |
| CN106992123B (en) | 2020-02-07 |
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