CN106980594A - A kind of low-cost and high-performance space computer - Google Patents
A kind of low-cost and high-performance space computer Download PDFInfo
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- CN106980594A CN106980594A CN201710221688.XA CN201710221688A CN106980594A CN 106980594 A CN106980594 A CN 106980594A CN 201710221688 A CN201710221688 A CN 201710221688A CN 106980594 A CN106980594 A CN 106980594A
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- core cpu
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
Abstract
The invention discloses a kind of space computer of low-cost and high-performance, including：3 double-core CPU, 3 groups of dynamic memories, 3 program storages, arbitration and bus expand FPGA, PCIe bus switch chip, kilomega network bus switch chip.Double-core CPU possesses polytype external interface；Dynamic memory provides outside exented memory for CPU；Program storage provides program's memory space for CPU；Arbitration and bus expand FPGA and CPU working conditions are judged and arbitrated, and select the CPU on duty external input and output of HDLC low speed bus；PCIe bus switch chips are responsible for each 2 PCIe buses from 3 CPU focusing on two external PCIe buses；Kilomega network bus switch chip is responsible for each 2 kilomega network interface concentrations from 3 CPU to two external preposition network interfaces.The computer had both been reduced to exterior node, in turn ensured that signal quality and bandwidth.
Description
Technical field
The present invention relates to the computer installation of the electronic equipment in space, more particularly to a kind of low-cost and high-performance space is used
Computer.
Background technology
Space computer has a wide range of applications in fields such as the rail control system of spacecraft, data processing, payload,
With the development of the miniaturization of satellite, synthesization, integration and commercialization, space is needed to realize more and more with computer
Function.Therefore, to the data-handling capacity of the computer in space, data throughout, power consumption, cost, external interface it is abundant
Higher and higher requirement is proposed in terms of degree.Conventional space computer can not often meet those more and more highers at present
Requirement.In addition, it is contemplated that complicated space environment, the computer system in space must also possess higher reliability and anti-
Single-particle ability.
The content of the invention
It is an object of the invention to provide a kind of low-cost and high-performance space computer, used tricks with solving existing space
Calculation machine can not typically meet data-handling capacity, the data throughput of the computer in existing space application to space well
The problem of high request proposed in terms of amount, power consumption, cost, the abundant degree of external interface.
The second object of the present invention is to provide a kind of low-cost and high-performance space computer, to solve existing high property
Energy computer is not suitable for the space environment of complexity, and due to not possessing, higher reliability and anti-single particle ability can not be used directly
The problem of in space application.
To achieve the above object, the invention provides a kind of low-cost and high-performance space computer, it is characterised in that bag
Include：Three are run module, arbitration and bus and expand FPGA, PCIe bus switch chip and kilomega network bus switch chip,
Wherein, each operation module includes：Double-core CPU, for execution system computing, with ECC error correction function；Dynamic is deposited
Reservoir, for providing working memory for the double-core CPU, and coordinates the double-core CPU to carry out monobit errro correction；Program storage
Device, the configuration processor for storing the double-core CPU, and coordinate the double-core CPU to carry out monobit errro correction；
The arbitration and bus expand the redundancy mould that FPGA is used to determine computer according to the job information of the double-core CPU
Formula；The PCIe bus switch chip connects for the PCIe buses from 3 double-core CPU to be focused on into an external PCIe bus
Mouthful；The kilomega network bus switch chip is used for the kilomega network interface concentration from 3 double-core CPU to an external kilomega network
Interface.
It is preferred that the double-core CPU uses double-core ARM-Cortex-A7 frameworks, dominant frequency is up to 1GHz, and operational capability is most
Greatly 4000MIPS, possesses the caching inside floating-point operation ability, and double-core CPU and possesses ECC error correction function.
It is preferred that the built-in Peripheral Interface of the chip of the double-core CPU includes：I2C、UART、CAN、SPI、I2S.
It is preferred that using usb bus connection, under normal circumstances, three double-cores between the double-core CPU of three operation modules
CPU runs identical program, and the program that each double-core CPU obtains two other double-core CPU by the usb bus, which is run, to be tied
Really, each double-core CPU obtains operation result by two from three voting, and three double-core CPU operation result carries out final three again
Two votings are taken to obtain final operation result；When three one or two failures run in module, computer correspondence is downgraded to
Dual OMU Servers Mode with double computing modules or the single cpu mode with single operation module.
It is preferred that the dynamic memory uses DDR4SDRAM, the DDR4SDRAM to pass through independent RAM buses and institute
Double-core CPU communications are stated, data throughout is up to 1600MT/s, and coordinate the ECC error correction function of the double-core CPU to carry out list
Bit error correction.
It is preferred that described program memory is communicated using NAND FLASH, the NAND FLASH with the double-core CPU,
By coordinating the ECC error correction function of the double-core CPU to carry out monobit errro correction.
Lead to it is preferred that the double-core CPU expands FPGA by HDLC low speed time-divisions universal serial bus with the arbitration and bus
Letter, the arbitration and bus expand FPGA also by HDLC low speed time-divisions universal serial bus and computer PERCOM peripheral communication, maximum clock
For 25MHz.
It is preferred that the maximum speed of the external PCIe EBIs is 2.5GT/s；The external gigabit network interface is most
It is 1.25Gbps at high speed.
It is preferred that it is anti-fuse FPGA that the arbitration and bus, which expand FPGA, for the double-core CPU to three operation modules
Working condition make decisions, its working condition is judged, to determine the redundant mode of computer and the double-core CPU of failure is carried out
Reset or isolate.
It is preferred that the external high low speed bus of computer uses the form of double-bus redundancy.
The space computer that the present invention is provided, the low-cost and high-performance scheme above-mentioned due to taking utilizes 3 high-performance
Low cost commercialization double-core CPU networkings work, and improve reliability of the system under complex space environment using many kinds of measures, obtain
Following beneficial effect：
1.CPU dominant frequency is high, and operational capability is strong, is also equipped with floating-point operation ability, internal Cache possesses ECC error correction function, nothing
It need to increase and outer hardware resource can correct single-bit error, single particle effect can be effectively antagonized.Peripheral hardware enrich, possess I2C,
The Peripheral Interfaces such as UART, CAN, SPI, I2S；
2. being connected between three machine group-network constructions, CPU using usb bus, handling capacity is high, and interface is simple；
3. complete machine externally possesses double high low-frequency serial bus (PCIe, kilomega network, HDLC time-shared bus), both reduced externally
Node, in turn ensures that signal quality and bandwidth.
Brief description of the drawings
Fig. 1 constitutes structure chart for the space calculating machine that the preferred embodiment of the present invention is provided.
Embodiment
Below with reference to the accompanying drawing of the present invention, clear, complete description is carried out to the technical scheme in the embodiment of the present invention
And discussion, it is clear that as described herein is only a part of example of the present invention, is not whole examples, based on the present invention
In embodiment, the every other implementation that those of ordinary skill in the art are obtained on the premise of creative work is not made
Example, belongs to protection scope of the present invention.
To adapt to the development of the miniaturization of satellite, synthesization, integration, commercialization, space computer needs stronger
Data-handling capacity, higher data throughout, higher abundant external interface, lower unit work consumptiom and cost, also simultaneously
Must possess higher reliability and anti-single particle ability.The present invention disclosure satisfy that the process demand of space computer, and adapt to
Complicated space environment.
For the ease of the understanding to the embodiment of the present invention, below in conjunction with accompanying drawing by taking specific embodiment as an example to the present invention's
Space is further explained with computer, and each embodiment does not constitute the restriction to embodiment of the present invention.
As shown in figure 1, present embodiments providing a kind of low-cost and high-performance space computer, the computer includes：Three
Individual operation module is respectively 10,20,30, arbitration and bus expand FPGA 40, PCIe bus switch chip 50 and gigabit network bus
Exchange chip 60,
Wherein, operation module 10 includes double-core CPU 11, dynamic memory 12 and program storage 13, accordingly, operation
Module 20 includes double-core CPU 21, dynamic memory 22 and program storage 23, and operation module 30 includes double-core CPU 31, dynamic
Memory 32 and program storage 33.Wherein, in each operation module, double-core CPU is used for execution system computing, with ECC
Error correction；Dynamic memory is used to provide working memory for the double-core CPU, and coordinates the double-core CPU to carry out digital ratio
Special error correction；Program storage is used for the configuration processor for storing double-core CPU, and coordinates double-core CPU to carry out monobit errro correction.
And arbitration and bus expand FPGA 40 and are used to be determined according to the job information of the double-core CPU in each operation module
The redundant mode of computer；PCIe bus switch chip 50 (PCIe switch) is used for the PCIe from 3 double-core CPU is total
Line focuses on an external PCIe EBI, and its quantity is two；(the Ethernet of kilomega network bus switch chip 60
Switch) it is used for the kilomega network interface concentration from 3 double-core CPU to an external gigabit network interface, its quantity is two.
Specifically, the double-core CPU in the present embodiment uses the commercial double-core ARM-Cortex-A7 frameworks of high-performance and low-cost,
Dominant frequency is high, reaches as high as 1GHz, and operational capability is strong (being 4000MIPS to the maximum), possesses floating-point operation ability, and the computer
Double-core CPU inside Cache (caching) possesses ECC error correction function (ECC-Error Checking and Correcting, mistake
Flase drop is looked into and corrected, and is a kind of computer technology for being widely used in various fields, is a kind of correcting data error technology), without increasing
Plus and outer hardware resource can correct single-bit error, single particle effect can be effectively antagonized.The double-core cpu chip peripheral hardware is rich
Richness, the built-in Peripheral Interface of chip includes：I2C, UART, CAN, SPI, I2S etc..
Referring again to shown in Fig. 1, USB is used between the double-core CPU of above-mentioned in a preferred embodiment three operation modules
Bus is connected, under normal circumstances, and three double-core CPU run identical program, and each double-core CPU is obtained by the usb bus
Two other double-core CPU program operation result, each double-core CPU obtains operation result, three double-cores by two from three voting
CPU operation result carries out final two from three voting and obtains final operation result again；When three run module in one or
During two failures, computer correspondence is downgraded to the Dual OMU Servers Mode with double computing modules or the unit mould with single operation module
Formula.
Referring again to shown in Fig. 1, in a preferred embodiment, above-mentioned dynamic memory uses DDR4SDRAM (EDAC), makees
With being to provide working memory for CPU, DDR4SDRAM is communicated by independent RAM buses with double-core CPU, data throughout highest
ECC error correction function for 1600MT/s, and cooperation double-core CPU carries out monobit errro correction.
Referring again to shown in Fig. 1, in a preferred embodiment, above-mentioned program storage uses NAND FLASH (EDAC),
Effect is the configuration processor for storing CPU, and NAND FLASH communicate with double-core CPU, by the ECC error correction function of coordinating double-core CPU
Carry out monobit errro correction.
Further, referring to Fig. 1, double-core CPU in the present embodiment by HDLC low speed time-divisions universal serial bus and arbitration and
Bus expands FPGA communications, and it is two that arbitration and bus, which expand FPGA, and it is also by HDLC low speed time-divisions universal serial bus with calculating
Machine PERCOM peripheral communication, maximum clock is 25MHz.
In a preferred embodiment, the maximum speed of external PCIe EBIs is 2.5GT/s；The external gigabit network interface
Maximum speed be 1.25Gbps.
It is anti-fuse FPGA that arbitration and bus, which expand FPGA, the working condition for the double-core CPU to three operation modules
Make decisions, judge its working condition, with determine the redundant mode of computer and the double-core CPU of failure is resetted or every
From.
Externally high low speed bus is using the form of double-bus redundancy for computer, to improve whole aircraft reliability.
The rational CPU selections of the present invention and computer architecture are the cores of space computer, and the present invention uses high property
Double-core commercialization CPU, internal cache, outside SDRAM, FLASH of energy low-power consumption have ECC functions, can effectively antagonize single-particle
Upset；Complete machine is worked using three machine networkings, is carried out high-speed data interaction using usb bus between CPU, is improved system reliability；
Dual redundant high/low speed serial bus architecture is externally used, is obtained between handling capacity, external number of contacts, interface complexity preferably
Equilibrium；Complete machine redundant mode can be configured by CPU state monitoring, necessary Fault Isolation is carried out.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those skilled in the art the invention discloses technical scope in, to the present invention deformation or replacement done, should all cover
Within protection scope of the present invention.Therefore, protection scope of the present invention should be defined by described scope of the claims.
Claims (10)
1. a kind of low-cost and high-performance space computer, it is characterised in that including：Three are run module, arbitration and bus and opened up
FPGA, PCIe bus switch chip and kilomega network bus switch chip are opened up,
Wherein, each operation module includes：Double-core CPU, for execution system computing, with ECC error correction function；Dynamic memory
Device, for providing working memory for the double-core CPU, and coordinates the double-core CPU to carry out monobit errro correction；Program storage
Device, the configuration processor for storing the double-core CPU, and coordinate the double-core CPU to carry out monobit errro correction；
The arbitration and bus expand the redundant mode that FPGA is used to determine computer according to the job information of the double-core CPU；
The PCIe bus switch chip is used to the PCIe buses from 3 double-core CPU focusing on an external PCIe EBI；
The kilomega network bus switch chip is used to connect the kilomega network interface concentration from 3 double-core CPU to an external kilomega network
Mouthful.
2. low-cost and high-performance space according to claim 1 computer, it is characterised in that the double-core CPU is used
Double-core ARM-Cortex-A7 frameworks, dominant frequency is up to 1GHz, and operational capability is 4000MIPS to the maximum, possesses floating-point operation ability,
And the caching inside double-core CPU possesses ECC error correction function.
3. low-cost and high-performance space according to claim 2 computer, it is characterised in that the core of the double-core CPU
The built-in Peripheral Interface of piece includes：I2C、UART、CAN、SPI、I2S.
4. low-cost and high-performance space according to claim 1 computer, it is characterised in that pair of three operation modules
Connected between core CPU using usb bus, under normal circumstances, three double-core CPU run identical program, and each double-core CPU passes through
The usb bus obtains two other double-core CPU program operation result, and each double-core CPU obtains fortune by two from three voting
Row result, three double-core CPU operation result carries out final two from three voting and obtains final operation result again；When three operations
During one or two failure in module, computer correspondence is downgraded to Dual OMU Servers Mode with double computing modules or with single operation
The single cpu mode of module.
5. low-cost and high-performance space according to claim 1 computer, it is characterised in that the dynamic memory is adopted
Communicated with DDR4SDRAM, the DDR4SDRAM by independent RAM buses with the double-core CPU, data throughout is up to
1600MT/s, and coordinate the ECC error correction function of the double-core CPU to carry out monobit errro correction.
6. low-cost and high-performance space according to claim 1 computer, it is characterised in that described program memory is adopted
NAND FLASH, the NAND FLASH is used to be communicated with the double-core CPU, by the ECC error correction function of coordinating the double-core CPU
Carry out monobit errro correction.
7. low-cost and high-performance space according to claim 1 computer, it is characterised in that the double-core CPU passes through
HDLC low speed time-divisions universal serial bus with it is described arbitration and bus expand FPGA communicate, it is described arbitration and bus expansion FPGA also by
HDLC low speed time-divisions universal serial bus and computer PERCOM peripheral communication, maximum clock is 25MHz.
8. low-cost and high-performance space according to claim 1 computer, it is characterised in that the external PCIe buses
The maximum speed of interface is 2.5GT/s；The maximum speed of the external gigabit network interface is 1.25Gbps.
9. low-cost and high-performance space according to claim 1 computer, it is characterised in that the arbitration and bus are opened up
Exhibition FPGA is anti-fuse FPGA, and the working condition for the double-core CPU to three operation modules makes decisions, and judges its work shape
State, to determine the redundant mode of computer and the double-core CPU of failure is resetted or isolated.
10. low-cost and high-performance space according to claim 1 computer, it is characterised in that the external height of computer
Fast bus uses the form of double-bus redundancy.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710221688.XA CN106980594A (en) | 2017-04-06 | 2017-04-06 | A kind of low-cost and high-performance space computer |
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| CN201710221688.XA CN106980594A (en) | 2017-04-06 | 2017-04-06 | A kind of low-cost and high-performance space computer |
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| CN101576836A (en) * | 2009-06-12 | 2009-11-11 | 北京航空航天大学 | Degradable three-machine redundancy fault-tolerant system |
| CN101667454A (en) * | 2008-09-05 | 2010-03-10 | 三星电子株式会社 | Memory system and data processing method thereof |
| CN102023815A (en) * | 2009-09-15 | 2011-04-20 | 格雷戈里·伯德 | Implementing RAID in solid state memory |
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2017
- 2017-04-06 CN CN201710221688.XA patent/CN106980594A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101169962A (en) * | 2006-10-23 | 2008-04-30 | 国际商业机器公司 | High density high reliability memory module with a fault tolerant address and command bus |
| CN101667454A (en) * | 2008-09-05 | 2010-03-10 | 三星电子株式会社 | Memory system and data processing method thereof |
| CN101576836A (en) * | 2009-06-12 | 2009-11-11 | 北京航空航天大学 | Degradable three-machine redundancy fault-tolerant system |
| CN102023815A (en) * | 2009-09-15 | 2011-04-20 | 格雷戈里·伯德 | Implementing RAID in solid state memory |
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Application publication date: 20170725 |
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