CN106959412B - Graphic display method for circuit board test - Google Patents
Graphic display method for circuit board test Download PDFInfo
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- CN106959412B CN106959412B CN201710319711.9A CN201710319711A CN106959412B CN 106959412 B CN106959412 B CN 106959412B CN 201710319711 A CN201710319711 A CN 201710319711A CN 106959412 B CN106959412 B CN 106959412B
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- circuit board
- file
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention relates to a graphic display method for testing a circuit board, which comprises the following steps: generating an asc file through a circuit board file; asc generates complete graphic file of circuit board; displaying a circuit board graph through a display device arranged on the test equipment, wherein the circuit board graph displays element symbols corresponding to the circuit board elements; when the circuit board tests for defects, the circuit board pattern highlights the element symbols of the defective elements. The graphic display method for testing the circuit board can display the accurate positions of the elements on the front side and the back side of the circuit board, and can highlight the element symbols corresponding to the bad elements without manually searching the circuit board, thereby greatly saving the testing time and effectively improving the testing efficiency.
Description
Technical Field
The invention relates to the field of testing, in particular to a graphic display method for testing a circuit board.
Background
In the conventional circuit board test mode, the components of the circuit board need to be directly observed. If the bad elements, the needle points and the network positions are to be searched, the bad elements, the needle points and the network positions must be searched against a real circuit board or a needle point map, so that the efficiency is low and the error is easy to occur. Especially for some small circuit boards, it is very difficult to directly view by naked eyes
Disclosure of Invention
The invention provides a visual graphic display method for testing a circuit board, which overcomes the defects of the prior art.
Specifically, the graphic display method for testing a circuit board of the present invention comprises: generating an asc file through a circuit board file; asc generates complete graphic file of circuit board; displaying a circuit board graph through a display device arranged on the test equipment, wherein the circuit board graph displays element symbols corresponding to the circuit board elements; when the circuit board tests for defects, the circuit board graph highlights the element symbol, network name, and element pin number of the defective element.
Further, the circuit board file includes a PCB file or a GERBER file.
Further, the. Asc files comprise a Format. Asc file, a Nails. Asc file, a parts. Asc file, a Pin. Asc file and a status. Asc file, and the. Asc files are integrated into a. Bv file after the test equipment is called.
Further, the component symbols of the circuit board graphic display can be modified, deleted, added, moved or searched.
Further, the display device also displays a programming interface that displays a component name that establishes a hyperlink with a component symbol of the circuit board graphic.
Further, a plurality of spliced circuit boards are tested, the circuit board patterns display a plurality of spliced sub-circuit board patterns, and the plurality of sub-circuit board patterns are arranged in a predetermined order.
Further, the circuit board pattern can be displayed in a highlighting mode, and when the circuit board failure is detected, the failure sub-circuit board pattern is displayed in black or red, and the element symbol of the failure element is displayed in red or black.
The graphic display method for testing the circuit board can display the accurate positions of the elements on the front side and the back side of the circuit board, and can highlight the element symbols corresponding to the bad elements without manually searching the circuit board, thereby greatly saving the testing time and effectively improving the testing efficiency.
Drawings
FIG. 1 is a schematic illustration of a single circuit board pattern of a pattern display method of the circuit board test of the present invention;
FIG. 2 is a schematic diagram of a plurality of circuit board graphics of the graphic display method for testing a circuit board according to the present invention;
wherein 1 is a circuit board pattern, 11 is a reference symbol, 2 is a plurality of circuit board patterns, and 2a, 2b, 2c are sub-circuit board patterns.
Detailed Description
The following description is given of a graphic display method for testing a circuit board according to the present invention, without limitation, with reference to the accompanying drawings, for the purpose of better understanding the technical content of the public.
As shown in fig. 1, the graphic display method for testing a circuit board according to the present invention is used for online testing of the circuit board ICT (in circuit tester), and the graphic visualization is performed on the circuit board file through the display device.
Specifically, the graphic display method for testing the circuit board at least comprises the following steps: a. generating an asc file through a circuit board file; b. asc generates complete graphic file of circuit board; c. the circuit board pattern 1 is displayed by a display device provided with the test apparatus. The circuit board graphic displays the reference numeral 11 corresponding to the circuit board element. When the circuit board is tested to be bad, the circuit board graph highlights the element symbol of the bad element, and can be particularly displayed in red, and the circuit board graph is green or black.
The circuit board file may be a PCB file (circuit board design file) or a GERBER file (a collection of document formats for circuit board industry software describing circuit board images and drilling and milling data). The asc files include a Format. Asc file (coordinates of a recorded frame), a Nails. Asc file (coordinates of a recorded point), a parts. Asc file (names and coordinates of recorded parts), a Pin. Asc file (coordinates of a pin of a recorded part), and a status. Asc file (information of a needle implantation recorded). The asc file is integrated into a bv file after the test equipment is called. It should be noted that the element number 11 of the circuit board graphic display 1 can be modified, deleted, added, moved or searched, so that the user can directly search, modify, etc. the related information.
Of course, the display device also displays a programming interface that displays the component names that establish hyperlinks with the components of the circuit board graphic. When programming is performed manually, the name of the element can be double-clicked in the program Cheng Huamian, and the mouse can automatically jump to the position of the corresponding element on the graph, so that debugging working hours are saved.
The plurality of spliced circuit boards 2 are tested, the circuit board graphics display a plurality of spliced sub-circuit board graphics 2a, 2b and 2c, the plurality of sub-circuit board graphics are arranged according to a preset sequence, each sub-circuit board graphic can be numbered, and the numbered positions can be custom designed according to requirements. For example, the sub-circuit board patterns may be arranged as shown in fig. 2, that is, the sub-circuit board patterns are rotated by 90 degrees and then arranged in sequence from left to right, and the numbers are arranged at the lower left. The circuit board graph 2 can be displayed in a highlight mode, when the circuit board is tested to be bad, the bad sub-circuit board graph is displayed in black or red, the element symbol corresponding to the bad element is displayed in red or black, and the color of the good circuit board is kept unchanged.
The graphic display method for testing the circuit board can display the accurate positions of the elements on the front side and the back side of the circuit board, and can highlight the element symbols corresponding to the bad elements without manually searching the circuit board, thereby greatly saving the testing time and effectively improving the testing efficiency.
It should be understood that the foregoing is not intended to limit the scope of the invention, but in fact, all modifications to the invention, including modifications in the shape, size, materials used, and substitution of similar functional elements, based on the same or similar principles, are within the scope of the invention as claimed.
Claims (2)
1. A graphic display method for testing a circuit board, comprising:
generating an asc file through a circuit board file;
the test equipment calls the asc file to generate a complete circuit board graphic file;
displaying a circuit board graph through a display device arranged on the test equipment, wherein the circuit board graph displays element symbols corresponding to the circuit board elements;
when the circuit board tests to be bad, the circuit board graph highlights the element symbol, the network name and the element pin number of the bad element;
the information processing system comprises a plurality of information processing modules, a plurality of information processing modules and a plurality of information processing modules, wherein the information processing modules are used for processing information of a plurality of information processing modules, and the information processing modules are used for processing information of a plurality of information processing modules;
the asc files are integrated into a bv file after the test equipment is called;
the component symbols of the circuit board graphic display can be modified, deleted, added, moved or searched;
the display device also displays a programming interface, the programming interface displays a component name, the component name and a component of the circuit board graph establish a hyperlink, and when the component name is double-clicked in Cheng Huamian, the mouse automatically jumps to the position of the corresponding component on the graph;
testing a plurality of spliced circuit boards, wherein the circuit board graph displays a plurality of spliced sub-circuit board graphs, the plurality of sub-circuit board graphs are sequentially arranged from left to right after rotating for 90 degrees, and the numbers are arranged at the lower left;
the circuit board graph can be displayed in a highlight mode, when the circuit board is tested to be bad, the bad sub-circuit board graph is displayed in black or red, and the element symbol corresponding to the bad element is displayed in red or black.
2. The method for graphic display of a circuit board test of claim 1, wherein: the circuit board file includes a PCB file or a GERBER file.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710319711.9A CN106959412B (en) | 2017-05-09 | 2017-05-09 | Graphic display method for circuit board test |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710319711.9A CN106959412B (en) | 2017-05-09 | 2017-05-09 | Graphic display method for circuit board test |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106959412A CN106959412A (en) | 2017-07-18 |
| CN106959412B true CN106959412B (en) | 2023-08-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710319711.9A Active CN106959412B (en) | 2017-05-09 | 2017-05-09 | Graphic display method for circuit board test |
Country Status (1)
| Country | Link |
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| CN (1) | CN106959412B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6453435B1 (en) * | 1998-12-29 | 2002-09-17 | Fujitsu Network Communications, Inc. | Method and apparatus for automated testing of circuit boards |
| CN101042422A (en) * | 2006-03-21 | 2007-09-26 | 韦瑞吉（新加坡）私人有限公司 | Graphical presentation of semiconductor test results |
| CN101127054A (en) * | 2006-08-18 | 2008-02-20 | 英业达股份有限公司 | Logic circuitry dot pitch analysis method |
| CN101364174A (en) * | 2007-08-09 | 2009-02-11 | 鸿富锦精密工业（深圳）有限公司 | Test file generation system and method for printed circuit board |
| CN101833608A (en) * | 2010-05-20 | 2010-09-15 | 华为技术有限公司 | Processing method and device of PCB (Printed Circuit Board) data |
| CN102799853A (en) * | 2011-05-27 | 2012-11-28 | 鸿富锦精密工业（深圳）有限公司 | Test point imaging identification system and method of circuit board |
-
2017
- 2017-05-09 CN CN201710319711.9A patent/CN106959412B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6453435B1 (en) * | 1998-12-29 | 2002-09-17 | Fujitsu Network Communications, Inc. | Method and apparatus for automated testing of circuit boards |
| CN101042422A (en) * | 2006-03-21 | 2007-09-26 | 韦瑞吉（新加坡）私人有限公司 | Graphical presentation of semiconductor test results |
| CN101127054A (en) * | 2006-08-18 | 2008-02-20 | 英业达股份有限公司 | Logic circuitry dot pitch analysis method |
| CN101364174A (en) * | 2007-08-09 | 2009-02-11 | 鸿富锦精密工业（深圳）有限公司 | Test file generation system and method for printed circuit board |
| CN101833608A (en) * | 2010-05-20 | 2010-09-15 | 华为技术有限公司 | Processing method and device of PCB (Printed Circuit Board) data |
| CN102799853A (en) * | 2011-05-27 | 2012-11-28 | 鸿富锦精密工业（深圳）有限公司 | Test point imaging identification system and method of circuit board |
Non-Patent Citations (1)
| Title |
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| "用Protel99SE 快速设计印刷电路板的方法";宋卫星等;《电脑知识与技术》;第6卷(第31期);第8890-8891页 * |
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| Publication number | Publication date |
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| CN106959412A (en) | 2017-07-18 |
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