CN106951385B - Serial PWM signal decoding circuit and method based on capacitor charging and discharging structure - Google Patents

Serial PWM signal decoding circuit and method based on capacitor charging and discharging structure Download PDF

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CN106951385B
CN106951385B CN201710166006.XA CN201710166006A CN106951385B CN 106951385 B CN106951385 B CN 106951385B CN 201710166006 A CN201710166006 A CN 201710166006A CN 106951385 B CN106951385 B CN 106951385B
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discharging
charging
capacitor
decoding
charge
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CN106951385A (en
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李智
赵建中
周玉梅
辛卫华
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Ruili Flat Core Microelectronics Guangzhou Co Ltd
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Institute of Microelectronics of CAS
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Computer Hardware Design (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

The invention provides a serial PWM signal decoding circuit based on a capacitor charging and discharging structure, which comprises: the input end of the sequential logic generating circuit receives the PWM differential signal and generates a sequential logic signal; the input ends of the at least two capacitor charging and discharging decoding modules are respectively connected with the output end of the sequential logic generating circuit, and charging and discharging are carried out according to sequential logic signals; the voltage of a charge-discharge capacitor of the capacitor charge-discharge decoding module before charge and discharge in the decoding process is a common-mode voltage VCM, and the voltage of a charge-discharge node after the charge and discharge is finished is VCAnd identifying the PWM signal by judging the polarity of the voltage difference of the two signals so as to decode the signal. The invention also provides a serial PWM signal decoding method based on the capacitor charge-discharge structure. The invention has simple structure, does not need synchronous code stream, avoids the use of complex CDR and oversampling structure, realizes the decoding of PWM signals under different rates, improves the signal transmission efficiency and reduces the power consumption.

Description

Serial PWM signal decoding circuit and method based on capacitor charging and discharging structure
Technical Field
The invention relates to the field of integrated circuit design related to an M-PHY interface, in particular to a serial PWM signal decoding circuit and method based on a capacitor charging and discharging structure.
Background
In the field of serial interfaces, PWM signals are often used for data transmission in low speed mode, such as mipi M _ PHY, and are characterized by a low level time 1/3 in a UI, a high level time 2/3 for data 1, a low level time 2/3, and a high level time 1/3 for data 0. The transmission data rate of the synchronous code transmission device can be changed from several megahertz to several hundred megahertz to meet the requirement of saving power consumption under different data transmission quantity, and meanwhile, the synchronous code is not transmitted under the low-speed mode.
The existing scheme adopts oversampling or realizes the decoding of serial PWM signals based on a CDR structure, but all has the condition that the circuit structure is complex, the redundant power consumption is wasted, the large data rate change range cannot be covered, and even the decoding can be realized only by matching with synchronous codes, so that a PWM signal receiving circuit which has simple structure, low power consumption, adaptation to different working rates and capability of realizing the receiving without synchronous data codes is urgently needed.
Disclosure of Invention
Technical problem to be solved
In view of the above technical problems, the present invention provides a serial PWM signal decoding circuit and method based on a capacitor charging/discharging structure. The invention has simple structure, avoids the use of complex CDR and oversampling structure, realizes the decoding of PWM signals under different speeds by adopting capacitance value programmable charging and discharging capacitance and current value programmable current source, and can realize the decoding of serial PWM signals without synchronous codes, thereby improving the signal transmission efficiency and saving the power consumption.
(II) technical scheme
According to an aspect of the present invention, there is provided a serial PWM signal decoding circuit based on a capacitor charging and discharging structure, including:
the input end of the sequential logic generating circuit receives the PWM differential signal and generates a sequential logic signal according to the input PWM differential signal;
the input ends of the at least two capacitor charging and discharging decoding modules are respectively connected with the output end of the sequential logic generating circuit, receive sequential logic signals sent by the sequential logic generating circuit and carry out charging and discharging according to the sequential logic signals; wherein,
in the decoding process, the voltage of a charge-discharge capacitor of the capacitor charge-discharge decoding module before charge and discharge is a common-mode voltage VCM, and the voltage of a charge-discharge node after the charge and discharge is finished is VCAnd identifying the PWM signal by judging the polarity of the voltage difference of the two signals so as to decode the signal.
Preferably, the sequential logic generating circuit includes: the input port PWM _ P, PWM _ N is used for receiving an input low-voltage differential PWM signal; at least two groups of time sequence logic output ports which are respectively connected with the input ports of the at least two capacitor charge-discharge decoding modules, wherein output signals of the first group of time sequence logic output ports are SWP1, SWN1, SWR1 and SA1 which are respectively used for controlling a charge switch SWP, a discharge switch SWN, a reset switch SWR and an SA port of the first capacitor charge-discharge decoding module; the output signals of the second group of sequential logic output ports are SWP2, SWN2, SWR2 and SA2, which are respectively used for controlling the charging switch SWP, the discharging switch SWN, the reset switch SWR and the SA port of the second capacitor charging and discharging decoding module.
Preferably, the capacitance charging and discharging decoding module includes: charging and discharging capacitor C0The charge and discharge node C is connected with the input end of the common-mode voltage VCM through the switch SWR; current source IchConnected in series with the switch SWP for charging and discharging the capacitor C0Charging is carried out; current source IdisConnected in series with the switch SWN for charging and discharging the capacitor C0Discharging; a comparator having a positive input terminal and the charge/discharge capacitor C0Is connected with the common-mode voltage input end VCM, and is used for judging the voltage VCVoltage difference polarity from common mode voltage VCM; and a DATA input port D of the register is connected with the output end of the comparator, a DATA output port Q of the register is connected with a DATA output end DATA of the capacitor charging and discharging decoding module, and a clock port clk of the register is connected with a port SA of the capacitor charging and discharging decoding module and used for storing a decoding result.
Preferably, when the low level of the PWM signal arrives, SWN is switched off and SWP is switched on, and the current source IchTo charge and discharge capacitor C0Charging is carried out; when the high level of the PWM signal arrives, the SWP is switched off and the SWN is switched on, and the current source IdisTo charge and discharge capacitor C0And discharging is performed.
Preferably, the current source IchAnd a current source IdisAre all programmable current sources, the programmable current sources IchAnd a programmable current source IdisThe current of the PWM signal is changed according to the data rate change of the PWM signal, and the larger the data rate is, the larger the current is; the smaller the opposite.
Preferably, the charge-discharge capacitor C0Is a programmable charge-discharge capacitor C0Volume value according toThe PWM signal data rate changes, and the larger the data rate is, the smaller the capacity value is; the larger the opposite.
Preferably, the serial PWM signal decoding circuit includes two capacitor charge-discharge decoding modules, and the two capacitor charge-discharge decoding modules alternately operate under the control of the sequential logic generating circuit to realize the continuous decoding of the serial PWM signal.
Preferably, the two capacitor charge-discharge decoding modules are respectively a first capacitor charge-discharge decoding module and a second capacitor charge-discharge decoding module; the first capacitor charge-discharge decoding module performs charge-discharge at odd bits of the serial PWM signal, and completes data register output and module reset at even bits; the second capacitor charging and discharging decoding module performs charging and discharging at even bits of the serial PWM signal, and completes data register output and module reset at odd bits; so that the two modules work alternately to realize the continuous decoding of the serial PWM signals.
Preferably, the voltage difference between the charge-discharge node of the charge-discharge capacitor and the common mode voltage VCM is kept consistent at different data rates, that is, the following relation is satisfied:
wherein UI is 1bit data time length, I0 is charge and discharge current, C0 is capacitance of charge and discharge capacitor, const is constant.
According to another aspect of the present invention, there is provided a serial PWM signal decoding circuit based on a capacitor charging and discharging structure for decoding, including:
s1: before the arrival of the PWM signal, a charge-discharge capacitor C of a capacitor charge-discharge decoding module0Resetting the initial voltage value to a common-mode voltage VCM;
s2: when a bit PWM signal arrives, the charge and discharge capacitor C0At bit PWM signal lowAnd respectively charging and discharging in high level period, and the charging and discharging capacitor C0The voltage of the charge-discharge node C when the charge-discharge of the bit PWM signal is finished is VC；
S3: judgment voltage VCVoltage difference from common mode voltage VCMΔThe V-polarity identifies the PWM signal to decode.
(III) advantageous effects
According to the technical scheme, the serial PWM signal decoding circuit and method based on the capacitor charging and discharging structure have at least one of the following beneficial effects:
(1) the invention adopts the sequential logic generating circuit and the capacitance charging and discharging decoding module, can realize the decoding of the serial PWM signal without a synchronous code, has simple structure, avoids the use of complex CDR and an oversampling structure, improves the signal transmission efficiency and saves the power consumption.
(2) The invention adopts the capacitance value programmable charge-discharge capacitor and the current value programmable current source to realize the PWM signal decoding under different speeds.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the accompanying drawings. Like reference numerals refer to like parts throughout the drawings. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.
Fig. 1 is a schematic diagram of a serial PWM signal decoding circuit based on a capacitor charging/discharging structure according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of a capacitor charging/discharging decoding module according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of an operation timing sequence of the capacitor charging/discharging decoding module according to the embodiment of the invention.
FIG. 4 is a schematic diagram of the sequential logic signal output by the sequential logic generating circuit according to the embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
It should be noted that in the drawings or description, the same drawing reference numerals are used for similar or identical parts. Implementations not depicted or described in the drawings are of a form known to those of ordinary skill in the art. Additionally, while exemplifications of parameters including particular values may be provided herein, it is to be understood that the parameters need not be exactly equal to the respective values, but may be approximated to the respective values within acceptable error margins or design constraints. Directional phrases used in the embodiments, such as "upper," "lower," "front," "rear," "left," "right," and the like, refer only to the orientation of the figure. Accordingly, the directional terminology used is intended to be in the nature of words of description rather than of limitation.
Fig. 1 is a schematic diagram of a serial PWM signal decoding circuit based on a capacitor charging/discharging structure according to an embodiment of the present invention. Referring to fig. 1, the serial PWM signal decoding circuit based on the capacitor charging/discharging structure of the present embodiment includes:
the input end of the sequential logic generating circuit receives the PWM differential signal and generates a sequential logic signal according to the input PWM differential signal;
the input ends of the at least two capacitor charging and discharging decoding modules are respectively connected with the output end of the sequential logic generating circuit, receive sequential logic signals sent by the sequential logic generating circuit and carry out charging and discharging according to the sequential logic signals; the voltage of a charge-discharge capacitor of the capacitor charge-discharge decoding module before charge and discharge is a common-mode voltage VCM, and the charge-discharge capacitor after charge and discharge is finishedThe voltage of the charging and discharging node is VCAnd identifying the PWM signal by judging the polarity of the voltage difference of the two signals so as to decode the signal.
Specifically, the serial PWM signal decoding circuit based on the capacitor charging and discharging structure may include two capacitor charging and discharging decoding modules, and the two charging and discharging decoding modules alternately operate under the control of the timing logic generating circuit, so as to realize the continuous decoding of the serial PWM signal.
More specifically, the two capacitor charging and discharging decoding modules are a first capacitor charging and discharging decoding module and a second capacitor charging and discharging decoding module; the first charge-discharge decoding module can charge and discharge at odd bits of the serial PWM signals, and complete data deposit output and module reset at even bits, the second charge-discharge decoding module can charge and discharge at even bits of the serial PWM signals, and complete data deposit output and module reset at odd bits, so that the two modules work alternately to realize continuous decoding of the serial PWM signals. Of course, the working order of the two capacitor charging and discharging decoding modules can be exchanged, and the two capacitor charging and discharging decoding modules can be alternated.
In addition, the serial PWM signal decoding circuit based on the capacitor charging/discharging structure may also include more than three capacitor charging/discharging decoding modules, and the more than three capacitor charging/discharging decoding modules sequentially operate under the control of the sequential logic generating circuit, so that the serial PWM signal can be continuously decoded. Taking three capacitor charge-discharge decoding modules as an example, the three capacitor charge-discharge decoding modules are a first capacitor charge-discharge decoding module, a second capacitor charge-discharge decoding module and a third capacitor charge-discharge decoding module; the first capacitor charge-discharge decoding module can be charged and discharged at a first bit of the serial PWM signal, and data register output and module reset are completed during charge and discharge of the second and third capacitor charge-discharge decoding modules; the second capacitor charging and discharging decoding module can charge and discharge at a second bit of the serial PWM signal, and data register output and module reset are carried out during the charging and discharging of the third capacitor charging and discharging decoding module and the first capacitor charging and discharging decoding module; the third capacitor charging and discharging decoding module can charge and discharge at the third bit of the serial PWM signal, and data register output and module reset are carried out during the charging and discharging of the first and second capacitor charging and discharging decoding modules, so that the three modules alternately work to realize the continuous decoding of the serial PWM signal. Certainly, the working sequence of the capacitor charge-discharge decoding modules can be exchanged, at least one capacitor charge-discharge decoding module is charged and discharged in any bit period, and the rest capacitor charge-discharge decoding modules perform data register output and module reset at the bit.
Referring to fig. 1, the sequential logic generating circuit includes:
the input port PWM _ P, PWM _ N is used for receiving an input low-voltage differential PWM signal;
at least two groups of sequential logic output ports which are respectively connected with the input ports of the at least two capacitance charging and discharging decoding modules, wherein,
the output signals of the first group of sequential logic output ports are respectively SWP1, SWN1, SWR1 and SA 1; the SWP1 is used for controlling a charging switch SWP of the first capacitor charging and discharging decoding module, the SWN1 is used for controlling a discharging switch SWN of the first capacitor charging and discharging decoding module, the SWR1 is used for controlling a reset switch SWR of the first capacitor charging and discharging decoding module, and the SA1 is connected with an SA port of the first capacitor charging and discharging decoding module.
Correspondingly, the output signals of the second group of sequential logic output ports are respectively SWP2, SWN2, SWR2 and SA 2; the SWP2 is used for controlling a charging switch SWP of the second capacitor charging and discharging decoding module, the SWN2 is used for controlling a discharging switch SWN of the second capacitor charging and discharging decoding module, the SWR2 is used for controlling a reset switch SWR of the second capacitor charging and discharging decoding module, and the SA2 is connected with an SA port of the second capacitor charging and discharging decoding module.
FIG. 2 is a circuit diagram of a capacitor charging/discharging decoding module according to an embodiment of the present invention. Referring to fig. 2, the capacitor charging/discharging decoding module of the present embodiment includes:
charging and discharging capacitor C0The charge-discharge node C is connected with the common-mode voltage input end VCM through a switch SWR；
Current source IchConnected in series with a switch SWP for charging and discharging the capacitor C0Charging is carried out;
current source IdisConnected in series with a switch SWN for charging and discharging the capacitor C0Discharging;
a comparator having a positive input terminal and a charge-discharge capacitor C0Is connected to the common mode voltage input VCM, and has its negative input connected to the common mode voltage input VCM.
And a DATA input port D of the register is connected with the output end of the comparator, a DATA output port Q is connected with a DATA output end DATA of the capacitor charge-discharge decoding module, and a clock port clk of the register is connected with a port SA of the capacitor charge-discharge decoding module.
Specifically, when the low level of the PWM signal arrives, the SWR is switched off and the SWP is switched on, and the current source IchTo charge and discharge capacitor C0Charging is carried out; when the high level arrives, the SWP is switched off and the SWN is switched on, and the current source IdisTo charge and discharge capacitor C0And discharging is performed.
The capacitor charging and discharging decoding module judges the voltage V through a comparatorCVoltage difference from common mode voltage VCMΔThe V polarity identifies the PWM signal to decode; and storing the decoding result through a register.
Preferably, the current source IchAnd a current source IdisAre all programmable current sources. The programmable current source IchAnd a programmable current source IdisThe current changes according to the change of the data rate of the PWM signal, and the larger the data rate is, the larger the current is; the smaller the opposite. The charge and discharge capacitor C0Is a programmable charge-discharge capacitor. Wherein the capacitor C is charged and discharged0The capacity value changes according to the change of the data rate of the PWM signal, and the larger the data rate is, the smaller the capacity value is; the larger the opposite.
The working process of the capacitor charging and discharging decoding module according to the embodiment of the invention is described in detail below. Fig. 3 is a schematic diagram of a working timing sequence of the capacitor charging/discharging decoding module according to the embodiment of the invention.
Referring to fig. 3, before the PWM signal arrives, the initial voltage value of the charge/discharge capacitor is the common mode voltage VCM, when the low level of the first bit PWM signal arrives, the SWN is turned off and the SWP is turned on, if the PWM signal is 0, the low level is 2/3UI (UI is 1bit data time length), the high level is 1/3UI, and the charge/discharge capacitor C is charged or discharged0Charging for 2/3 UIs at a charging current I0When high level arrives, SWP is switched off and SWN is switched on to charge and discharge capacitor C0Discharging for 1/3 UIs at a discharge current I0When SWN is turned off, the capacitor C is charged and discharged0Voltage V of charge-discharge node CCWith a positive voltage difference to VCMΔV：
If the PWM signal is 1, i.e. the low level is 1/3UI, the high level is 2/3UI, the charging and discharging capacitor C0Charging for 1/3 UIs and discharging for 2/3 UIs at a charging/discharging current I0When SWN is turned off, the capacitor C is charged and discharged0Voltage V of charge-discharge node CCA negative voltage difference with VCM-ΔV：
After the first bit PWM signal is finished, the voltage of the charging and discharging node C needs to be kept for a period of time t1To ensure the comparator correctly identifiesΔV or-ΔV and outputs the comparison result of the full swing, t after the SA signal ends at the first bit PWM signal1And the register stores and outputs the comparison result of the comparator to DATA under the triggering of the rising edge to finish the decoding of the first bit PWM signal.
SA needs to go low before the second bit PWM signal ends. SWR delay t after SA rising edge2And the register is closed for a period of time after finishing data registering and outputting, the voltage of the charge-discharge capacitor is reset to VCM, the SWR needs to be disconnected before the second bit PWM signal is finished, the capacitor charge-discharge decoding module finishes charge-discharge in the period of the first bit PWM signal, and finishes data registering and outputting and resetting of the module in the period of the second bit PWM signal.
When the input PWM data rate changes, i.e. the value of UI changes, in order to ensure that the decoding effect is not affected by the data rate,Δv or-ΔV should remain consistent at different data rates. Namely:
const is constant, and when the data rate becomes larger, UI becomes smaller, I can be increased0Or lower C0To ensure the normal work of the capacitance charge-discharge decoding module, when the data rate becomes smaller and UI becomes larger, the I can be reduced0Or increasing C0To ensure the normal operation of the capacitor charging and discharging decoding module.
The following describes the output sequential logic process of the sequential logic generating circuit according to the embodiment of the present invention in detail by taking the case of two capacitor charging/discharging decoding modules as an example. FIG. 4 is a schematic diagram of the timing logic signal output by the timing logic generation circuit, before the arrival of the PWM signal, the common mode voltage VCM of the initial voltage values of the charge and discharge capacitors of the first capacitor charge and discharge decoding module is generated, when the low level of the first bit PWM signal arrives, the SWR1 is turned off and the SWP1 is turned on, the charge and discharge capacitors of the first capacitor charge and discharge decoding module are charged during the low level, when the high level arrives, the SWP1 is turned off and the SWN1 is turned on, the charge and discharge capacitors of the first capacitor charge and discharge decoding module are discharged during the high level, after the high level arrives, the SWN1 is turned off to complete the charge and discharge process1To ensure that the comparator outputs the correct comparison result, the SA1 signal is at the first bit PWM signalT after the number is over1And the register stores and outputs the comparison result of the comparator to DATA under the triggering of the rising edge to finish the decoding of the first bitPWM signal.
The SA1 needs to go low before the second bit signal ends. SWR1 time delay t after SA1 rising edge2And the register is closed for a period of time after finishing data registering and outputting, the voltage of the charge-discharge capacitor is reset to VCM, the SWR1 needs to be disconnected before the second bit PWM signal is finished, the first capacitor charge-discharge decoding module finishes charge-discharge in the period of the first bit PWM signal, and finishes data registering and outputting and resetting of the module in the period of the second bit PWM signal.
The second capacitor charging and discharging decoding module completes initialization in the period of the first bit PWM signal, when the low level of the second bit PWM signal arrives, the SWR2 is disconnected and the SWP2 is closed, the charging and discharging capacitor of the second capacitor charging and discharging decoding module is charged in the period of the low level, when the high level arrives, the SWP2 is disconnected and the SWN2 is closed, the charging and discharging capacitor of the first capacitor charging and discharging decoding module is discharged in the period of the high level, after the high level arrives, the SWN2 is disconnected, the charging and discharging process is completed, and a period of time t passes1To ensure that the comparator outputs a correct comparison result, the SA2 signal is t after the first bit PWM signal is over1And the register stores and outputs the comparison result of the comparator to DATA under the triggering of the rising edge to finish the decoding of the first bit PWM signal.
The SA2 needs to go low before the second bit signal ends. SWR2 time delay t after SA2 rising edge2And the register is closed for a period of time after finishing data registering and outputting, the voltage of the charge-discharge capacitor is reset to VCM, the SWR2 needs to be disconnected before the third bit PWM signal is finished, the second capacitor charge-discharge decoding module finishes charge-discharge in the second bit PWM signal period, and finishes data registering and outputting and resetting of the module in the third bit PWM signal period.
The two capacitor charging and discharging decoding modules work alternately under the control of the time sequence logic generating circuit, the first capacitor charging and discharging decoding module performs charging and discharging at an odd number bit of the serial PWM signal, data register output and module resetting are completed at an even number bit, the second capacitor charging and discharging decoding module performs charging and discharging at the even number bit of the serial PWM signal, data register output and module resetting are completed at the odd number bit, and continuous decoding of the serial PWM signal can be realized through alternate work of the two modules.
In addition, an embodiment of the present invention further provides a serial PWM signal decoding method, including:
s1: before the arrival of the PWM signal, a charge-discharge capacitor C of a capacitor charge-discharge decoding module0Resetting the initial voltage value to a common-mode voltage VCM;
s2: when a bit PWM signal arrives, the charge and discharge capacitor C0Respectively charging and discharging in the low and high level periods of the bit PWM signal, and the charging and discharging capacitor C0The voltage of the charge-discharge node C when the charge-discharge of the bit PWM signal is finished is VC；
S3: judgment voltage VCVoltage difference from common mode voltage VCMΔThe V-polarity identifies the PWM signal to decode.
In the present invention, all sequential logic generating circuits capable of generating and driving the at least two capacitor charging and discharging decoding modules to complete decoding operations can be used in the serial PWM signal decoding circuit based on the capacitor charging and discharging structure of the present invention, and no matter what way the sequential logic generating circuit is specifically implemented, the present invention falls within the protection scope of the claims of the present invention.
The serial PWM signal decoding circuit and method based on the capacitor charging and discharging structure have the advantages that the structure is simple, the use of a complex CDR and oversampling structure is avoided, and the PWM signal decoding under different rates is realized by adopting the capacitor value programmable charging and discharging capacitor and the current value programmable current source. Meanwhile, the PWM signal decoding circuit can completely decode all received PWM signals without synchronous code streams, so that the signal transmission efficiency is improved, and the power consumption is reduced.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. Furthermore, the above definitions of the various elements and methods are not limited to the particular structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by one of ordinary skill in the art, for example:
the charge-discharge decoding module can also discharge in the low level period of the PWM signal and charge in the high level period, and the invention can also be realized.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (8)

1. A serial PWM signal decoding circuit based on a capacitor charging and discharging structure is characterized by comprising:
the input end of the sequential logic generating circuit receives the PWM differential signal and generates a sequential logic signal according to the input PWM differential signal;
the input ends of the at least two capacitor charging and discharging decoding modules are respectively connected with the output end of the sequential logic generating circuit, receive sequential logic signals sent by the sequential logic generating circuit and carry out charging and discharging according to the sequential logic signals; wherein,
in the decoding process, the voltage of a charge-discharge capacitor of the capacitor charge-discharge decoding module before charge and discharge is a common-mode voltage VCM, and the voltage of a charge-discharge node after the charge and discharge is finished is VCIdentifying the PWM signal by judging the polarity of the voltage difference of the two signals so as to decode the signal; wherein,
the capacitance charging and discharging decoding module comprises:
charging and discharging capacitor C0The charge-discharge node C is connected with the input end of the common-mode voltage VCM through a reset switch SWR;
current source IchAnd a series charging switch SWP for charging and discharging the capacitor C0Charging is carried out;
current source IdisA series discharge switch SWN for charging and discharging the capacitor C0Discharging;
a comparator having a positive input terminal and the charge/discharge capacitor C0Is connected with the common-mode voltage input end VCM, and is used for judging the voltage VCVoltage difference polarity from common mode voltage VCM;
a DATA input port D of the register is connected with the output end of the comparator, a DATA output port Q of the register is connected with a DATA output end DATA of the capacitor charging and discharging decoding module, and a clock port clk of the register is connected with a port SA of the capacitor charging and discharging decoding module and used for storing a decoding result;
the at least two capacitor charging and discharging decoding modules alternately work under the control of the sequential logic generating circuit to realize the continuous decoding of the serial PWM signals;
the voltage V of the charge and discharge node of the charge and discharge capacitorCThe voltage difference with the common-mode voltage VCM is consistent at different data rates, i.e. the following relation is satisfied:
wherein UI is 1bit data time length, I0For charging and discharging current, C0For charging and discharging capacitorsThe capacitance const of (1) is constant.
2. The serial PWM signal decoding circuit according to claim 1, wherein the sequential logic generating circuit comprises:
the input port PWM _ P, PWM _ N is used for receiving an input low-voltage differential PWM signal;
at least two groups of sequential logic output ports which are respectively connected with the input ports of the at least two capacitance charging and discharging decoding modules, wherein,
output signals of the first group of sequential logic output ports are SWP1, SWN1, SWR1 and SA1, which are respectively used for controlling a charging switch SWP, a discharging switch SWN, a reset switch SWR and a port SA of the first capacitor charging and discharging decoding module;
the output signals of the second group of sequential logic output ports are SWP2, SWN2, SWR2 and SA2, which are respectively used for controlling the charging switch SWP, the discharging switch SWN, the reset switch SWR and the port SA of the second capacitor charging and discharging decoding module.
3. The serial PWM signal decoding circuit based on the capacitor charging and discharging structure as claimed in claim 2, wherein when the low level of the PWM signal arrives, the discharging switch SWN is turned off and the charging switch SWP is turned on, and the current source I is connected to the charging and discharging circuitchTo charge and discharge capacitor C0Charging is carried out; when the high level of the PWM signal arrives, the charging switch SWP is switched off and the discharging switch SWN is switched on, and the current source IdisTo charge and discharge capacitor C0And discharging is performed.
4. The serial PWM signal decoding circuit based on the capacitor charging and discharging structure as claimed in claim 2, wherein the current source I ischAnd a current source IdisAre all programmable current sources, the programmable current sources IchAnd a programmable current source IdisThe current of the PWM signal is changed according to the data rate change of the PWM signal, and the larger the data rate is, the larger the current is; the smaller the opposite.
5. The serial PWM signal decoding circuit based on the capacitor charging and discharging structure according to claim 2, wherein the charging and discharging capacitor C0Is a programmable charge-discharge capacitor C0The capacity value changes according to the change of the data rate of the PWM signal, and the larger the data rate is, the smaller the capacity value is; the larger the opposite.
6. The serial PWM signal decoding circuit based on the capacitor charging and discharging structure as claimed in claim 2, wherein the serial PWM signal decoding circuit comprises two capacitor charging and discharging decoding modules, and the two capacitor charging and discharging decoding modules alternately work under the control of the sequential logic generating circuit to realize the continuous decoding of the serial PWM signal.
7. The serial PWM signal decoding circuit based on the capacitor charging and discharging structure according to claim 6, wherein the two capacitor charging and discharging decoding modules are a first capacitor charging and discharging decoding module and a second capacitor charging and discharging decoding module respectively; wherein,
the first capacitor charging and discharging decoding module performs charging and discharging at odd bits of the serial PWM signal, and completes data register output and module reset at even bits;
the second capacitor charging and discharging decoding module performs charging and discharging at even bits of the serial PWM signal, and completes data register output and module reset at odd bits; therefore, the two capacitor charging and discharging decoding modules work alternately to realize continuous decoding of the serial PWM signals.
8. A method for decoding by using the serial PWM signal decoding circuit based on the capacitor charging and discharging structure according to any one of claims 1 to 7, comprising:
s1: before the arrival of the PWM signal, a charge-discharge capacitor C of a capacitor charge-discharge decoding module0Resetting the initial voltage value to a common-mode voltage VCM;
s2: when a bit PWM signalWhen coming, the charge and discharge capacitor C0Respectively charging and discharging in the low and high level periods of the bit PWM signal, and the charging and discharging capacitor C0The voltage of the charge-discharge node C when the charge-discharge of the bit PWM signal is finished is VC；
S3: judgment voltage VCThe voltage difference Δ V from the common mode voltage VCM identifies the PWM signal for decoding.
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