CN106951385B - Serial pwm signal decoding circuit and method based on capacitor charge and discharge structure - Google Patents
Serial pwm signal decoding circuit and method based on capacitor charge and discharge structure Download PDFInfo
- Publication number
- CN106951385B CN106951385B CN201710166006.XA CN201710166006A CN106951385B CN 106951385 B CN106951385 B CN 106951385B CN 201710166006 A CN201710166006 A CN 201710166006A CN 106951385 B CN106951385 B CN 106951385B
- Authority
- CN
- China
- Prior art keywords
- discharge
- charge
- pwm signal
- capacitor
- capacitor charge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention provides a kind of serial pwm signal decoding circuit based on capacitor charge and discharge structure, comprising: sequential logic generation circuit, input terminal receives PWM differential signal, and generates sequential logic signal；At least two capacitor charge and discharge decoder modules, input terminal are connect with the output end of sequential logic generation circuit respectively, carry out charge and discharge according to sequential logic signal；Voltage of the charge and discharge capacitance of capacitor charge and discharge decoder module before charge and discharge is common-mode voltage VCM in decoding process, and the voltage of charge and discharge electrical nodes is V after charge and dischargeC, decoded by the voltage difference polarity identification pwm signal of both judgements.The present invention also provides a kind of serial pwm signal coding/decoding method based on capacitor charge and discharge structure.The configuration of the present invention is simple avoids the use of complicated CDR and over-sampling structure without synchronous code stream, realizes the pwm signal decoding under different rates, improving effectiveness reduces power consumption.
Description
Technical field
The present invention relates to the interface related IC design fields of M-PHY, more particularly to one kind to be based on capacitor charge and discharge
The serial pwm signal decoding circuit and method of structure.
Background technique
In field of serial interfaces, transmitted frequently with pwm signal for the data under low-speed mode, such as mipi M_PHY,
The characteristics of signal is that low level time accounts for 1/3 in a UI, and high level accounts for and 2/3 represents data 1, low level time accounts for 2/3, high
Level accounts for 1/3 and represents data 0.Its transmission data rate variation range is from several megahertzs to several hundred megahertzs, to adapt to different data
The demand of power consumption is saved under transmission quantity, while there is the case where not sending synchronous code in the low-speed mode.
Current existing scheme uses over-sampling, or the decoding of serial pwm signal is realized based on CDR structure, but all deposit
In circuit structure complexity, redundancy power consumption is wasted, big data rate variation range can not be covered, or even synchronous code must be cooperated real
Therefore the case where now decoding needs that a kind of structure is simple, and power consumption is lower, adapt to different operating rate, while without synchrodata
Code is able to achieve received pwm signal and receives circuit.
Summary of the invention
(1) technical problems to be solved
In view of above-mentioned technical problem, the serial pwm signal decoding based on capacitor charge and discharge structure that the present invention provides a kind of
Circuit and method.The configuration of the present invention is simple, avoids complicated CDR, and the use of over-sampling structure is in addition programmable using capacitance
Charge and discharge capacitance and current value programmable current source realize the decoding of the pwm signal under different rates, while without synchronous code
The decoding that serial pwm signal can be realized, improves effectiveness, has saved power consumption.
(2) technical solution
According to an aspect of the invention, there is provided a kind of serial pwm signal based on capacitor charge and discharge structure decodes electricity
Road, comprising:
Sequential logic generation circuit, input terminal receives PWM differential signal, and is generated according to the PWM differential signal of input
Sequential logic signal；
At least two capacitor charge and discharge decoder modules, the input terminal output end with the sequential logic generation circuit respectively
Connection receives the sequential logic signal of sequential logic generation circuit transmission, and carries out charge and discharge according to the sequential logic signal；
Wherein,
Voltage of the charge and discharge capacitance of capacitor charge and discharge decoder module described in decoding process before charge and discharge is common mode
Voltage VCM, the voltage of charge and discharge electrical nodes is V after charge and dischargeC, believed by the voltage difference polarity identification PWM of both judgements
Number to decoding.
Preferably, the sequential logic generation circuit, comprising: input port PWM_P, PWM_N is for receiving input low
Press differential PWM signal；At least two groups Sequential logic output port, respectively at least two capacitor charge and discharges decoder module
Input port connection, wherein the output signal of first group of Sequential logic output port is SWP1, SWN1, SWR1 and SA1, difference
For controlling the charge switch SWP, discharge switch SWN, the end reset switch SWR and SA of first capacitor charge and discharge decoder module
Mouthful；The output signal of second group of Sequential logic output port is SWP2, SWN2, SWR2 and SA2, is respectively used to the second capacitor of control
The charge switch SWP of charge and discharge decoder module, discharge switch SWN, the port reset switch SWR and SA.
Preferably, the capacitor charge and discharge decoder module, comprising: charge and discharge capacitance C0, charge and discharge electrical nodes C and common mode are electric
VCM input terminal is pressed to pass through the switch SWR connection；Current source Ich, the switch SWP that connects is for charge and discharge capacitance C0Into
Row charging；Current source Idis, the switch SWN that connects is for charge and discharge capacitance C0It discharges；Comparator, positive input
End and the charge and discharge capacitance C0Charge and discharge electrical nodes C be connected, negative input end is connect with the common-mode voltage input terminal VCM,
For judging voltage VCWith the voltage difference polarity of common-mode voltage VCM；Register, data-in port D and the comparator
Output end connection, data-out port Q are connected with the data output end DATA of the capacitor charge and discharge decoder module, clock
Port clk is connected with the port SA of the capacitor charge and discharge decoder module, for storing decoding result.
Preferably, when pwm signal low level arrives, SWN disconnects SWP closure simultaneously, the current source IchTo charge and discharge
Capacitor C0It charges；When pwm signal high level arrives, SWP disconnects SWN closure simultaneously, the current source IdisTo charge and discharge
Capacitor C0It discharges.
Preferably, the current source IchWith current source IdisIt is programmable current source, programmable current source IchWith can
Program current source IdisElectric current according to pwm signal data transfer rate change and change, data transfer rate more high current is bigger；Otherwise it is smaller.
Preferably, the charge and discharge capacitance C0To may be programmed charge and discharge capacitance, charge and discharge capacitance C0Capacitance is believed according to PWM
Number rate changes and changes, and the bigger capacitance of data transfer rate is smaller；Otherwise it is bigger.
Preferably, the serial pwm signal decoding circuit includes two capacitor charge and discharge decoder modules, which fills
Electric discharge decoder module works alternatively under the control of sequential logic generation circuit, realizes the continuous decoding of serial pwm signal.
Preferably, described two capacitor charge and discharge decoder modules are respectively first capacitor charge and discharge decoder module and the second electricity
Hold charge and discharge decoder module；Wherein, first capacitor charge and discharge decoder module carries out charge and discharge in the odd number bit of serial pwm signal,
Data register output and the reset of module are completed in even number bit；Second capacitor charge and discharge decoder module is in serial pwm signal
Even number bit carries out charge and discharge, completes data register output and the reset of module in odd number bit；To which two modules replace work
Make the continuous decoding of the serial pwm signal of realization.
Preferably, the voltage VC of the charge and discharge electrical nodes of the charge and discharge capacitance is from the voltage difference of common-mode voltage VCM in different numbers
According to being consistent under rate, that is, meet following relationship:
Wherein, UI is 1bit data time length, and I0 is charging and discharging currents, and C0 is the capacitor of charge and discharge capacitance, and const is
Constant.
According to another aspect of the present invention, a kind of serial pwm signal decoding based on capacitor charge and discharge structure is provided
The method that circuit is decoded, comprising:
S1: before pwm signal arrival, by the charge and discharge capacitance C of a capacitor charge and discharge decoder module0Initial voltage value weight
It is set to common-mode voltage VCM；
S2: when a bit pwm signal arrives, the charge and discharge capacitance C0The bit pwm signal is low, between high period
Charge and discharge, the charge and discharge capacitance C are carried out respectively0The electricity of charge and discharge electrical nodes C when the bit pwm signal charge and discharge are completed
Pressure is VC；
S3: judge voltage VCWith common-mode voltage VCM voltage differenceΔV polarity identification pwm signal is to decode.
(3) beneficial effect
It can be seen from the above technical proposal that the present invention is based on the serial pwm signal decoding circuits of capacitor charge and discharge structure
And method at least has the advantages that one of them:
(1) present invention uses sequential logic generation circuit and capacitor charge and discharge decoder module, can be real without synchronous code
The now decoding of serial pwm signal, structure is simple, avoids complicated CDR, and the use of over-sampling structure improves signal transmission
Efficiency has saved power consumption.
(2) present invention may be programmed charge and discharge capacitance and current value programmable current source using capacitance, realize not synchronized
Pwm signal decoding under rate.
Detailed description of the invention
By the way that shown in attached drawing, above and other purpose of the invention, feature and advantage will be more clear.In all the attached drawings
Identical appended drawing reference indicates identical part.Attached drawing deliberately is not drawn by actual size equal proportion scaling, it is preferred that emphasis is is shown
Purport of the invention out.
Fig. 1 is the serial pwm signal decoding circuit structural representation based on capacitor charge and discharge structure according to an embodiment of the present invention
Figure.
Fig. 2 is capacitor charge and discharge decoder module circuit diagram according to an embodiment of the present invention.
Fig. 3 is capacitor charge and discharge decoder module working sequence schematic diagram according to an embodiment of the present invention.
Fig. 4 is sequential logic generation circuit output timing logical signal schematic diagram according to an embodiment of the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in more detail.
It should be noted that similar or identical part all uses identical figure number in attached drawing or specification description.It is attached
The implementation for not being painted or describing in figure is form known to a person of ordinary skill in the art in technical field.In addition, though this
Text can provide the demonstration of the parameter comprising particular value, it is to be understood that parameter is equal to corresponding value without definite, but can connect
It is similar to be worth accordingly in the error margin or design constraint received.The direction term mentioned in embodiment, for example, "upper", "lower",
"front", "rear", "left", "right" etc. are only the directions with reference to attached drawing.Therefore, the direction term used is for illustrating not to use
To limit the scope of the invention.
Fig. 1 is the serial pwm signal decoding circuit structural representation based on capacitor charge and discharge structure according to an embodiment of the present invention
Figure.Please refer to Fig. 1, serial pwm signal decoding circuit of the present embodiment based on capacitor charge and discharge structure, comprising:
Sequential logic generation circuit, input terminal receives PWM differential signal, and is generated according to the PWM differential signal of input
Sequential logic signal；
At least two capacitor charge and discharge decoder modules, the input terminal output end with the sequential logic generation circuit respectively
Connection receives the sequential logic signal of sequential logic generation circuit transmission, and carries out charge and discharge according to the sequential logic signal；
Wherein, voltage of the charge and discharge capacitance of the capacitor charge and discharge decoder module before charge and discharge is common-mode voltage VCM, charge and discharge
After the charge and discharge capacitance charge and discharge electrical nodes voltage be VC, pass through the voltage difference polarity identification PWM of both judgements
Signal is to decode.
Specifically, the serial pwm signal decoding circuit based on capacitor charge and discharge structure may include two capacitor charge and discharges
Electric decoder module, two charge and discharge decoder modules work alternatively under the control of sequential logic generation circuit, realize serial PWM letter
Number continuous decoding.
More specifically, described two capacitor charge and discharge decoder modules are first capacitor charge and discharge decoder module and the second electricity
Hold charge and discharge decoder module；Wherein, first charge and discharge decoder module can carry out charge and discharge in the odd number bit of serial pwm signal,
Data register output and the reset of module are completed in even number bit, second charge and discharge decoder module can be in serial pwm signal
Even number bit carries out charge and discharge, data register output and the reset of module is completed in odd number bit, so that two modules replace work
Make the continuous decoding of the serial pwm signal of realization.It is of course also possible to by the job order tune of two capacitor charge and discharge decoder modules
It changes, alternately.
In addition, the serial pwm signal decoding circuit based on capacitor charge and discharge structure also may include three or more
Capacitor charge and discharge decoder module, three or more the capacitor charge and discharge decoder module sequences under the control of sequential logic generation circuit
It successively works, the continuous decoding of serial pwm signal can be realized.By taking three capacitor charge and discharge decoder modules as an example, described three
Capacitor charge and discharge decoder module is first capacitor charge and discharge decoder module, the second capacitor charge and discharge decoder module, third capacitor fill
Discharge decoder module；Wherein, first capacitor charge and discharge decoder module can carry out charge and discharge in the first bit of serial pwm signal,
Data register output and the reset of module are completed during second and third capacitor charge and discharge decoder module charge and discharge；Second capacitor fills
The decoder module that discharges can carry out charge and discharge in the 2nd bit of serial pwm signal, fill in third, a capacitor charge and discharge decoder module
Data register output and the reset of module are carried out during electric discharge；Third capacitor charge and discharge decoder module can be in serial pwm signal
The 3rd bit carry out charge and discharge, during the first and second capacitor charge and discharge decoder module charge and discharge carry out data register output and
The reset of module, so that three modules work alternatively the continuous decoding for realizing serial pwm signal.It can certainly be by capacitor charge and discharge
The job order of electric decoder module is exchanged, at least one capacitor charge and discharge decoder module during any bit is only needed to carry out charge and discharge,
Remaining capacitor charge and discharge decoder module carries out data register output and the reset of module in the bit simultaneously.
Please continue to refer to Fig. 1, the sequential logic generation circuit, comprising:
Input port PWM_P, PWM_N, low-voltage differential pwm signal for receiving input；
At least two groups Sequential logic output port, respectively with the input terminal of at least two capacitor charge and discharges decoder module
Mouth connection, wherein
The output signal of first group of Sequential logic output port is respectively SWP1, SWN1, SWR1, SA1；SWP1 is for controlling
The charge switch SWP, SWN1 of first capacitor charge and discharge decoder module are used to control the electric discharge of first capacitor charge and discharge decoder module
Switch SWN, SWR1 is used to control the reset switch SWR, SA1 of first capacitor charge and discharge decoder module and first capacitor charge and discharge is electrolysed
The code port module SA is connected.
Correspondingly, the output signal of second group of Sequential logic output port is respectively SWP2, SWN2, SWR2, SA2；SWP2
Charge switch SWP, SWN2 for controlling the second capacitor charge and discharge decoder module decode mould for controlling the second capacitor charge and discharge
The discharge switch SWN, SWR2 of block are used to control the reset switch SWR, SA2 and the second capacitor of the second capacitor charge and discharge decoder module
The charge and discharge port decoder module SA is connected.
Fig. 2 is capacitor charge and discharge decoder module circuit diagram according to an embodiment of the present invention.Referring to figure 2., the present embodiment capacitor
Charge and discharge decoder module, comprising:
Charge and discharge capacitance C0, charge and discharge electrical nodes C connect with common-mode voltage input terminal VCM by a switch SWR；
Current source Ich, one switch SWP of series connection is for charge and discharge capacitance C0It charges；
Current source Idis, one switch SWN of series connection is for charge and discharge capacitance C0It discharges；
Comparator, positive input terminal and charge and discharge capacitance C0Charge and discharge electrical nodes C be connected, negative input end and common-mode voltage
Input terminal VCM connection.
The output end of register, data-in port D and comparator connects, and data-out port Q is filled with the capacitor
The decoder module data output end DATA that discharges is connected, and clock port clk is connected with the port SA of capacitor charge and discharge decoder module.
Specifically, SWR disconnects SWP closure simultaneously, the current source I when pwm signal low level arriveschTo charge and discharge
Capacitor C0It charges；When high level arrives, SWP disconnects SWN closure simultaneously, the current source IdisTo charge and discharge capacitance C0Into
Row electric discharge.
The capacitor charge and discharge decoder module judges voltage V by comparatorCWith common-mode voltage VCM voltage differenceΔV polarity
Identification pwm signal is to decode；It is stored by register pair decoding result.
Preferably, the current source IchWith current source IdisIt is programmable current source.The programmable current source IchWith
Programmable current source IdisElectric current changes according to pwm signal data transfer rate and is changed, and data transfer rate more high current is bigger；Otherwise it is smaller.Institute
State charge and discharge capacitance C0To may be programmed charge and discharge capacitance.Wherein charge and discharge capacitance C0Capacitance changes according to pwm signal data transfer rate and is become
Change, the bigger capacitance of data transfer rate is smaller；Otherwise it is bigger.
The capacitor charge and discharge decoder module course of work of the embodiment of the present invention is described in detail below.Fig. 3 is the embodiment of the present invention
Capacitor charge and discharge decoder module working sequence schematic diagram.
Referring to figure 3., before pwm signal arrival, charge and discharge capacitance initial voltage value is common-mode voltage VCM, when first
When the low level of bit pwm signal arrives, SWN disconnects SWP closure simultaneously, if pwm signal is 0, i.e., low level is 2/3UI (UI
For 1bit data time length), high level 1/3UI, charge and discharge capacitance C0The time of 2/3 UI is undergone to charge, charging current
For I0, when high level arrives, SWP disconnects SWN simultaneously and is closed charge and discharge capacitance C0The time of 1/3 UI is undergone to discharge, electric discharge electricity
Stream is I0, SWN disconnects, charge and discharge capacitance C at this time0Charge and discharge electrical nodes C voltage VCThere are a positive electricity pressure differences with VCMΔV:
If pwm signal is 1, i.e., low level is 1/3UI, high level 2/3UI, charge and discharge capacitance C0Undergo 1/3 UI's
Time charging and the time electric discharge of 2/3 UI, charging and discharging currents I0, SWN disconnects, charge and discharge capacitance C at this time0Charge and discharge
The voltage V of node CCThere are a negative electricity pressure differences-with VCMΔV:
After first bit pwm signal, the voltage of charge and discharge electrical nodes C need to keep a period of time t1To ensure comparator just
Really identificationΔV or-ΔV and the comparison result for exporting the full amplitude of oscillation, t of SA signal after the first bit pwm signal1Moment hair
Comparator comparison result is stored under the triggering of this rising edge and is exported to DATA, completed by raw rising edge modulation, register
The decoding of first bit pwm signal.
SA need to be lower before the 2nd bit pwm signal terminates.SWR is delayed t after SA rising edge2Ensure that register is complete
At a period of time is closed after data register and output, charge and discharge capacitance voltage is set to VCM again, SWR need to be in the 2nd bit PWM
Signal disconnects before terminating, and capacitor charge and discharge decoder module completes charge and discharge during the first bit pwm signal, and second
Data register output and the reset of module are completed during bit pwm signal.
When input PWM count changes according to rate, i.e. the value of UI changes, in order to ensure decoding effect is not by data transfer rate
It influences,ΔV or-ΔV should be consistent under different data rate.That is:
Const is constant, when the data transfer rate UI that becomes larger becomes smaller, can pass through and increase I0Or reduce C0To ensure capacitor charge and discharge
The normal work of electric decoder module, when the data transfer rate UI that becomes smaller becomes larger, can pass through reduces I0Or increase C0To ensure capacitor charge and discharge
The normal work of electric decoder module.
Below in case where two capacitor charge and discharge decoder modules, the production of sequential logic of the embodiment of the present invention is discussed in detail
Raw circuit output sequential logic process.Fig. 4 is sequential logic generation circuit output timing logical signal schematic diagram, in pwm signal
First capacitor charge and discharge decoder module charge and discharge capacitance initial voltage value common-mode voltage VCM before arrival, when the first bit PWM believes
Number low level arrive when, SWR1 disconnect simultaneously SWP1 closure, first capacitor charge and discharge decoder module charge and discharge capacitance is in low electricity
Flat period charges, and when high level arrives, SWP1 disconnects SWN1 simultaneously and is closed first capacitor charge and discharge decoder module charge and discharge
Capacitor discharges between high period, and SWN1 is disconnected after high level beam, charging and discharging process is completed, through t after a period of time1
To ensure that comparator exports correct comparison result, t of SA1 signal after the first bit pwm signal1Rising edge occurs for the moment
Comparator comparison result is stored under the triggering of this rising edge and is exported to DATA by modulation, register, completes first
The decoding of bitPWM signal.
SA1 need to be lower before the 2nd bit signal terminates.SWR1 is delayed t after SA1 rising edge2Ensure that register is complete
At a period of time is closed after data register and output, charge and discharge capacitance voltage is set to VCM again, SWR1 need to be in the 2nd bit
Pwm signal disconnects before terminating, and first capacitor charge and discharge decoder module completes charge and discharge during the first bit pwm signal, and
Data register output and the reset of module are completed during the 2nd bit pwm signal.
The second capacitor charge and discharge decoder module completes initialization during the first bit pwm signal, when the 2nd bit PWM believes
Number low level arrive when, SWR2 disconnect simultaneously SWP2 closure, the charge and discharge capacitance of the second capacitor charge and discharge decoder module is low
It charges during level, when high level arrives, SWP2 disconnects SWN2 simultaneously and is closed first capacitor charge and discharge decoder module
Charge and discharge capacitance discharges between high period, and SWN2 is disconnected after high level beam, charging and discharging process is completed, when by one section
Between t1To ensure that comparator exports correct comparison result, t of SA2 signal after the first bit pwm signal1In moment generation
It rises along modulation, comparator comparison result is stored under the triggering of this rising edge and exported to DATA by register, completes first
The decoding of bit pwm signal.
SA2 need to be lower before the 2nd bit signal terminates.SWR2 is delayed t after SA2 rising edge2Ensure that register is complete
At a period of time is closed after data register and output, charge and discharge capacitance voltage is set to VCM again, SWR2 need to be in the 3rd bit
Pwm signal disconnects before terminating, and the second capacitor charge and discharge decoder module completes charge and discharge during the 2nd bit pwm signal, and
Data register output and the reset of module are completed during the 3rd bit pwm signal.
Two capacitor charge and discharge decoder modules work alternatively under the control of sequential logic generation circuit, first capacitor charge and discharge
Electric decoder module carries out charge and discharge in the odd number bit of serial pwm signal, completes data register output and module in even number bit
Reset, the second capacitor charge and discharge decoder module serial pwm signal even number bit carry out charge and discharge, odd number bit complete number
According to deposit output and the reset of module, two modules work alternatively the continuous decoding that serial pwm signal can be realized.
In addition, the embodiment of the invention also provides a kind of serial pwm signal coding/decoding methods, comprising:
S1: before pwm signal arrival, by the charge and discharge capacitance C of a capacitor charge and discharge decoder module0Initial voltage value weight
It is set to common-mode voltage VCM；
S2: when a bit pwm signal arrives, the charge and discharge capacitance C0The bit pwm signal is low, between high period
Charge and discharge, the charge and discharge capacitance C are carried out respectively0The electricity of charge and discharge electrical nodes C when the bit pwm signal charge and discharge are completed
Pressure is VC；
S3: judge voltage VCWith common-mode voltage VCM voltage differenceΔV polarity identification pwm signal is to decode.
In the present invention, it is all can generate drive above-mentioned at least two capacitor charge and discharges decoder module complete decoding efforts when
Sequence logic generation circuit may be incorporated for the serial pwm signal decoding circuit of the invention based on capacitor charge and discharge structure no matter
Sequential logic generation circuit is specifically realized in which way, is belonged within claims of the invention.
Serial pwm signal decoding circuit and method of the embodiment of the present invention based on capacitor charge and discharge structure, structure is simple, keeps away
Complicated CDR is exempted from, the use of over-sampling structure may be programmed charge and discharge capacitance and current value programmable current source using capacitance
To realize the decoding of the pwm signal under different rates.The pwm signal decoding circuit can be completely real without synchronous code stream simultaneously
Decoding now is realized to all pwm signals received, therefore improve effectiveness to reduce power consumption.
The foregoing description of the disclosed embodiments makes professional and technical personnel in the field can be realized or use the application.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the application.Therefore, the application
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
It should be noted that in attached drawing or specification text, the implementation for not being painted or describing is affiliated technology
Form known to a person of ordinary skill in the art, is not described in detail in field.In addition, the above-mentioned definition to each element and method is simultaneously
It is not limited only to various specific structures, shape or the mode mentioned in embodiment, those of ordinary skill in the art can carry out letter to it
It singly changes or replaces, such as:
The charge and discharge decoder module can also discharge between pwm signal low period, charge between high period,
The present invention equally may be implemented.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical scheme and beneficial effects
It describes in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in guarantor of the invention
Within the scope of shield.
Claims (8)
1. a kind of serial pwm signal decoding circuit based on capacitor charge and discharge structure characterized by comprising
Sequential logic generation circuit, input terminal receives PWM differential signal, and generates timing according to the PWM differential signal of input
Logical signal；
At least two capacitor charge and discharge decoder modules, input terminal connect with the output end of the sequential logic generation circuit respectively
It connects, receives the sequential logic signal of sequential logic generation circuit transmission, and charge and discharge are carried out according to the sequential logic signal；Its
In,
Voltage of the charge and discharge capacitance of capacitor charge and discharge decoder module described in decoding process before charge and discharge is common-mode voltage
VCM, the voltage of charge and discharge electrical nodes is V after charge and dischargeC, by judgement both voltage difference polarity identification pwm signal from
And it decodes；Wherein,
The capacitor charge and discharge decoder module, comprising:
Charge and discharge capacitance C0, charge and discharge electrical nodes C connect with common-mode voltage VCM input terminal by reset switch SWR；
Current source Ich, serial connection charge switch SWP is for charge and discharge capacitance C0It charges；
Current source Idis, discharged in series switch SWN is for charge and discharge capacitance C0It discharges；
Comparator, positive input terminal and the charge and discharge capacitance C0Charge and discharge electrical nodes C be connected, negative input end and the common mode
Voltage input end VCM connection, for judging voltage VCWith the voltage difference polarity of common-mode voltage VCM；
Register, data-in port D are connect with the output end of the comparator, data-out port Q and the capacitor
The data output end DATA of charge and discharge decoder module is connected, the end of clock port clk and the capacitor charge and discharge decoder module
Mouth SA is connected, for storing decoding result；
At least two capacitor charge and discharges decoder module works alternatively under the control of sequential logic generation circuit, realizes serial
The continuous decoding of pwm signal；
The voltage V of the charge and discharge electrical nodes of the charge and discharge capacitanceCOne is kept under different data rate with the voltage difference of common-mode voltage VCM
It causes, that is, meets following relationship:
Wherein, UI is 1bit data time length, I0For charging and discharging currents, C0For the capacitor of charge and discharge capacitance, const is constant.
2. the serial pwm signal decoding circuit according to claim 1 based on capacitor charge and discharge structure, which is characterized in that
The sequential logic generation circuit, comprising:
Input port PWM_P, PWM_N low-voltage differential pwm signal for receiving input；
At least two groups Sequential logic output port connects with the input port of at least two capacitor charge and discharges decoder module respectively
It connects, wherein
The output signal of first group of Sequential logic output port is SWP1, SWN1, SWR1 and SA1, is respectively used to the first electricity of control
Hold charge switch SWP, discharge switch SWN, reset switch SWR and the port SA of charge and discharge decoder module；
The output signal of second group of Sequential logic output port is SWP2, SWN2, SWR2 and SA2, is respectively used to the second electricity of control
Hold charge switch SWP, discharge switch SWN, reset switch SWR and the port SA of charge and discharge decoder module.
3. the serial pwm signal decoding circuit according to claim 2 based on capacitor charge and discharge structure, which is characterized in that
When pwm signal low level arrives, discharge switch SWN disconnects charge switch SWP closure simultaneously, the current source IchTo charge and discharge
Capacitor C0It charges；When pwm signal high level arrives, charge switch SWP disconnects discharge switch SWN closure simultaneously, described
Current source IdisTo charge and discharge capacitance C0It discharges.
4. the serial pwm signal decoding circuit according to claim 2 based on capacitor charge and discharge structure, which is characterized in that
The current source IchWith current source IdisIt is programmable current source, programmable current source IchWith programmable current source Idis's
Electric current changes according to pwm signal data transfer rate and is changed, and data transfer rate more high current is bigger；Otherwise it is smaller.
5. the serial pwm signal decoding circuit according to claim 2 based on capacitor charge and discharge structure, which is characterized in that
The charge and discharge capacitance C0To may be programmed charge and discharge capacitance, charge and discharge capacitance C0Capacitance changes according to pwm signal data transfer rate and is become
Change, the bigger capacitance of data transfer rate is smaller；Otherwise it is bigger.
6. the serial pwm signal decoding circuit according to claim 2 based on capacitor charge and discharge structure, which is characterized in that
The serial pwm signal decoding circuit includes two capacitor charge and discharge decoder modules, which exists
It is worked alternatively under the control of sequential logic generation circuit, realizes the continuous decoding of serial pwm signal.
7. the serial pwm signal decoding circuit according to claim 6 based on capacitor charge and discharge structure, which is characterized in that
Described two capacitor charge and discharge decoder modules are respectively first capacitor charge and discharge decoder module and the second capacitor charge and discharge decoding mould
Block；Wherein,
First capacitor charge and discharge decoder module carries out charge and discharge in the odd number bit of serial pwm signal, completes data in even number bit
Deposit output and the reset of module；
Second capacitor charge and discharge decoder module carries out charge and discharge in the even number bit of serial pwm signal, completes data in odd number bit
Deposit output and the reset of module；Serial pwm signal is realized to which described two capacitor charge and discharge decoder modules work alternatively
Continuous decoding.
8. a kind of serial pwm signal decoding based on capacitor charge and discharge structure using as described in any one of claims 1 to 7
The method that circuit is decoded characterized by comprising
S1: before pwm signal arrival, by the charge and discharge capacitance C of a capacitor charge and discharge decoder module0Initial voltage value is reset to
Common-mode voltage VCM；
S2: when a bit pwm signal arrives, the charge and discharge capacitance C0The bit pwm signal is low, between high period respectively
Carry out charge and discharge, the charge and discharge capacitance C0The voltage of charge and discharge electrical nodes C when the bit pwm signal charge and discharge are completed is
VC；
S3: judge voltage VCWith common-mode voltage VCM voltage difference delta V polarity identification pwm signal to decode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710166006.XA CN106951385B (en) | 2017-03-20 | 2017-03-20 | Serial pwm signal decoding circuit and method based on capacitor charge and discharge structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710166006.XA CN106951385B (en) | 2017-03-20 | 2017-03-20 | Serial pwm signal decoding circuit and method based on capacitor charge and discharge structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106951385A CN106951385A (en) | 2017-07-14 |
| CN106951385B true CN106951385B (en) | 2019-09-24 |
Family
ID=59471931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710166006.XA Active CN106951385B (en) | 2017-03-20 | 2017-03-20 | Serial pwm signal decoding circuit and method based on capacitor charge and discharge structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106951385B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10958261B2 (en) | 2017-03-20 | 2021-03-23 | Institute of Microelectronics, Chinese Academy of Sciences | Serial PWM signal decoding circuit and method based on a capacitor charge-discharge structure and method thereof |
| US10904048B2 (en) | 2019-05-24 | 2021-01-26 | SanDiskTechnologies LLC | Pulse width modulated receiver systems and methods |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104283569A (en) * | 2013-07-04 | 2015-01-14 | 奇景光电股份有限公司 | Signal decoding circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE112011105674T5 (en) * | 2011-09-28 | 2014-07-17 | Intel Corp. | Data recovery at low power using overclocking |
| US8564365B2 (en) * | 2012-01-20 | 2013-10-22 | Qualcomm Incorporated | Wide input bit-rate, power efficient PWM decoder |
| US9425781B2 (en) * | 2013-03-29 | 2016-08-23 | Stmicroelectronics International N.V. | Syncless unit interval variation tolerant PWM receiver circuit, system and method |
-
2017
- 2017-03-20 CN CN201710166006.XA patent/CN106951385B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104283569A (en) * | 2013-07-04 | 2015-01-14 | 奇景光电股份有限公司 | Signal decoding circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106951385A (en) | 2017-07-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9998300B2 (en) | N-phase phase and polarity encoded serial interface | |
| CN107679000A (en) | The circuit and method that a kind of receiving end signal dutycycle adaptively adjusts | |
| CN106951385B (en) | Serial pwm signal decoding circuit and method based on capacitor charge and discharge structure | |
| CN103118251A (en) | Multi-level data transmission method and system | |
| CN101617494A (en) | Three phase and polarity encoded serial interface | |
| CN104639477A (en) | Backchannel communications for initialization of high-speed networks | |
| CN104252841A (en) | LED (Light Emitting Diode) display control method and card and LED display screen system | |
| CN108631151A (en) | Laser drive circuit | |
| CN103141066A (en) | Transmission circuit, reception circuit, transmission method, reception method, communication system and communication method therefor | |
| CN103559867A (en) | Grid drive circuit and array substrate and display panel thereof | |
| US20160301519A1 (en) | Clock and data recovery for pulse based multi-wire link | |
| CN101303683A (en) | Control interface and protocol | |
| WO2022262129A1 (en) | Led control system | |
| CN108959155A (en) | Address expansioning circuit and I2C communication interface chip | |
| CN101667851A (en) | Information processing apparatus and signal determining method | |
| CN104464676B (en) | Clock generation circuit of liquid crystal display device and operation method thereof | |
| CN105591645B (en) | A kind of multistage serial-parallel conversion circuit | |
| WO2018170681A1 (en) | Serial pwm signal decoding circuit and method based on capacitance charge-discharge structure | |
| CN87100875A (en) | Method and device with the proportional frequency of converting electrical signal | |
| CN209001927U (en) | Pulse signal transmission circuit and refresh pulse signal circuit | |
| CN110266303A (en) | Refresh circuit, method, chip and data transmission system | |
| CN106026982B (en) | A kind of monostable flipflop | |
| CN109104170B (en) | A kind of adaptive broadband digital clock interpolation device unit | |
| CN108988845A (en) | Nonpolarity RS485 realizes the circuit of polarity upset | |
| CN208673327U (en) | Address expansioning circuit and I2C communication interface chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201225 Address after: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee after: AoXin integrated circuit technology (Guangdong) Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220429 Address after: 510000 room 710, Jianshe building, No. 348, Kaifa Avenue, Huangpu District, Guangzhou, Guangdong Patentee after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. Address before: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee before: AoXin integrated circuit technology (Guangdong) Co.,Ltd. |
|
| TR01 | Transfer of patent right |