CN106950873A - Method of work of the nonvolatile memory in brake control unit - Google Patents
Method of work of the nonvolatile memory in brake control unit Download PDFInfo
- Publication number
- CN106950873A CN106950873A CN201710087303.5A CN201710087303A CN106950873A CN 106950873 A CN106950873 A CN 106950873A CN 201710087303 A CN201710087303 A CN 201710087303A CN 106950873 A CN106950873 A CN 106950873A
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- CN
- China
- Prior art keywords
- data
- scene
- nonvolatile memory
- signal
- logic compiler
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Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/21—Pc I-O input output
- G05B2219/21113—Bus interface has multiplexer, control register, data shift register
Abstract
The present invention relates to method of work of the nonvolatile memory in brake control unit, it will be added in conventional brake supervisory circuit, its specific works step is as follows：Step one, data are loaded；Loading signal acquisition circuit by the outside loading signal for applying ground connection be converted into it is live can logic compiler gate circuit can cross the signal of collection, and can logic compiler gate circuit to scene by hard-wire transfer；Step 2, data are uploaded；Loading signal acquisition circuit by it is outside apply hanging up-delivering signal be converted into scene can logic compiler gate circuit can cross the signal of collection by hard-wire transfer to scene can logic compiler gate circuit, scene can logic compiler gate circuit receive high level signal upload command be transferred to by digital signal processor by data/address bus.The present invention can realize that the upload of data in nonvolatile memory and scene are loaded.
Description
Technical field
The present invention relates to a kind of airplane brake system, specifically a kind of nonvolatile memory is in airplane brake system
Application technology.
Background technology
With the progress of Military Aviation Industry, the instrument and equipment on aircraft is to many electric-type, all electric development, brake system
The testbility demand of system requires more and more higher with Man machine interaction, therefore proposes to brake system higher requirement.It will
Ask the airplane brake system can be to each accessory electronic resume of Electric-machinery Management System reporting system, and scene can change resume.For
The uniformity that above-mentioned requirements ensure systems soft ware again is met, the present invention stores each annex using a kind of nonvolatile memory
Electronic record data, by scene can logic compiler gate circuit realize nonvolatile memory data upload with loading control
System, and by data by data bus transmission to digital signal processor, digital signal processor is according to biography after being changed
It is defeated by Electric-machinery Management System.
The content of the invention
Goal of the invention
To realize that the electronic record of brake system is reported and field modification, the present invention proposes a kind of nonvolatile memory
Application technology.
Technical scheme content
1st, method of work of the nonvolatile memory in brake control unit, will be added to conventional brake supervisory circuit
In, its specific works step is as follows：
Step one, data are loaded；The outside loading signal for applying ground connection is converted into scene by loading signal acquisition circuit can
Logic compiler gate circuit can cross the signal of collection, and by hard-wire transfer to scene can logic compiler gate circuit, scene can be compiled
Logic gates receives and loading command is transferred at digital signal processor, data signal by data/address bus after the signal
Reason device will receive RS422 communication datas can logic compiler gate circuit to scene by data bus transmission；Scene can compile and patrol
Collect gate circuit and Loading Control is carried out to nonvolatile memory again, it is effective to make chip selection signal, receives nonvolatile memory
Busy signal, when the not busy time control write signal of nonvolatile memory loads data into nonvolatile memory；
Step 2, data are uploaded；The hanging up-delivering signal of outside application is converted into scene by loading signal acquisition circuit can
Logic compiler gate circuit can cross the signal of collection by hard-wire transfer to scene can logic compiler gate circuit, scene can logic compiler
Gate circuit receives high level signal and upload command is transferred into digital signal processor by data/address bus；Digital Signal Processing
Device receives data upload command can logic compiler gate circuit to scene by data bus transmission；Scene can logic compiler door electricity
Road carries out upload control to nonvolatile memory again, and it is effective to make chip selection signal, makes read signal effectively, reads non-volatile deposit
Reservoir interior data, and mapped to by address date digital signal processor is transferred on data/address bus.
If data are 8 in the nonvolatile memory described in step 2, and the number that digital signal processor need to be spread out of
According to for 16, digital signal processor then needs the data that will be obtained from nonvolatile memory to merge, i.e. odd address
Data constitute 8, data composition ground on most-significant byte, even address line on line；The data combined are uploaded by 1553B communications again real
The application in brake system of existing nonvolatile memory.
The advantage of invention
Based on scene can logic compiler gate circuit+nonvolatile memory+Design of Digital Signal Processor, be it is a kind of it is non-easily
Application process of the property the lost memory in brake system, the upload and scene that can realize data in nonvolatile memory adds
Carry.
Brief description of the drawings
Fig. 1 is principle of the invention figure.
Embodiment
Effect to illustrate the invention, is verified by taking certain airplane brake system as an example, and electronic record data are passed through
1553B communications are uploaded to host computer, to prove application feasibility of the nonvolatile memory in brake system.
Referring to Fig. 1, the present embodiment is to be used for certain type machine brake system, and its detailed process is：
The nonvolatile memory chip that this example is used is STK14C88, scene can logic compiler gate circuit chip be
JQV1000, digital signal processor uses 2812
Step one, data are loaded
1. the outside loading signal for applying ground connection is converted into scene by loading signal acquisition circuit can logic compiler gate circuit
Can cross the signal of collection, and by hard-wire transfer to scene can logic compiler gate circuit, scene can logic compiler gate circuit receive
Loading command is transferred to by digital signal processor by data/address bus after to the signal.
2. digital signal processor will receive RS422 communication datas can logic compiler to scene by data bus transmission
Gate circuit；Scene can logic compiler gate circuit again to nonvolatile memory carry out Loading Control, it is effective to make chip selection signal, is connect
The busy signal of nonvolatile memory is received, when the not busy time control write signal of nonvolatile memory is to nonvolatile memory
Middle loading data.
Step 2, data are uploaded
1. the hanging up-delivering signal of outside application is converted into scene by loading signal acquisition circuit can logic compiler gate circuit
Can cross the signal of collection by hard-wire transfer to scene can logic compiler gate circuit, scene can logic compiler gate circuit receive height
Upload command is transferred to digital signal processor by level signal by data/address bus.
2. digital signal processor receives data upload command can logic compiler door to scene by data bus transmission
Circuit；Scene can logic compiler gate circuit again to nonvolatile memory carry out upload control, it is effective to make chip selection signal, makes reading
Signal effectively, reading non-volatile storage internal data, and mapped to by address date numeral is transferred on data/address bus
Signal processor.
Step 3, digital signal processor data conversion
Because 1553B communication datas are 16, and data are 8 in nonvolatile memory, and digital signal processor is needed
The data obtained from nonvolatile memory are merged, i.e., data are constituted on most-significant byte, even address line on the line of odd address
8, data composition ground.Again by the data combined by 1553B communicate upload realize nonvolatile memory in brake system
In application.
Claims (2)
1. method of work of the nonvolatile memory in brake control unit, it is characterised in that will be added to conventional brake
In supervisory circuit, its specific works step is as follows：
Step one, data are loaded；The outside loading signal for applying ground connection is converted into scene by loading signal acquisition circuit to be compiled
Logic gates can cross the signal of collection, and by hard-wire transfer to scene can logic compiler gate circuit, scene can logic compiler
Gate circuit receives and loading command is transferred into digital signal processor, digital signal processor by data/address bus after the signal
RS422 communication datas will be received can logic compiler gate circuit to scene by data bus transmission；Scene can logic compiler door
Circuit carries out Loading Control to nonvolatile memory again, and it is effective to make chip selection signal, receives the busy of nonvolatile memory
Signal, when the not busy time control write signal of nonvolatile memory loads data into nonvolatile memory；
Step 2, data are uploaded；The hanging up-delivering signal of outside application is converted into scene by loading signal acquisition circuit to be compiled
Logic gates can cross the signal of collection by hard-wire transfer to scene can logic compiler gate circuit, scene can logic compiler door electricity
Road receives high level signal and upload command is transferred into digital signal processor by data/address bus；Digital signal processor connects
Receiving data upload command can logic compiler gate circuit to scene by data bus transmission；Scene can logic compiler gate circuit again
Upload control is carried out to nonvolatile memory, it is effective to make chip selection signal, make read signal effectively, reading non-volatile storage
Internal data, and mapped to by address date digital signal processor is transferred on data/address bus.
2. method of work as claimed in claim 1, it is characterised in that if number in nonvolatile memory described in step 2
According to for 8, and the data that digital signal processor need to be spread out of are 16, and digital signal processor then needs to deposit from non-volatile
The data obtained on reservoir are merged, i.e., data constitute 8, data composition ground on most-significant byte, even address line on the line of odd address；Again
The data combined are communicated by 1553B and upload the application in brake system for realizing nonvolatile memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710087303.5A CN106950873A (en) | 2017-02-17 | 2017-02-17 | Method of work of the nonvolatile memory in brake control unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710087303.5A CN106950873A (en) | 2017-02-17 | 2017-02-17 | Method of work of the nonvolatile memory in brake control unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106950873A true CN106950873A (en) | 2017-07-14 |
Family
ID=59467106
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710087303.5A Pending CN106950873A (en) | 2017-02-17 | 2017-02-17 | Method of work of the nonvolatile memory in brake control unit |
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| Country | Link |
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| CN (1) | CN106950873A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101996265A (en) * | 2009-08-25 | 2011-03-30 | 安凯(广州)微电子技术有限公司 | Verification system and method for memory controller |
| CN102508467A (en) * | 2011-10-18 | 2012-06-20 | 中国西电电气股份有限公司 | Online monitoring system of switch equipment based on DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) |
| CN103092119A (en) * | 2013-01-15 | 2013-05-08 | 北京工业大学 | Bus state monitoring system and method based on field programmable gate array (FPGA) |
| CN103198042A (en) * | 2013-04-22 | 2013-07-10 | 哈尔滨工业大学 | PCI (programmable communications interface) aviation serial bus board and dynamic data loading processing method |
| CN106094659A (en) * | 2016-08-19 | 2016-11-09 | 北京航天长征飞行器研究所 | A kind of there is two-stage freestanding environment power identification function draw control device |
-
2017
- 2017-02-17 CN CN201710087303.5A patent/CN106950873A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101996265A (en) * | 2009-08-25 | 2011-03-30 | 安凯(广州)微电子技术有限公司 | Verification system and method for memory controller |
| CN102508467A (en) * | 2011-10-18 | 2012-06-20 | 中国西电电气股份有限公司 | Online monitoring system of switch equipment based on DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) |
| CN103092119A (en) * | 2013-01-15 | 2013-05-08 | 北京工业大学 | Bus state monitoring system and method based on field programmable gate array (FPGA) |
| CN103198042A (en) * | 2013-04-22 | 2013-07-10 | 哈尔滨工业大学 | PCI (programmable communications interface) aviation serial bus board and dynamic data loading processing method |
| CN106094659A (en) * | 2016-08-19 | 2016-11-09 | 北京航天长征飞行器研究所 | A kind of there is two-stage freestanding environment power identification function draw control device |
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| SE01 | Entry into force of request for substantive examination | ||
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| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170714 |