CN106941104A - A kind of charge trap-type nonvolatile storage preparation method of the high pressure resistant transistor of combination - Google Patents
A kind of charge trap-type nonvolatile storage preparation method of the high pressure resistant transistor of combination Download PDFInfo
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Abstract
A kind of charge trap-type nonvolatile storage preparation method of the high pressure resistant transistor of combination, including：In the active area of silicon-based substrate and shallow channel isolation area deposition ONO layer；The deposit polycrystalline silicon layer on ONO layer；The first insulating barrier of at least silicon nitride containing layer is deposited on the polysilicon layer；Control gate is formed by etching, and removes the polysilicon of memory block and external zones；In the noncontrolled area of memory block and external zones formation insulation film；The deposit polycrystalline silicon on insulation film；The second insulating barrier for including silicon nitride layer is deposited in polysilicon surface；The insulating barrier of dry etching second and polysilicon layer are to form external zones grid and memory block side wall type grid；External zones ion implanting is carried out through the second insulating barrier；The silicon nitride layer of the silicon nitride layer of synchronous the first insulating barrier for removing control gate top and the second insulating barrier of external zones top portions of gates.Compatibility of the invention is good, both ensure that the high breakdown voltage of peripheral circuit requirement, will not produce damage, and the effectively area of reduction memory cell to memory block again.
Description
Technical field
The present invention relates to the charge trap-type of technical field of manufacturing semiconductors, more particularly to a kind of high pressure resistant transistor of combination
Nonvolatile storage preparation method.
Background technology
With the development of technology, flush memory device is needed and advanced logical device is combined to reach more excellent performance, and
The programming of flush memory device and the erasable peripheral circuit offer high pressure for needing to be made up of logical device, this requires the tool of logical device
There is higher breakdown voltage.
Under normal circumstances, logic can be improved by increasing the energy of the shallow doped-drain of high pressure (HVLDD) ion implanting
The breakdown voltage of device, and higher ion implantation energy can bring the risk for punching grid, can now pass through increase again
The risk that the method reduction grid of gate height is punched.But, advanced logical device for reduction inter-level dielectric filling difficulty,
Consideration in terms of reduction parasitic capacitance and reduction power consumption would generally reduce gate height, at this moment just can be hard by depositing grid
The method of mask increases gate height.
Easily know ground, when removing the silicon nitride layer of hard mask version, memory block ONO (oxide-nitride-oxide)
The silicon nitride of layer needs also exist for protection, and this certainly will bring certain to non-volatile storage area with reference to the high pressure resistant device of advanced logic
Difficulty.
Therefore the problem of exist for prior art, this case designer is by the experience of the industry for many years is engaged in, actively research
Improvement, then there is a kind of charge trap-type nonvolatile storage preparation method of the high pressure resistant transistor of combination of the invention.
The content of the invention
The present invention be directed in the prior art, when removing the silicon nitride layer of hard mask version, memory block ONO (silica-nitrogen
SiClx-silica) layer silicon nitride need also exist for protection, this certainly will to non-volatile storage area combine the high pressure resistant device of advanced logic
Bring the charge trap-type nonvolatile storage making that the defects such as certain difficulty provide a kind of high pressure resistant transistor of combination
Method.
To realize the purpose of the present invention, a kind of charge trap-type of the high pressure resistant transistor of combination of present invention offer is non-volatile to be deposited
Reservoir preparation method, the charge trap-type nonvolatile storage preparation method of the high pressure resistant transistor of combination, including：
Perform step S1：ONO (oxygen is deposited in the active area (AA) of silicon-based substrate and the surface of shallow channel isolation area (STI)
SiClx-silicon-nitride and silicon oxide) layer；
Perform step S2：The first polysilicon layer is deposited in the side different from silicon-based substrate of the ONO layer；
Perform step S3：At least contain the first hard mask version in the side deposition different from ONO layer of first polysilicon layer
First insulating barrier of silicon nitride layer；
Perform step S4：Control gate is formed by etching, and removes the first polysilicon of memory block and external zones；
Perform step S5：In the noncontrolled area of memory block and external zones formation insulation film；
Perform step S6：The second polycrystalline for forming selection grid and external zones grid is deposited on the insulation film
Silicon；
Perform step S7：The second insulating barrier for including the second hard mask version silicon nitride layer is deposited in the second polysilicon surface；
Perform step S8：The insulating barrier of dry etching second and the second polysilicon layer are to form external zones grid and memory block side
Wall type grid；
Perform step S9：Shallow doped source drain electrode (LDD) ion implanting of external zones high pressure is carried out through the second insulating barrier；
Perform step S10：The first hard mask version silicon nitride layer of synchronous the first insulating barrier for removing control gate top and outside
Enclose the second hard mask version silicon nitride layer of the second insulating barrier of area's top portions of gates.
Alternatively, the first hard mask version silicon nitride layer of first insulating barrier at the control gate top and external zones grid top
The second hard mask version silicon nitride series of strata of second insulating barrier in portion are removed by wet etching.
Alternatively, in first insulating barrier, the thickness of the first hard mask version silicon nitride layer is maximum.
Alternatively, in second insulating barrier, the thickness of the second hard mask version silicon nitride layer is maximum.
Alternatively, the thickness of second insulating barrier is at least 800 angstroms.
Alternatively, the thickness of second insulating barrier is more than the height of external zones grid.
Alternatively, first insulating barrier and second insulating barrier using depositing respectively, while the technology mode removed.
Alternatively, the technology mode that the side wall type grid of memory block and external zones grid are formed using etching simultaneously.
Alternatively, the first hard mask version silicon nitride layer of first insulating barrier at the control gate top and external zones grid top
Side wall type grid of the removal of the second hard mask version silicon nitride layer of second insulating barrier in portion in the control gate side removes it
It is preceding to complete.
Alternatively, after the side wall type grid of the control gate side is removed, relative opposite side side wall type grid is
The selection grid of memory block.
In summary, the present invention increases control gate height by the method for control gate hard mask version and then forms side wall type and selects
Grid are selected, external zones gate height is increased by the method for peripheral circuit region grid hard mask version and then reaches reduction grid by ion
Inject the risk punched, and then improve peripheral logic device electric breakdown strength, and the hard mask version of external zones can be mixed high pressure is shallow
Miscellaneous drain electrode injection back side wall grid is entirely removed before removing, and the presence because of side wall type grid is so as to ensure hard mask version
Damage will not be caused during removal to the silicon nitride layer of memory block ONO (oxide-nitride-oxide) layer, can be preferably compatible
Advanced high pressure logical device and charge trap-type non-volatile memory device, both ensure that the higher breakdown potential of peripheral circuit requirement
Pressure, will not produce any damage, and effectively reduce the area of memory cell to memory block again.
Brief description of the drawings
Fig. 1~Figure 19 show the charge trap-type nonvolatile storage preparation method that the present invention combines high pressure resistant transistor
Flow chart.
Embodiment
To describe technology contents, construction feature, institute's reached purpose and effect of the invention in detail, below in conjunction with reality
Apply example and coordinate accompanying drawing to be described in detail.
With the development of technology, flush memory device is needed and advanced logical device is combined to reach more excellent performance, and
The programming of flush memory device and the erasable peripheral circuit offer high pressure for needing to be made up of logical device, this requires the tool of logical device
There is higher breakdown voltage.
Under normal circumstances, logic can be improved by increasing the energy of the shallow doped-drain of high pressure (HVLDD) ion implanting
The breakdown voltage of device, and higher ion implantation energy can bring the risk for punching grid, can now pass through increase again
The risk that the method reduction grid of gate height is punched.But, advanced logical device for reduction inter-level dielectric filling difficulty,
Consideration in terms of reduction parasitic capacitance and reduction power consumption would generally reduce gate height, at this moment just can be hard by depositing grid
The method of mask increases gate height.
Easily know ground, when removing the silicon nitride layer of hard mask version, memory block ONO (oxide-nitride-oxide)
The silicon nitride of layer needs also exist for protection, and this certainly will bring certain to non-volatile storage area with reference to the high pressure resistant device of advanced logic
Difficulty.
In order to overcome drawbacks described above, the present invention provides a kind of charge trap-type non-volatile memory of the high pressure resistant transistor of combination
The preparation method of device, the preparation method of the charge trap-type nonvolatile storage of the high pressure resistant transistor of combination, including：
Perform step S1：ONO (oxygen is deposited in the active area (AA) of silicon-based substrate and the surface of shallow channel isolation area (STI)
SiClx-silicon-nitride and silicon oxide) layer；
Perform step S2：The first polysilicon layer is deposited in the side different from silicon-based substrate of the ONO layer；
Perform step S3：At least contain the first hard mask version in the side deposition different from ONO layer of first polysilicon layer
First insulating barrier of silicon nitride layer；
Perform step S4：Control gate is formed by etching, and removes the first polysilicon of memory block and external zones；
Perform step S5：In the noncontrolled area of memory block and external zones formation insulation film；
Perform step S6：The second polycrystalline for forming selection grid and external zones grid is deposited on the insulation film
Silicon；
Perform step S7：The second insulating barrier for including the second hard mask version silicon nitride layer is deposited in the second polysilicon surface；
Perform step S8：The insulating barrier of dry etching second and the second polysilicon layer are to form external zones grid and memory block side
Wall type grid；
Perform step S9：Shallow doped source drain electrode (LDD) ion implanting of external zones high pressure is carried out through the second insulating barrier；
Perform step S10：The first hard mask version silicon nitride layer of synchronous the first insulating barrier for removing control gate top and outside
Enclose the second hard mask version silicon nitride layer of the second insulating barrier of area's top portions of gates.
Without limitation, the first hard mask version silicon nitride layer and external zones grid of first insulating barrier at the control gate top
The second hard mask version silicon nitride series of strata of second insulating barrier at pole top are removed by wet etching.In first insulating barrier
In, the thickness of the first hard mask version silicon nitride layer is maximum.In second insulating barrier, the second hard mask version nitridation
The thickness of silicon layer is maximum.More specifically, the thickness of second insulating barrier is at least 800 angstroms.The thickness of second insulating barrier
More than the height of external zones grid.
First insulating barrier and second insulating barrier using depositing respectively, while the technology mode removed.Memory block
Side wall type grid and external zones grid using simultaneously etch formed technology mode.First insulating barrier at the control gate top
The first hard mask version silicon nitride layer and second hard mask version silicon nitride layer of the second insulating barrier of external zones top portions of gates go
Except the completion before the removal of the side wall type grid of the control gate side.Further, the side wall type grid of the control gate side
After pole is removed, relative opposite side side wall type grid is the selection grid of memory block.
In order to more intuitively disclose the technical scheme of the present invention, the beneficial effect of the present invention is highlighted, in conjunction with specific implementation
Explained exemplified by mode.
Fig. 1~Figure 19 is referred to, the charge trap-type that Fig. 1~Figure 19 show the high pressure resistant transistor of present invention combination is non-easily
Lose the flow chart of memory preparation method.The charge trap-type nonvolatile storage making side of the high pressure resistant transistor of combination
Method, including：
Perform step S1：By deep trap inject silicon-based substrate 100 on carry out successively prerinse, ONO layer 101 deposit,
It is first polysilicon 102a depositions, the first hard mask version silicon oxide layer 103a depositions, polysilicon ion injection, prerinse, first hard
Mask plate silicon nitride layer 104a is deposited.
Wherein, the ONO layer 101 further comprises in being stacked in the silicon-based substrate 100, successively from bottom to top
The first silicon oxide layer 101a, silicon nitride layer 101b, the second silicon oxide layer 101c.The active area of the silicon-based substrate 100 enters one
Step is divided into memory block 100a, peripheral low-voltage device area 100b, periphery high voltage device regions 101c, and positioned at memory block 100a and institute
State the frontier district 100d between peripheral components area.
Meanwhile, for the ease of the brief description of the present invention, the peripheral low-voltage device area 100b, peripheral high voltage device regions
Frontier district 100d between 101c, memory block 100a and the peripheral components area, three regions are relative to the memory block 100a
Referred to as external zones.
Perform step S2：First photoresist 105a coating developments, are only covered at the 100a of memory block for forming control gate
Top area；
Perform step S3：Memory block 100a the first polysilicon 102a forms memory block 100a control after dry etching
Grid 106 processed, the first polysilicon 102a of peripheral circuit region is etched removals simultaneously, and etches and terminate at the of the ONO layer 101
Silicon dioxide layer 101c, and layer 107 is reoxidized in the side wall formation of control gate 106 by oxidation technology.It is apparent that active area
Because the stop by silicon nitride layer can effectively prevent from being oxidized.
Perform step S4：Oxide isotropic etching terminates at the silicon nitride layer 101b of ONO layer 101.
Perform step S5：Second photoresist 105b coating developments, the peripheral low-voltage device of the second photoresist 105b coverings
Area 100b, periphery high voltage device regions 100c and frontier district 100d, and carry out ion implanting.
It is apparent that being covered in the peripheral low-voltage device area 100b, periphery high voltage device regions 100c and frontier district 100d
The first hard mask version silicon oxide layer 103a and the version nitridation of the first hard mask at the second photoresist 105b and the top of the control gate 106
Silicon 104a can effectively stop the ion implanting, so that effective ion injection zone is only limitted to the non-control of the memory block 100a
Gate region processed.
It is used as those skilled in the art, it is readily appreciated that ground, the ion implanting is to form selection gate groove, by described in
Ion implantation technology is placed in influence of the fuel factor to ion implanting that can be reduced when herein produced by ONO layer 101 grows.However,
The processing step of the ion implanting can carry out order change on demand, be not limited to this, be not construed as to the technology of the present invention side
The limitation of case.
Perform step S6：Remove after the second photoresist 105b, remove active area ONO layer respectively by wet etching
101 silicon nitride layer 101b and the first silicon oxide layer 101a.
Perform step S7：After prerinse, the first thick grating oxide layer 108a depositions are carried out；
Perform step S8：Peripheral low-voltage device area 100b is exposed in 3rd photoresist 105c coating developments, passes through wet etching
Remove peripheral low-voltage device area 100b the first thick grating oxide layer 108a；
Perform step S9：Remove after the 3rd photoresist 105c, thin gate oxide deposition is carried out, finally in the peripheral low pressure
Device region 100b formation thin gate oxides 109, the second thick grating oxide layer 108b of peripheral high voltage device regions 100c formation, memory block
100a the second thick grating oxide layer 108b of non-controlling gate region formation.It is apparent that in the non-controlling grid region of the memory block 100a
Domain also can form thin gate oxide according to process requirements.
Perform step S10：Second polysilicon 102b deposit, the second polysilicon 102b simultaneously cover memory block 100a,
Peripheral low-voltage device area 100b, periphery high voltage device regions 100c and frontier district 100d, for forming memory block 100a selection
The grid of grid and external zones.
Perform step S11：4th photoresist 105d coating developments, covering P-type transistor region carries out N-type ion implanting
Annealing, to suppress poly-Si depletion effect, reduces gate oxide electrical thickness.It is apparent that in the art also can be according to technique
Need to choose whether to perform the step.
Perform step S12：The second hard mask version silicon oxide layer is successively sequentially depositing on the second polysilicon 102b
103b and the second hard mask version silicon nitride layer 104b, and carry out the 5th photoresist 105e coating developments, and the 5th photoresist
105e is covered in the top area for being used to form grid of external zones.
Perform step S13：Through the second hard mask version silicon oxide layer 103b and the second hard mask 104b pairs of silicon nitride layer of version
The second polysilicon 102b is performed etching, and in memory block 100a formation side wall types grid 110, in external zones formation grid
111。
Perform step S14：6th photoresist 105f coating developments, expose peripheral high voltage device regions 100c, enter horizontal high voltage shallow
Doped-drain (HVLDD) ion implanting.It is apparent that due to by second in the shallow doped-drain ion implantation process of the high pressure
Hard mask version silicon oxide layer 103b and the second hard mask version silicon nitride layer 104b protection, it is to avoid grid punches risk.
Perform step S15：The 6th photoresist 105f is removed, and silicon nitride wet etching is carried out, to remove control gate
The first hard mask version silicon nitride layer 104a at 106 tops and the second hard mask version silicon nitride layer at the top of external zones grid 111
The silicon nitride layer 101b of ONO layer 101 at 104b, and memory block 100a avoided under the protection of the side wall type grid 110 by
Damage.
Perform step S16：7th photoresist 105g coating developments, the 7th photoresist 105g borders are arranged on the control
The first hard mask version silicon oxide layer 103a of grid 106 processed top.
Perform step S17：Etching removes the polysilicon between control gate 106, the 7th photoresist 105g is then removed, with shape
Into the grid 111 of memory block 100a control gate 106, side wall type grid 110 and external zones.
Perform step S18：Deposited by grid curb wall, grid curb wall etching technics, formed grid curb wall 112.
Perform step S19：It is at the top of the side wall type grid 110, the top of control gate 106, external zones grid 111 and active
Area forms metal silicide 113.It is apparent that because the height of side wall type grid 110 is more than the height of control gate 106, then it is described
The grid curb wall 112 of side wall type grid 110 is effectively prevented positioned at the top of control gate 106 and the side wall type grid
The short circuit of metal silicide 113 at 110 tops.
As the embodiment of the present invention, without limitation, more than described first deposited in the silicon-based substrate 100
Crystal silicon 102a thickness is 1000~1500 angstroms, and the thickness of the hard mask version silicon oxide layer 103 is 100~200 angstroms, described hard
The thickness of mask silicon nitride layer 104 is 500~1000 angstroms.The thickness for reoxidizing layer 107 is 10~30nm.
In summary, the present invention increases control gate height by the method for control gate hard mask version and then forms side wall type and selects
Grid are selected, external zones gate height is increased by the method for peripheral circuit region grid hard mask version and then raising reduction grid quilt is reached
The risk that ion implanting is punched, and then peripheral logic device electric breakdown strength is improved, and the hard mask version of external zones can be in high pressure
Shallow doped-drain injection back side wall grid is entirely removed before removing, and the presence because of side wall type grid is so as to ensure to cover firmly
Masterplate will not cause damage to the silicon nitride layer of memory block ONO (oxide-nitride-oxide) layer when removing, can be preferably
Compatible advanced high pressure logical device and charge trap-type non-volatile memory device, both ensure that the higher of peripheral circuit requirement was hit
Voltage is worn, any damage will not be produced to memory block again, and effectively reduce the area of memory cell.
Those skilled in the art, can be to this hair it will be appreciated that without departing from the spirit or scope of the present invention
Bright carry out various modifications and variations.Thus, if any modification or modification fall into the protection of appended claims and equivalent
In the range of when, it is believed that the present invention cover these modification and modification.
Claims (10)
1. a kind of charge trap-type nonvolatile storage preparation method of the high pressure resistant transistor of combination, it is characterised in that the knot
The charge trap-type nonvolatile storage preparation method of high pressure resistant transistor is closed, including：
Perform step S1：Silicon-based substrate active area (AA) and shallow channel isolation area (STI) surface deposition ONO (silica-
Silicon-nitride and silicon oxide) layer；
Perform step S2：The first polysilicon layer is deposited in the side different from silicon-based substrate of the ONO layer；
Perform step S3：Nitrogenized at least version containing the first hard mask of the side deposition different from ONO layer of first polysilicon layer
First insulating barrier of silicon layer；
Perform step S4：Control gate is formed by etching, and removes the first polysilicon of memory block and external zones；
Perform step S5：In the noncontrolled area of memory block and external zones formation insulation film；
Perform step S6：The second polysilicon for forming selection grid and external zones grid is deposited on the insulation film；
Perform step S7：The second insulating barrier for including the second hard mask version silicon nitride layer is deposited in the second polysilicon surface；
Perform step S8：The insulating barrier of dry etching second and the second polysilicon layer are to form external zones grid and memory block side wall type
Grid；
Perform step S9：Shallow doped source drain electrode (LDD) ion implanting of external zones high pressure is carried out through the second insulating barrier；
Perform step S10：The the first hard mask version silicon nitride layer and external zones of synchronous the first insulating barrier for removing control gate top
The second hard mask version silicon nitride layer of second insulating barrier of top portions of gates.
2. the charge trap-type nonvolatile storage preparation method of high pressure resistant transistor, its feature are combined as claimed in claim 1
It is that the second of the first hard mask of first insulating barrier at control gate top version silicon nitride layer and external zones top portions of gates is exhausted
The second hard mask version silicon nitride series of strata of edge layer are removed by wet etching.
3. the charge trap-type nonvolatile storage preparation method of high pressure resistant transistor, its feature are combined as claimed in claim 1
It is that in first insulating barrier, the thickness of the first hard mask version silicon nitride layer is maximum.
4. the charge trap-type nonvolatile storage preparation method of high pressure resistant transistor, its feature are combined as claimed in claim 1
It is that in second insulating barrier, the thickness of the second hard mask version silicon nitride layer is maximum.
5. the charge trap-type nonvolatile storage preparation method of high pressure resistant transistor, its feature are combined as claimed in claim 4
It is that the thickness of second insulating barrier is at least 800 angstroms.
6. the charge trap-type nonvolatile storage preparation method of high pressure resistant transistor, its feature are combined as claimed in claim 4
It is that the thickness of second insulating barrier is more than the height of external zones grid.
7. the charge trap-type nonvolatile storage preparation method of high pressure resistant transistor, its feature are combined as claimed in claim 1
It is that first insulating barrier and second insulating barrier using depositing respectively, while the technology mode removed.
8. the charge trap-type nonvolatile storage preparation method of high pressure resistant transistor, its feature are combined as claimed in claim 1
It is that the side wall type grid and external zones grid of memory block are using the technology mode for etching formation simultaneously.
9. the charge trap-type nonvolatile storage preparation method of high pressure resistant transistor, its feature are combined as claimed in claim 1
It is that the second of the first hard mask of first insulating barrier at control gate top version silicon nitride layer and external zones top portions of gates is exhausted
The removal of the second hard mask version silicon nitride layer of edge layer is completed before the side wall type grid of the control gate side is removed.
10. the charge trap-type nonvolatile storage preparation method of high pressure resistant transistor, its feature are combined as claimed in claim 1
It is that after the side wall type grid of the control gate side is removed, relative opposite side side wall type grid is the choosing of memory block
Select grid.
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| US6274430B1 (en) * | 2000-07-07 | 2001-08-14 | United Microelectronics Corp. | Fabrication method for a high voltage electrical erasable programmable read only memory device |
| CN1855425A (en) * | 2005-04-26 | 2006-11-01 | 美格纳半导体有限会社 | Method for manufacturing a semiconductor device |
| KR20060124868A (en) * | 2005-05-26 | 2006-12-06 | 동부일렉트로닉스 주식회사 | Method for forming gate of flash memory device |
| CN101165903A (en) * | 2006-10-19 | 2008-04-23 | 三星电子株式会社 | Non-volatile memory devices including double diffused junction regions and methods of fabricating the same |
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2017
- 2017-04-24 CN CN201710272223.7A patent/CN106941104B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6274430B1 (en) * | 2000-07-07 | 2001-08-14 | United Microelectronics Corp. | Fabrication method for a high voltage electrical erasable programmable read only memory device |
| CN1855425A (en) * | 2005-04-26 | 2006-11-01 | 美格纳半导体有限会社 | Method for manufacturing a semiconductor device |
| KR20060124868A (en) * | 2005-05-26 | 2006-12-06 | 동부일렉트로닉스 주식회사 | Method for forming gate of flash memory device |
| CN101165903A (en) * | 2006-10-19 | 2008-04-23 | 三星电子株式会社 | Non-volatile memory devices including double diffused junction regions and methods of fabricating the same |
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