CN106935605A - Cmos image sensor and forming method thereof - Google Patents
Cmos image sensor and forming method thereof Download PDFInfo
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- CN106935605A CN106935605A CN201710142738.5A CN201710142738A CN106935605A CN 106935605 A CN106935605 A CN 106935605A CN 201710142738 A CN201710142738 A CN 201710142738A CN 106935605 A CN106935605 A CN 106935605A
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 94
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 238000005516 engineering process Methods 0.000 claims description 51
- 239000000463 material Substances 0.000 claims description 30
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 16
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 13
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 10
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Chemical compound O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 7
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 7
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 5
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 5
- 239000013078 crystal Substances 0.000 abstract description 6
- 230000001808 coupling effect Effects 0.000 abstract description 5
- 238000005240 physical vapour deposition Methods 0.000 description 60
- 238000005229 chemical vapour deposition Methods 0.000 description 37
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 23
- 229910052760 oxygen Inorganic materials 0.000 description 23
- 239000001301 oxygen Substances 0.000 description 23
- USPBSVTXIGCMKY-UHFFFAOYSA-N hafnium Chemical compound [Hf].[Hf] USPBSVTXIGCMKY-UHFFFAOYSA-N 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 230000008859 change Effects 0.000 description 14
- 229910052735 hafnium Inorganic materials 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 8
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- NMJKIRUDPFBRHW-UHFFFAOYSA-N titanium Chemical compound [Ti].[Ti] NMJKIRUDPFBRHW-UHFFFAOYSA-N 0.000 description 1
- -1 wherein Chemical compound 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
Abstract
The invention provides a kind of cmos image sensor and forming method thereof, wherein, first high-K dielectric layer includes multilayer the first high K dielectric sublayer, interface is discontinuous between adjacent two layers the first high K dielectric sublayer, thus, it is possible to improving coupling effect and suppressing crystal grain-growth, the free negative electrical charge in Semiconductor substrate is fixed between the first oxide layer and the first high-K dielectric layer interface well, the interface that free positive charge in Semiconductor substrate is fixed between Semiconductor substrate and the first oxide layer, so as to reduce leakage current well, further improve/avoid bright spot problem.
Description
Technical field
The present invention relates to imageing sensor manufacturing technology field, more particularly to a kind of cmos image sensor and its formation side
Method.
Background technology
Imageing sensor is the important component for constituting digital camera, is a kind of optical imagery to be converted into signal
Equipment, it is widely used in digital camera, mobile terminal, portable electron device and other electro-optical devices.Figure
As sensor can be divided into CCD (Charge Coupled Device, charge coupled cell) and CMOS (Complementary
Metal Semiconductor, CMOS complementary metal-oxide-semiconductor element) major class of imageing sensor two.
Because cmos image sensor is made using traditional cmos circuit technique, thus can by imageing sensor and
Peripheral circuit required for it is integrated, so that cmos image sensor has wider array of application prospect.
Bright spot (white pixel) is there is in cmos image sensor always, is mainly passed through in the prior art
K (high-k) dielectric layers high come attempt improve this problem.Specifically, cmos image sensor includes：Semiconductor substrate,
The oxide layer being formed in the Semiconductor substrate and the high-K dielectric layer being formed in the oxide layer.But, including K high Jie
Still there is a problem of than more serious bright spot in the cmos image sensor of matter layer.
The content of the invention
It is of the prior art to solve it is an object of the invention to provide a kind of cmos image sensor and forming method thereof
Still there is a problem of than more serious bright spot in cmos image sensor.
In order to solve the above technical problems, the present invention provides a kind of cmos image sensor, the cmos image sensor bag
Include：Semiconductor substrate, the first oxide layer being formed in the Semiconductor substrate and be formed in first oxide layer
One high-K dielectric layer, wherein, first high-K dielectric layer includes multilayer the first high K dielectric sublayer, the high K dielectric of adjacent two layers first
Interface is discontinuous between sublayer.
Optionally, in described cmos image sensor, every layer of component of the material of the first high K dielectric sublayer
Species is identical.
Optionally, in described cmos image sensor, every layer of component of the material of the first high K dielectric sublayer
Match identical or difference.
Optionally, in described cmos image sensor, every layer of surface of the first high K dielectric sublayer is by semiconductor work
Skill treatment.
Optionally, in described cmos image sensor, the cmos image sensor also includes being formed at described the
The second high-K dielectric layer in one high-K dielectric layer or between first high-K dielectric layer and first oxide layer, described second
The material of high-K dielectric layer is different from the material of first high-K dielectric layer.
Optionally, in described cmos image sensor, second high-K dielectric layer includes the high K dielectric of multilayer second
Sublayer, interface is discontinuous between adjacent two layers the second high K dielectric sublayer.
Optionally, in described cmos image sensor, first high-K dielectric layer and second high-K dielectric layer
Material include：Tantalum pentoxide, hafnium oxide, titanium oxide, Zirconium oxide or lanthanum-oxides.
Optionally, in described cmos image sensor, the cmos image sensor also includes being formed at described the
The second oxide layer in two high-K dielectric layers or first high-K dielectric layer.
The present invention also provides a kind of forming method of cmos image sensor, the forming method of the cmos image sensor
Including：
Semiconductor substrate is provided；
The first oxide layer is formed on the semiconductor substrate；
Multilayer the first high K dielectric sublayer is sequentially formed in first oxide layer, wherein, often form one layer of first K high
Surface while medium sublayer to the first high K dielectric sublayer carries out semiconductor technology treatment.
Optionally, in the forming method of described cmos image sensor, the semiconductor technology treatment includes：Annealing
Technique, oxidation technology or plasma-treating technology.
In cmos image sensor that the present invention is provided and forming method thereof, multilayer is included by the first high-K dielectric layer
First high K dielectric sublayer, interface is discontinuous between adjacent two layers the first high K dielectric sublayer, thus, it is possible to improve coupling effect and
Suppress crystal grain-growth, the free negative electrical charge in Semiconductor substrate is fixed on the first oxide layer and the first high-K dielectric layer well
Between interface, the interface that the free positive charge in Semiconductor substrate is fixed between Semiconductor substrate and the first oxide layer,
So as to reduce leakage current well, further improve/avoid bright spot problem.
Brief description of the drawings
Fig. 1 is the structural representation of the cmos image sensor of the embodiment of the present invention one；
Fig. 2 is the action principle figure of the cmos image sensor of the embodiment of the present invention one；
Fig. 3 is that the cmos image sensor of the embodiment of the present invention one compares with the effect of existing cmos image sensor
Figure；
Fig. 4 is the structural representation of the cmos image sensor of the embodiment of the present invention two；
Fig. 5 is the structural representation of the cmos image sensor of the embodiment of the present invention three；
Fig. 6 is the structural representation of the cmos image sensor of the embodiment of the present invention four.
Specific embodiment
Below in conjunction with the drawings and specific embodiments cmos image sensor proposed by the present invention and forming method thereof is made into
One step is described in detail.According to following explanation and claims, advantages and features of the invention will become apparent from.It should be noted that,
Accompanying drawing in the form of simplifying very much and uses non-accurately ratio, is only used to convenience, lucidly aids in illustrating the present invention
The purpose of embodiment.
【Embodiment one】
Fig. 1 is refer to, it is the structural representation of the cmos image sensor of the embodiment of the present invention one.As shown in figure 1,
In the embodiment of the present application, the cmos image sensor 1 includes：Semiconductor substrate 10, it is formed in the Semiconductor substrate 10
The first oxide layer 11 and the first high-K dielectric layer 12 for being formed in first oxide layer 11, wherein, first K high is situated between
Matter layer 12 includes multilayer the first high K dielectric sublayer, and interface is discontinuous between adjacent two layers the first high K dielectric sublayer.Here, described
First high-K dielectric layer 12 includes three layer of first high K dielectric sublayer, respectively the first high K dielectric sublayer 120, the first high K dielectric
The high K dielectric sublayer 122 of layer 121 and first.
Specifically, providing Semiconductor substrate 10 first.Preferably, the Semiconductor substrate 10 is silicon substrate.Further,
Photodiode (PD) and some control circuits etc. are formed with the Semiconductor substrate 10.
Then, the first oxide layer 11 is formed in the Semiconductor substrate 10, wherein, the material of first oxide layer 11
It can be silica.Specifically, first oxide layer 11 can be by chemical vapor deposition (CVD) or physical vapour deposition (PVD)
Etc. (PVD) semiconductor technology is formed.
Please continue to refer to Fig. 1, in the embodiment of the present application, then, the first K high is formed in first oxide layer 11 and is situated between
Proton sphere 120.Specifically, chemical vapor deposition (CVD) or K Jie high of physical vapour deposition (PVD) (PVD) formation first can be first passed through
Proton sphere, meanwhile, semiconductor technology treatment is carried out to the first high K dielectric sublayer.Wherein, the semiconductor technology treatment bag
Include：The techniques such as annealing process, oxidation technology or plasma-treating technology.The purpose is to change the first high K dielectric
The property on 120 surface of layer, so as to discontinuous with the interface of the first high K dielectric sublayer 121 being subsequently formed.It is therefore possible to use appointing
Anticipate a kind of semiconductor processes, if its enable to the surface of the first high K dielectric sublayer 120 property occur it is certain
Change.In the embodiment of the present application, the material of the first high K dielectric sublayer 120 is hafnium oxide, wherein, the hafnium
Hafnium is not construed as limiting with proportioning the present embodiment of oxygen in oxide.In the embodiment of the present application, the first high K dielectric sublayer 120
Thickness be 20 angstroms, in the other embodiment of the application, the thickness of the first high K dielectric sublayer 120 can it is thicker or
It is thinner, for example, the thickness of the first high K dielectric sublayer 120 can be 15 angstroms, 25 angstroms, 30 angstroms or 40 angstroms etc..
In the embodiment of the present application, then the first high K dielectric sublayer is formed in the first high K dielectric sublayer 120
121.Likewise, chemical vapor deposition (CVD) or physical vapour deposition (PVD) (PVD) the first high K dielectric sublayer of formation can be first passed through,
Meanwhile, semiconductor technology treatment is carried out to the first high K dielectric sublayer.Wherein, the semiconductor technology treatment includes：Annealing
The techniques such as technique, oxidation technology or plasma-treating technology.The purpose is to change the table of the first high K dielectric sublayer 121
The property in face, so as to discontinuous with the interface of the first high K dielectric sublayer 122 being subsequently formed.It is therefore possible to use any one is partly
Conductor handling process, as long as it enables to the property on the surface of the first high K dielectric sublayer 121 that certain change occurs i.e.
Can.In the embodiment of the present application, the material of the first high K dielectric sublayer 121 is hafnium oxide, wherein, the hafnium oxide
Middle hafnium is not construed as limiting with proportioning the present embodiment of oxygen.Further, in the first high K dielectric sublayer 121 hafnium and oxygen proportioning
Be able to can also be differed with identical with hafnium in the first high K dielectric sublayer 120 with the proportioning of oxygen.In the embodiment of the present application,
The thickness of the first high K dielectric sublayer 121 is 20 angstroms, in the other embodiment of the application, the first high K dielectric sublayer
121 thickness can be thicker or thinner, for example, the thickness of the first high K dielectric sublayer 121 can for 15 angstroms, 25 angstroms, 30
Angstrom or 40 angstroms etc..
Finally, the first high K dielectric sublayer 122 is formed in the first high K dielectric sublayer 121.In the embodiment of the present application
In, because the first high K dielectric sublayer 122 is last floor height K medium sublayers in first high-K dielectric layer 12, lead to
Cross after chemical vapor deposition (CVD) or physical vapour deposition (PVD) (PVD) form the first high K dielectric sublayer, both can be to described the
One high K dielectric sublayer carries out semiconductor technology treatment, it is also possible to the first high K dielectric sublayer is not carried out at semiconductor technology
Reason.In the embodiment of the present application, the material of the first high K dielectric sublayer 122 is hafnium oxide, wherein, the hafnium oxide
Middle hafnium is not construed as limiting with proportioning the present embodiment of oxygen.Further, in the first high K dielectric sublayer 122 hafnium and oxygen proportioning
With the proportioning of hafnium in the first high K dielectric sublayer 120 and the first high K dielectric sublayer 121 and oxygen can with it is identical can also
Differ.In the embodiment of the present application, the thickness of the first high K dielectric sublayer 122 is 20 angstroms, in other implementations of the application
In example, the thickness of the first high K dielectric sublayer 122 can be thicker or thinner, for example, the first high K dielectric sublayer 122
Thickness can be 15 angstroms, 25 angstroms, 30 angstroms or 40 angstroms etc..
As fully visible, in the embodiment of the present application, first high-K dielectric layer 12 includes three layer of first high K dielectric sublayer,
Respectively the first high K dielectric sublayer 120, the first high K dielectric sublayer 121 and the first high K dielectric sublayer 122, every layer of first K high are situated between
The thickness of proton sphere is 20 angstroms, and interface is discontinuous between adjacent two layers the first high K dielectric sublayer.
Then, Fig. 2 is refer to, it is the action principle figure of the cmos image sensor of the embodiment of the present invention one.Such as Fig. 2 institutes
Show, in the embodiment of the present application, because interface is discontinuous between adjacent two layers the first high K dielectric sublayer, thus, it is possible to improve coupling
Close effect and suppress crystal grain-growth, the free negative electrical charge in Semiconductor substrate 10 is fixed on the first oxide layer 11 and the well
Interface between one high-K dielectric layer 12 (herein namely the first high K dielectric sublayer 120), by Semiconductor substrate 10 it is free just
The interface that electric charge is fixed between the oxide layer 11 of Semiconductor substrate 10 and first, so as to reduce leakage current well, further changes
Be apt to/avoid bright spot problem.
Further, Fig. 3 is refer to, it is the cmos image sensor and existing cmos image of the embodiment of the present invention one
The effect of sensor compares figure.Wherein, curve a shows the bright spot situation of the cmos image sensor of the embodiment of the present application one,
In the cmos image sensor, including three layer of first high K dielectric sublayer, every layer of thickness of the first high K dielectric sublayer is 20 angstroms；
Curve b shows the bright spot situation of the cmos image sensor of prior art, in the cmos image sensor, including one (whole
Body) high-K dielectric layer, the thickness of the high-K dielectric layer is 60 angstroms, and as seen from Figure 3, the cmos image that the embodiment of the present application is provided is passed
Sensor can be apparent improvement bright spot problem.
【Embodiment two】
Fig. 4 is refer to, it is the structural representation of the cmos image sensor of the embodiment of the present invention two.As shown in figure 4,
In the embodiment of the present application, the cmos image sensor 2 includes：Semiconductor substrate 20, it is formed in the Semiconductor substrate 20
The first oxide layer 21, be formed in first oxide layer 21 the first high-K dielectric layer 22, be formed at the described first K high and be situated between
Matter layer 22 on the second high-K dielectric layer 23 and formed with second high-K dielectric layer 23 on the second oxide layer 24, wherein, institute
Stating the first high-K dielectric layer 22 includes multilayer the first high K dielectric sublayer, and interface does not connect between adjacent two layers the first high K dielectric sublayer
It is continuous.Here, first high-K dielectric layer 22 include two-layer the first high K dielectric sublayer, respectively the first high K dielectric sublayer 220 and
First high K dielectric sublayer 221.
Specifically, providing Semiconductor substrate 20 first.Preferably, the Semiconductor substrate 20 is silicon substrate.Further,
Photodiode (PD) and some control circuits etc. are formed with the Semiconductor substrate 20.
Then, the first oxide layer 21 is formed in the Semiconductor substrate 20, wherein, the material of first oxide layer 21
It can be silica.Specifically, first oxide layer 21 can be by chemical vapor deposition (CVD) or physical vapour deposition (PVD)
Etc. (PVD) semiconductor technology is formed.
Please continue to refer to Fig. 4, in the embodiment of the present application, then, the first K high is formed in first oxide layer 21 and is situated between
Proton sphere 220.Specifically, chemical vapor deposition (CVD) or K Jie high of physical vapour deposition (PVD) (PVD) formation first can be first passed through
Proton sphere, meanwhile, semiconductor technology treatment is carried out to the first high K dielectric sublayer.Wherein, the semiconductor technology treatment bag
Include：The techniques such as annealing process, oxidation technology or plasma-treating technology.The purpose is to change the first high K dielectric
The property on 220 surface of layer, so as to discontinuous with the interface of the first high K dielectric sublayer 221 being subsequently formed.It is therefore possible to use appointing
Anticipate a kind of semiconductor processes, if its enable to the surface of the first high K dielectric sublayer 220 property occur it is certain
Change.In the embodiment of the present application, the material of the first high K dielectric sublayer 220 is titanium oxide, wherein, the titanium
Titanium is not construed as limiting with proportioning the present embodiment of oxygen in oxide.The thickness of the first high K dielectric sublayer 220 can for 10 angstroms~
50 angstroms.
Then, the first high K dielectric sublayer 221 is formed in the first high K dielectric sublayer 220.In the embodiment of the present application
In, because the first high K dielectric sublayer 221 is last floor height K medium sublayers in first high-K dielectric layer 22, lead to
Cross after chemical vapor deposition (CVD) or physical vapour deposition (PVD) (PVD) form the first high K dielectric sublayer, both can be to described the
One high K dielectric sublayer carries out semiconductor technology treatment, it is also possible to the first high K dielectric sublayer is not carried out at semiconductor technology
Reason.In the embodiment of the present application, the material of the first high K dielectric sublayer 221 is titanium oxide, wherein, the titanium oxide
Middle titanium is not construed as limiting with proportioning the present embodiment of oxygen.Further, in the first high K dielectric sublayer 221 titanium and oxygen proportioning
Be able to can also be differed with identical with titanium in the first high K dielectric sublayer 220 with the proportioning of oxygen.In the embodiment of the present application,
The thickness of the first high K dielectric sublayer 221 can be 10 angstroms~50 angstroms.
In embodiment is applied for, then, the second high-K dielectric layer 23 is formed in the first high K dielectric sublayer 221.Its
In, second high-K dielectric layer 23 can be formed by chemical vapor deposition (CVD) or physical vapour deposition (PVD) (PVD), its material
Can be tantalum pentoxide, hafnium oxide, titanium oxide, Zirconium oxide or lanthanum-oxides etc., its thickness can be 10 angstroms~200
Angstrom.
Then, the second oxide layer 24 is formed in second high-K dielectric layer 23, the material of second oxide layer 24 can
Think silica.Specifically, second oxide layer 24 can be by chemical vapor deposition (CVD) or physical vapour deposition (PVD)
Etc. (PVD) semiconductor technology is formed.
In the embodiment of the present application, multilayer the first high K dielectric sublayer, adjacent two layers the are included by the first high-K dielectric layer
Interface is discontinuous between one high K dielectric sublayer, thus, it is possible to improving coupling effect and suppressing crystal grain-growth, well by semiconductor
The interface that free negative electrical charge in substrate is fixed between the first oxide layer and the first high-K dielectric layer, by Semiconductor substrate
The interface that free positive charge is fixed between Semiconductor substrate and the first oxide layer, so that leakage current is reduced well, further
Improve/avoid bright spot problem.
【Embodiment three】
Fig. 5 is refer to, it is the structural representation of the cmos image sensor of the embodiment of the present invention three.As shown in figure 5,
In the embodiment of the present application, the cmos image sensor 3 includes：Semiconductor substrate 30, it is formed in the Semiconductor substrate 30
The first oxide layer 31, be formed in first oxide layer 31 the first high-K dielectric layer 32, be formed at the described first K high and be situated between
The second oxide layer 34 in the second high-K dielectric layer 33 and formation and second high-K dielectric layer 33 on matter layer 32；Wherein, institute
Stating the first high-K dielectric layer 32 includes multilayer the first high K dielectric sublayer, and interface does not connect between adjacent two layers the first high K dielectric sublayer
It is continuous；Second high-K dielectric layer 33 includes multilayer the second high K dielectric sublayer, interface between adjacent two layers the second high K dielectric sublayer
Discontinuously.Here, first high-K dielectric layer 32 includes two-layer the first high K dielectric sublayer, respectively the first high K dielectric sublayer
320 and the first high K dielectric sublayer 321；Second high-K dielectric layer 33 includes two-layer the second high K dielectric sublayer, respectively second
The high K dielectric sublayer 331 of high K dielectric sublayer 330 and second.
Specifically, providing Semiconductor substrate 30 first.Preferably, the Semiconductor substrate 30 is silicon substrate.Further,
Photodiode (PD) and some control circuits etc. are formed with the Semiconductor substrate 30.
Then, the first oxide layer 31 is formed in the Semiconductor substrate 30, wherein, the material of first oxide layer 31
It can be silica.Specifically, first oxide layer 31 can be by chemical vapor deposition (CVD) or physical vapour deposition (PVD)
Etc. (PVD) semiconductor technology is formed.
Please continue to refer to Fig. 5, in the embodiment of the present application, then, the first K high is formed in first oxide layer 31 and is situated between
Proton sphere 320.Specifically, chemical vapor deposition (CVD) or K Jie high of physical vapour deposition (PVD) (PVD) formation first can be first passed through
Proton sphere, meanwhile, semiconductor technology treatment is carried out to the first high K dielectric sublayer.Wherein, the semiconductor technology treatment bag
Include：The techniques such as annealing process, oxidation technology or plasma-treating technology.The purpose is to change the first high K dielectric
The property on 320 surface of layer, so as to discontinuous with the interface of the first high K dielectric sublayer 321 being subsequently formed.It is therefore possible to use appointing
Anticipate a kind of semiconductor processes, if its enable to the surface of the first high K dielectric sublayer 320 property occur it is certain
Change.In the embodiment of the present application, the material of the first high K dielectric sublayer 320 is hafnium oxide, wherein, the hafnium
Hafnium is not construed as limiting with proportioning the present embodiment of oxygen in oxide.The thickness of the first high K dielectric sublayer 320 can for 10 angstroms~
50 angstroms.
Then, the first high K dielectric sublayer 321 is formed in the first high K dielectric sublayer 320.In the embodiment of the present application
In, because the first high K dielectric sublayer 321 is last floor height K medium sublayers in first high-K dielectric layer 32, lead to
Cross after chemical vapor deposition (CVD) or physical vapour deposition (PVD) (PVD) form the first high K dielectric sublayer, both can be to described the
One high K dielectric sublayer carries out semiconductor technology treatment, it is also possible to the first high K dielectric sublayer is not carried out at semiconductor technology
Reason.In the embodiment of the present application, the material of the first high K dielectric sublayer 321 is hafnium oxide, wherein, the hafnium oxide
Middle hafnium is not construed as limiting with proportioning the present embodiment of oxygen.Further, in the first high K dielectric sublayer 321 hafnium and oxygen proportioning
Be able to can also be differed with identical with hafnium in the first high K dielectric sublayer 320 with the proportioning of oxygen.In the embodiment of the present application,
The thickness of the first high K dielectric sublayer 321 can be 10 angstroms~50 angstroms.
In embodiment is applied for, then, the second high-K dielectric layer 33 is formed in the first high K dielectric sublayer 321.Tool
Body, form the second high K dielectric sublayer 330 in the first high K dielectric sublayer 321.Specifically, chemical gaseous phase can be first passed through
Deposition (CVD) or physical vapour deposition (PVD) (PVD) form the second high K dielectric sublayer, meanwhile, to the second high K dielectric sublayer
Carry out semiconductor technology treatment.Wherein, the semiconductor technology treatment includes：Annealing process, oxidation technology or plasma
The techniques such as handling process.Property the purpose is to change the surface of the second high K dielectric sublayer 330, so as to be subsequently formed
The interface of second high K dielectric sublayer 331 is discontinuous.It is therefore possible to use any one semiconductor processes, as long as it can make
There is certain change in the property for obtaining the surface of the second high K dielectric sublayer 330.In the embodiment of the present application, described
The material of two high K dielectric sublayers 330 is tantalum pentoxide, wherein, tantalum is not made with proportioning the present embodiment of oxygen in the tantalum pentoxide
Limit.The thickness of the second high K dielectric sublayer 330 can be 10 angstroms~50 angstroms.
Then, the second high K dielectric sublayer 331 is formed in the second high K dielectric sublayer 330.In the embodiment of the present application
In, because the second high K dielectric sublayer 331 is last floor height K medium sublayers in second high-K dielectric layer 33, lead to
Cross after chemical vapor deposition (CVD) or physical vapour deposition (PVD) (PVD) form the second high K dielectric sublayer, both can be to described the
Two high K dielectric sublayers carry out semiconductor technology treatment, it is also possible to the second high K dielectric sublayer is not carried out at semiconductor technology
Reason.In the embodiment of the present application, the material of the second high K dielectric sublayer 331 is tantalum pentoxide, wherein, the tantalum pentoxide
Middle tantalum is not construed as limiting with proportioning the present embodiment of oxygen.Further, in the second high K dielectric sublayer 331 hafnium and oxygen proportioning
Be able to can also be differed with identical with tantalum in the second high K dielectric sublayer 330 with the proportioning of oxygen.In the embodiment of the present application,
The thickness of the second high K dielectric sublayer 331 can be 10 angstroms~50 angstroms.
Then, (namely in described second high K dielectric sublayer 331) forms second in second high-K dielectric layer 33
Oxide layer 34, the material of second oxide layer 34 can be silica.Specifically, second oxide layer 34 can be by changing
The semiconductor technologies such as vapour deposition (CVD) or physical vapour deposition (PVD) (PVD) are learned to be formed.
In the embodiment of the present application, multilayer the first high K dielectric sublayer, adjacent two layers the are included by the first high-K dielectric layer
Interface is discontinuous between one high K dielectric sublayer；Second high-K dielectric layer includes multilayer the second high K dielectric sublayer, adjacent two layers second
Interface is discontinuous between high K dielectric sublayer, thus, it is possible to improving coupling effect and suppressing crystal grain-growth, well serves as a contrast semiconductor
The interface that free negative electrical charge in bottom is fixed between the first oxide layer and the first high-K dielectric layer, by the trip in Semiconductor substrate
From the interface that positive charge is fixed between Semiconductor substrate and the first oxide layer, so as to reduce leakage current well, further change
Be apt to/avoid bright spot problem.
【Example IV】
Fig. 6 is refer to, it is the structural representation of the cmos image sensor of the embodiment of the present invention four.As shown in fig. 6,
In the embodiment of the present application, the cmos image sensor 4 includes：Semiconductor substrate 40, it is formed in the Semiconductor substrate 40
The first oxide layer 41, be formed in first oxide layer 41 the second high-K dielectric layer 43, be formed at the described second K high and be situated between
The second oxide layer 44 in the first high-K dielectric layer 42 and formation and first high-K dielectric layer 42 on matter layer 43；Wherein, institute
Stating the first high-K dielectric layer 42 includes multilayer the first high K dielectric sublayer, and interface does not connect between adjacent two layers the first high K dielectric sublayer
It is continuous.Here, first high-K dielectric layer 42 include two-layer the first high K dielectric sublayer, respectively the first high K dielectric sublayer 420 and
First high K dielectric sublayer 421.
Specifically, providing Semiconductor substrate 40 first.Preferably, the Semiconductor substrate 40 is silicon substrate.Further,
Photodiode (PD) and some control circuits etc. are formed with the Semiconductor substrate 40.
Then, the first oxide layer 41 is formed in the Semiconductor substrate 40, wherein, the material of first oxide layer 41
It can be silica.Specifically, first oxide layer 41 can be by chemical vapor deposition (CVD) or physical vapour deposition (PVD)
Etc. (PVD) semiconductor technology is formed.
In the embodiment of the present application, then, the second high-K dielectric layer 43 is formed in first oxide layer 41.Wherein, institute
Stating the second high-K dielectric layer 43 can be formed by chemical vapor deposition (CVD) or physical vapour deposition (PVD) (PVD), and its material can be with
It is tantalum pentoxide, hafnium oxide, titanium oxide, Zirconium oxide or lanthanum-oxides etc., its thickness can be 10 angstroms~200 angstroms.
Please continue to refer to Fig. 6, in the embodiment of the present application, then, first is formed in second high-K dielectric layer 43 high
K medium sublayers 420.Specifically, the first K high of chemical vapor deposition (CVD) or physical vapour deposition (PVD) (PVD) formation can be first passed through
Medium sublayer, meanwhile, semiconductor technology treatment is carried out to the first high K dielectric sublayer.Wherein, the semiconductor technology treatment
Including：The techniques such as annealing process, oxidation technology or plasma-treating technology.The purpose is to change first high K dielectric
The property on the surface of sublayer 420, so as to discontinuous with the interface of the first high K dielectric sublayer 421 being subsequently formed.It is therefore possible to use
Any one semiconductor processes, as long as it enables to the property on the surface of the first high K dielectric sublayer 420 to occur necessarily
Change.In the embodiment of the present application, the material of the first high K dielectric sublayer 420 is hafnium oxide, wherein, it is described
Hafnium is not construed as limiting with proportioning the present embodiment of oxygen in hafnium oxide.The thickness of the first high K dielectric sublayer 420 can be 10 angstroms
~50 angstroms.
Then, the first high K dielectric sublayer 421 is formed in the first high K dielectric sublayer 420.In the embodiment of the present application
In, because the first high K dielectric sublayer 421 is last floor height K medium sublayers in first high-K dielectric layer 42, lead to
Cross after chemical vapor deposition (CVD) or physical vapour deposition (PVD) (PVD) form the first high K dielectric sublayer, both can be to described the
One high K dielectric sublayer carries out semiconductor technology treatment, it is also possible to the first high K dielectric sublayer is not carried out at semiconductor technology
Reason.In the embodiment of the present application, the material of the first high K dielectric sublayer 421 is hafnium oxide, wherein, the hafnium oxide
Middle hafnium is not construed as limiting with proportioning the present embodiment of oxygen.Further, in the first high K dielectric sublayer 421 hafnium and oxygen proportioning
Be able to can also be differed with identical with hafnium in the first high K dielectric sublayer 420 with the proportioning of oxygen.In the embodiment of the present application,
The thickness of the first high K dielectric sublayer 421 can be 10 angstroms~50 angstroms.In the other embodiment of the application, described first
High-K dielectric layer 42 (including the first high K dielectric sublayer 420 and first high K dielectric sublayer 421) can also be tantalum pentoxide, titanyl
Other high K dielectric materials such as compound, Zirconium oxide or lanthanum-oxides.
Then, (namely in described first high K dielectric sublayer 421) forms second in first high-K dielectric layer 42
Oxide layer 44, the material of second oxide layer 44 can be silica.Specifically, second oxide layer 44 can be by changing
The semiconductor technologies such as vapour deposition (CVD) or physical vapour deposition (PVD) (PVD) are learned to be formed.
In the embodiment of the present application, multilayer the first high K dielectric sublayer, adjacent two layers the are included by the first high-K dielectric layer
Interface is discontinuous between one high K dielectric sublayer, thus, it is possible to improving coupling effect and suppressing crystal grain-growth, well by semiconductor
The interface that free negative electrical charge in substrate is fixed between the first oxide layer and the first high-K dielectric layer, by Semiconductor substrate
The interface that free positive charge is fixed between Semiconductor substrate and the first oxide layer, so that leakage current is reduced well, further
Improve/avoid bright spot problem.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Scope.
Claims (10)
1. a kind of cmos image sensor, it is characterised in that the cmos image sensor includes：Semiconductor substrate, it is formed at
The first oxide layer in the Semiconductor substrate and the first high-K dielectric layer being formed in first oxide layer, wherein, it is described
First high-K dielectric layer includes multilayer the first high K dielectric sublayer, and interface is discontinuous between adjacent two layers the first high K dielectric sublayer.
2. cmos image sensor as claimed in claim 1, it is characterised in that every layer of material of the first high K dielectric sublayer
The species of component is identical.
3. cmos image sensor as claimed in claim 2, it is characterised in that every layer of material of the first high K dielectric sublayer
The proportioning of component is identical or difference.
4. the cmos image sensor as any one of claims 1 to 3, it is characterised in that every layer of the first high K dielectric
The surface of layer is processed by semiconductor technology.
5. cmos image sensor as claimed in claim 4, it is characterised in that the cmos image sensor also includes being formed
In the second high-K dielectric layer in first high-K dielectric layer or between first high-K dielectric layer and first oxide layer,
The material of second high-K dielectric layer is different from the material of first high-K dielectric layer.
6. cmos image sensor as claimed in claim 5, it is characterised in that second high-K dielectric layer includes multilayer the
Two high K dielectric sublayers, interface is discontinuous between adjacent two layers the second high K dielectric sublayer.
7. cmos image sensor as claimed in claim 5, it is characterised in that first high-K dielectric layer and described second
The material of high-K dielectric layer includes：Tantalum pentoxide, hafnium oxide, titanium oxide, Zirconium oxide or lanthanum-oxides.
8. such as claim cmos image sensor as claimed in claim 5, it is characterised in that the cmos image sensor
Also include the second oxide layer being formed in second high-K dielectric layer or first high-K dielectric layer.
9. a kind of forming method of cmos image sensor, it is characterised in that the forming method bag of the cmos image sensor
Include：
Semiconductor substrate is provided；
The first oxide layer is formed on the semiconductor substrate；
Multilayer the first high K dielectric sublayer is sequentially formed in first oxide layer, wherein, often form one layer of first high K dielectric
Surface while sublayer to the first high K dielectric sublayer carries out semiconductor technology treatment.
10. the forming method of cmos image sensor as claimed in claim 9, it is characterised in that at the semiconductor technology
Reason includes：Annealing process, oxidation technology or plasma-treating technology.
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| CN1734777A (en) * | 2004-08-10 | 2006-02-15 | 索尼株式会社 | Solid-state imaging device, method of producing the same, and camera |
| CN101409301A (en) * | 2007-10-11 | 2009-04-15 | 索尼株式会社 | Solid state imaging device, its manufacturing method, and imaging device |
| CN103378117A (en) * | 2012-04-25 | 2013-10-30 | 台湾积体电路制造股份有限公司 | Backside illuminated image sensor with negatively charged layer |
| CN104103654A (en) * | 2013-04-04 | 2014-10-15 | 全视科技有限公司 | Image sensor and imaging device |
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2017
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1734777A (en) * | 2004-08-10 | 2006-02-15 | 索尼株式会社 | Solid-state imaging device, method of producing the same, and camera |
| CN101409301A (en) * | 2007-10-11 | 2009-04-15 | 索尼株式会社 | Solid state imaging device, its manufacturing method, and imaging device |
| CN103378117A (en) * | 2012-04-25 | 2013-10-30 | 台湾积体电路制造股份有限公司 | Backside illuminated image sensor with negatively charged layer |
| CN104103654A (en) * | 2013-04-04 | 2014-10-15 | 全视科技有限公司 | Image sensor and imaging device |
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Application publication date: 20170707 |