CN106935581A - A kind of memory cell for reducing static discharge interference - Google Patents
A kind of memory cell for reducing static discharge interference Download PDFInfo
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- CN106935581A CN106935581A CN201511010622.3A CN201511010622A CN106935581A CN 106935581 A CN106935581 A CN 106935581A CN 201511010622 A CN201511010622 A CN 201511010622A CN 106935581 A CN106935581 A CN 106935581A
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- memory cell
- static discharge
- reduce
- ground
- storage capacitance
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
Abstract
The present invention provides a kind of memory cell for reducing static discharge interference, and the memory cell includes：First phase inverter, the second phase inverter, first phase inverter join end to end with the second phase inverter input and output；Storage capacitance between memory cell input and output end, the storage capacitance be suitable to input supply voltage decrease below ground when and/or output end be increased above supply voltage when, reduce because of the disturbance burr time on power supply and ground caused by static discharge interference, reduce static discharge interference.
Description
Technical field
Invention is related to anti-ESD fields, more particularly to a kind of memory cell for reducing static discharge interference.
Background technology
Esd refers to the transfer of electrostatic charge between object of the object with different electrostatic potentials caused by directly contact or electrostatic induction.It is often referred to after ELECTROSTATIC FIELD ENERGY reaches to a certain degree, the phenomenon for puncturing medium therebetween and being discharged.Esd causes electronic building brick failure to be divided into three kinds of situations：（One）Hardware failure：Esd arc voltages scurry into inside semiconductor the situation for making insulation division bit loss bad.Such as in the short circuit of P-N abutments or open circuit, the oxide layer of built-in electrical insulation runs through, and metal oxidation treatment site produces corrosion etc..（Two）Latent failure：Though system is temporarily affected when esd occurs, still can continue action, function can gradually be deteriorated over time, exception occur every system after a few days or several weeks, finally as hardware failure.（Three）Field intensity sensing failure：The electrion spark of esd can produce electric field radiation effect with electric current, and the radiation of this bandwidth often makes the circuit for closing on be interfered not normal, such as latch-up, or temporary program entanglement, and data loss etc., hardware can be more damaged when serious as permanent hardware failure.
In the third situation of esd failures, the electric field radiation effect that esd is produced causes the data that digital internal register is stored to change, and causes the display effect of display device to go wrong, such as there is white screen, the phenomenons such as Hua Ping, picture exception, and a kind of solution for being given.
In the application of lcd, the elementary cell of numeral is provided by foundries, and digital domain is produced by software automatic placement and routing.When being esd for whole chip and process, the esd protections for digital module can be done and process：
（One）：The ground of numeral is separated with the ground of pad, with single ground pad, or the independent lead from ground pad.
（Two）：Its power supply to the path of releasing on ground can be increased in digital module periphery.The unit of its path of releasing substantially can be ggnmos（Grid ground NMOS）, gate-couple-technique（Grid coupling technique）, dynamic-gate-circuit（Dynamic gate circuit）, gate-driven-circuit（Gate driving circuit）Etc. way.
（Three）：The electric capacity to ground can be powered up around digital module, comes stabilized power source and ground potential.
（Four）：For the interface signal of digital module, the esd protections of input can be done to the signal that numeral is passed in simulation：The general protection device used can be resistance, diode, metal oxide device, thick oxide layer device, thyristor etc..
Therefore the static discharge interference for how preventing the field intensity sensing failure type of electronic device is the problem found extensively in the industry.
The content of the invention
To reduce the static discharge interference of memory cell, the present invention provides a kind of memory cell for reducing static discharge interference, and the memory cell includes：First phase inverter, the second phase inverter, first phase inverter join end to end with the second phase inverter input and output；Storage capacitance between memory cell input and output end, the storage capacitance be suitable to input supply voltage decrease below ground when and/or output end be increased above supply voltage when, reduce because of the disturbance burr time on power supply and ground caused by static discharge interference, reduce static discharge interference.
Preferably, the electric capacity of the storage capacitance is set to discharge the electric charge time less than power supply or the burr time on ground.
Preferably, the storage capacitance is passive device；The storage capacitance is MIP electric capacity or MIM capacitor.
Preferably, the MIM capacitor is the electric capacity between adjacent metal.
Preferably, the memory cell also includes：Increase the first power supply release path between the power supply and ground of output end window, and/or increase second source release path between the power supply and ground of output end window.
Preferably, first power supply release path, second source release path are ggnmos, gate-couple-technique, dynamic-gate-circuit, gate-driven-circuit any one.
Preferably, it is set forth in input window and/or output end window is respectively provided with the second storage capacitance, the 3rd storage capacitance.
Preferably, the memory cell is：Register, trigger.
The present invention proposes a kind of memory cell for preventing static discharge from disturbing, and storage capacitance is increased between memory cell input and output end, reduces because of the disturbance burr time on power supply and ground caused by static discharge interference, reduces static discharge interference.Increase the first power supply release path between the power supply and ground of output end window, and/or increase second source release path between the power supply and ground of output end window, further improve the impact capacity of ESD, optimize the ability of anti-ESD.
Brief description of the drawings
The following detailed description to non-limiting example is read by referring to accompanying drawing, other features, objects and advantages of the invention will become more apparent upon.
Fig. 1 is the schematic diagram of the memory cell of reduction static discharge interference in one embodiment of the invention；
Fig. 2 is the circuit diagram of the memory cell of reduction static discharge interference in one embodiment of the invention；
Fig. 3 is the schematic diagram of the memory cell of reduction static discharge interference in another embodiment of the present invention；
Fig. 4 is the schematic diagram of the memory cell of reduction static discharge interference in yet another embodiment of the invention；
In figure, through different diagrams, same or similar reference represents same or analogous device（Module）Or step.
Specific embodiment
In the specific descriptions of following preferred embodiment, by the accompanying drawing with reference to appended by constituting a present invention part.Appended accompanying drawing has been illustrated by way of example can realize specific embodiment.The embodiment of example is not intended as limit all embodiments of the invention.It is appreciated that without departing from the scope of the present invention, it is possible to use other embodiment, it is also possible to carry out structural or logicality modification.Therefore, specific descriptions below are simultaneously nonrestrictive, and the scope of the present invention is defined by the claims appended hereto.
The present invention provides a kind of memory cell for reducing static discharge interference, it is characterised in that the memory cell includes：First phase inverter, the second phase inverter, first phase inverter join end to end with the second phase inverter input and output；Storage capacitance between memory cell input and output end, the storage capacitance be suitable to input supply voltage decrease below ground when and/or output end be increased above supply voltage when, reduce because of the disturbance burr time on power supply and ground caused by static discharge interference, reduce static discharge interference.
This case is specifically described with reference to specific embodiment,
First embodiment
Fig. 1, Fig. 2 are refer to, Fig. 1 is the schematic diagram of the memory cell of reduction static discharge interference in one embodiment of the invention；
Fig. 2 is the circuit diagram of the memory cell of reduction static discharge interference in one embodiment of the invention；Treatment to digital basic unit of storage, can strengthen the ability of its anti-esd interference, such as Fig. 1：
In Fig. 1,101 is the latch structures of anti-esd interference in figure.On the basis of basic latch, a passive capacitive 102 is added between input and output.Right figure in physical circuit such as Fig. 1.Including the passive capacitive 102 between input and output node, pmos pipes 103, nmos pipes 104, pmos pipes 105 and nmos pipes 106.
The specific course of work refer to Fig. 2：
In Fig. 2, it is assumed that voltage is store in latch, a points are high potential 1（VDD）, b points are ground potential 0（GND）.The high potential that a points are pinned disconnects 103pmos pipes, and 104nmos pipes are opened, and it is 0 to hale b points, the more stable formation positive feedback for being locked the low potential of b points.The low potential that b points are pinned simultaneously opens 105pmos pipes, the shut-off of 106nmos pipes, and it is 1 that a points are haled, and makes locked more stable of high level of a points,.If power vd D has shake between ground GND, if VDD does not shake do not shaken higher than in the case of VDD less than GND or GND, all without influence a points and the data of b point pokes, the data of memory cell output are constant after power good.
But in the case of being impacted in strong esd, the inside of digital module occurs of short duration VDD shakes less than GND or GND situations of the shake higher than VDD.In this case, in latch the state of pipe not in the range of normal work.As shown in Fig. 2 for 103pmos pipes, temporarily listing the parasitic diode D1 and D2 of its source electrode and drain electrode to substrate, and its drain electrode to the parasitic capacitance C1 of substrate.For 104nmos pipes, the parasitic diode D4 and D3 of its source electrode and drain electrode to substrate, and its drain electrode are temporarily listed to the parasitic capacitance C2 of substrate.For 105pmos pipes, the parasitic diode D5 and D6 of its source electrode and drain electrode to substrate, and its drain electrode are temporarily listed to the parasitic capacitance C3 of substrate.For 106nmos pipes, the parasitic diode D8 and D7 of its source electrode and drain electrode to substrate, and its drain electrode are temporarily listed to the parasitic capacitance C4 of substrate.When ESD causes VDD to shake downwards, if VDD is higher than GND, node a can follow the change of VDD, because VDD is higher than still GND, so the data latched in latch after power good will not change, if VDD drops below the threshold voltage of pmos pipes, such as 105pmos pipes exit linear zone, have entered into saturation region.Node a can still be slightly below VDD and follow the VDD to reduce this when, and now VDD is higher than still GND.After power supply and ground recover from shake, the data in latch can still be recovered.But if when VDD continues to drop below GND current potentials, the pipe in latch is no longer interval in normal work.This when, substrate understood positively biased to the parasitic diode of source and drain for nmos and pmos pipes, for node a.105pmos's drain to substrate parasitics diode D6 positively biaseds, and 106nmos pipes drain to substrate parasitics diode D7 positively biaseds.This when, the voltage of node a was just determined by the conducting resistance of parasitic diode D6 and D7.Because this when of VDD has been less than GND.If so after the electric charge of node a is released completely completely.A points cannot again preserve the original information of latch, and the current potential of storage is negative potential.Similarly for node b, current potential is also the negative potential determined by the conducting resistance of parasitic diode after its electric charge of having been released completely, and b points can not again preserve the original information of latch.Even if after VDD returns to normal condition.The information of Latch can be written over.
For above-mentioned situation, the present invention has been put into storage capacitance 102 between node a and node.When VDD drops below GND, node a and node b can release electric charge, the conducting resistance of the speed that it is released and parasitic diode, and the parasitic capacitance of substrate and source and drain, and substrate is relevant with the dead resistance of source and drain.The presence of storage capacitance 102 makes the electric charge of its storage more, while making its time released in the case of electric charge of releasing become slow.The power jitter caused due to esd generation time on the power supply of digital module be 10nS within burr, so its influence for bringing can be weakened by the electric capacity of small area in piece completely according to the time.The time of the time less than burr on VDD for being defined as making its electric charge of releasing of its capacitance.Because can not released completely, VDD recovers the normal rear potential difference that still there is its original orientation between a nodes and b nodes to the storage electric charge of a nodes and b nodes, so initial data can still be recovered when VDD recovers normal.Due to needing the memory node information of storage capacitance 102, and all without its internal charge is influenceed when VDD and GND acute variations, so it is not active device to need storage capacitance 102.Selection storage capacitance 102 is passive device, can be MIP electric capacity or MIM capacitor.Because the placement-and-routing of digital domain typically only selects m1 and m2 i.e., adjacent metal level.So selection MIP or the electric capacity between M1 and M2 are proper, unwanted layers will not be so taken.The increase of area is also few simultaneously, to the influence very little of the cost of chip.
Second embodiment
Please continue to refer to Fig. 3, Fig. 3 is the schematic diagram of the memory cell of reduction static discharge interference in another embodiment of the present invention；When the interference of esd produces big shake between digital internal power supply and ground, when node on latch can not store initial data, increase the ability that storage capacitance 302 can improve its anti-esd impact in input and output stage, and can be processed with adding locally supplied power source to discharge path.Elementary cell power supply and ground input window position increase power supply to ground release path, or power supply to ground the second storage capacitance 303 and the 3rd storage capacitance 304.General way is all that the protection of esd is carried out to overall digital circuit, and its releasing unit is the periphery for being made in overall digital module.Here protection has been made in inside digital basic unit, has been placed on power supply and ground enters the window's position of module.When esd impacts enter digital internal, internal the first power supply release path 303 and second source release path 304 can shorten times of the vdd less than gnd or gnd higher than vdd, the time of the node discharge in the case of large disturbances can be reduced, the ability of the anti-esd disturbances of enhancing internal storage unit is played.Work and can reduce the size for being added to storage capacitance 302 in memory cell with storage capacitance 302 1 simultaneously.Requirement according to actual conditions balances 302 and 303 and 304 ratios for adding.It is selectable on the basis of storage capacitance 302 is set, the first power supply release path 303 is increased between the power supply and ground of output end window, and/or increase second source release path 304 between the power supply and ground of output end window.It can be electric capacity of voltage regulation, or the module ggnmos that releases that first power supply discharges path 303 and second source release path 304（Grid ground NMOS）, gate-couple-technique（Grid coupling technique）, dynamic-gate-circuit（Dynamic gate circuit）, gate-driven-circuit（Gate drive circuit）Deng.
In the present invention, memory cell 301 can be basic unit of storage latch, or register, the structure such as trigger.For example, if the structure of master-slave flip-flop.Its storage capacitance only needs to increase in master flip-flop.
Fig. 4 is refer to, Fig. 4 is the schematic diagram of the memory cell of reduction static discharge interference in yet another embodiment of the invention, in master-slave flip-flop, in the storage capacitance 401 that main offence device is added.
A kind of memory cell for preventing static discharge from disturbing of the present invention, increases storage capacitance between memory cell input and output end, reduces because of the disturbance burr time on power supply and ground caused by static discharge interference, reduces static discharge interference.Increase the first power supply release path between the power supply and ground of output end window, and/or increase second source release path between the power supply and ground of output end window, further improve the impact capacity of ESD.Optimize the ability of anti-ESD.
It is obvious to a person skilled in the art that the invention is not restricted to the details of above-mentioned one exemplary embodiment, and without departing from the spirit or essential characteristics of the present invention, can in other specific forms realize the present invention.Therefore, from the point of view of anyway, embodiment all should be regarded as exemplary, and be nonrestrictive.Additionally, it will be evident that " including " word is not excluded for other elements and step, and wording " one " is not excluded for plural number.The multiple element stated in device claim can also be realized by an element.The first, the second grade word is used for representing title, and is not offered as any specific order.
Claims (8)
1. it is a kind of to reduce the memory cell that static discharge is disturbed, it is characterised in that the memory cell includes：
First phase inverter, the second phase inverter, first phase inverter join end to end with the second phase inverter input and output；
Storage capacitance between memory cell input and output end, the storage capacitance be suitable to input supply voltage decrease below ground when and/or output end be increased above supply voltage when, reduce because of the disturbance burr time on power supply and ground caused by static discharge interference, reduce static discharge interference.
2. it is according to claim 1 to reduce the memory cell that static discharge is disturbed, it is characterised in that the electric capacity of the storage capacitance is set to discharge the electric charge time less than power supply or the burr time on ground.
3. it is according to claim 1 to reduce the memory cell that static discharge is disturbed, it is characterised in that the storage capacitance is passive device；The storage capacitance is MIP electric capacity or MIM capacitor.
4. it is according to claim 3 to reduce the memory cell that static discharge is disturbed, it is characterised in that the MIM capacitor is the electric capacity between adjacent metal.
5. it is according to claim 1 to reduce the memory cell that static discharge is disturbed, it is characterised in that the memory cell also includes：Increase the first power supply release path between the power supply and ground of output end window, and/or increase second source release path between the power supply and ground of output end window.
6. it is according to claim 5 to reduce the memory cell that static discharge is disturbed, characterized in that, the first power supply release path, second source release path are grid ground NMOS technologies, grid coupling technique, dynamic gate circuit, gate drive circuit any one.
7. it is according to claim 5 to reduce the memory cell that static discharge is disturbed, it is characterised in that to be set forth in input window and/or output end window is respectively provided with the second storage capacitance, the 3rd storage capacitance.
8. the memory cell for reducing static discharge interference according to claim 1, it is characterised in that the memory cell is：Register, trigger.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511010622.3A CN106935581B (en) | 2015-12-30 | 2015-12-30 | Memory unit for reducing electrostatic discharge interference |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511010622.3A CN106935581B (en) | 2015-12-30 | 2015-12-30 | Memory unit for reducing electrostatic discharge interference |
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| CN106935581A true CN106935581A (en) | 2017-07-07 |
| CN106935581B CN106935581B (en) | 2020-11-17 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117060364A (en) * | 2023-10-12 | 2023-11-14 | 芯耀辉科技有限公司 | Electrostatic clamp and chip |
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