CN110491874B - Electrostatic protection circuit and panel - Google Patents
Electrostatic protection circuit and panel Download PDFInfo
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- CN110491874B CN110491874B CN201910779077.6A CN201910779077A CN110491874B CN 110491874 B CN110491874 B CN 110491874B CN 201910779077 A CN201910779077 A CN 201910779077A CN 110491874 B CN110491874 B CN 110491874B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
Abstract
The invention discloses an electrostatic protection circuit and a panel, which are used for solving the problem of low reliability of the electrostatic protection circuit in the related technology. The electrostatic protection circuit includes: the first electrostatic discharge circuit and the second electrostatic discharge circuit are respectively used for discharging electrostatic charges from the first end of the electrostatic protection circuit to the second end of the electrostatic protection circuit, and the second electrostatic discharge circuit is used for delaying the discharge of the electrostatic charges compared with the first electrostatic discharge circuit. After the first static discharge loop is melted down, the second static discharge loop can still work normally, and the reliability of the static protection circuit is improved.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to an electrostatic protection circuit and a panel.
Background
During the manufacturing process, the rubbing may cause the array substrate to be electrostatically charged. The mechanism is the transfer of electrostatic charges between objects having different electrostatic charge potentials due to direct contact or electrostatic induction. ESD (Electro-Static Discharge) generally refers to a phenomenon in which after the energy of an electrostatic field reaches a certain level, a dielectric is broken down to Discharge. ESD typically damages the interface device to which it is connected, and in another case, devices subjected to ESD shock may not be damaged immediately, but rather performance degradation leads to premature product failure. In the current production, the mode of adding an electrostatic discharge loop is generally adopted to reduce electrostatic breakdown. However, in the currently used electrostatic discharge circuit, once the current is too large, the electrostatic discharge circuit is fused, and when secondary ESD occurs at the same position, the connected interface device cannot be protected, and the reliability is low.
Disclosure of Invention
In view of the above, an objective of the present invention is to provide an electrostatic protection circuit and a panel, which are used to solve the problem of low reliability of an electrostatic discharge circuit in the related art.
According to a first aspect of the present invention, there is provided an electrostatic protection circuit including: the first electrostatic discharge circuit and the second electrostatic discharge circuit are respectively used for discharging the electrostatic charge from the first end of the electrostatic protection circuit to the second end of the electrostatic protection circuit, and the second electrostatic discharge circuit delays the discharge of the electrostatic charge compared with the first electrostatic discharge circuit.
Optionally, the first electrostatic discharge circuit includes a first switch element, the first switch element is connected to a first end of the electrostatic protection circuit, and the first switch element is configured to be turned on when a voltage of the first end is greater than an on voltage of the first switch element, so as to discharge electrostatic charges from the first end to a second end of the electrostatic protection circuit; the second electrostatic discharge circuit comprises a second switch element and a first delay circuit connected with the second switch element, the second switch element is used for conducting when the voltage of the first end is larger than the turn-on voltage of the second switch element, and the first delay circuit is used for absorbing the electrostatic charge from the first end of the electrostatic protection circuit, so that the second electrostatic discharge circuit delays to discharge the electrostatic charge compared with the first electrostatic discharge circuit.
Optionally, the first delay release circuit includes a third switching element and a first capacitor, a control electrode of the third switching element is connected to the first electrode of the second switching element, the second electrode of the third switching element and one end of the first capacitor, and the first electrode of the third switching element is connected to the other end of the first capacitor and the second end of the electrostatic protection circuit.
Optionally, the control electrode and the second electrode of the first switching element are connected to the first end of the electrostatic protection circuit, and the first electrode of the first switching element is connected to the second end of the electrostatic protection circuit.
Optionally, the control electrode and the first electrode of the second switching element are connected to the first end of the electrostatic protection circuit, the first electrode of the second switching element is connected to the first delay release circuit, and the first delay release circuit is connected to the second end of the electrostatic protection circuit.
Optionally, the electrostatic protection circuit further includes: and the reverse electrostatic discharge loop is used for discharging the electrostatic charge flowing from the second end of the electrostatic protection circuit to the first end of the electrostatic protection circuit.
Optionally, the reverse electrostatic discharge circuit includes: a first sub-reverse electrostatic discharge circuit, the first sub-reverse electrostatic discharge circuit comprising: and a control electrode and a second electrode of the fourth switching element are connected with the second end of the electrostatic protection circuit, and a first electrode of the fourth switching element is connected with the first end of the electrostatic protection circuit.
Optionally, the reverse electrostatic discharge circuit further comprises: a second sub-reverse electrostatic discharge circuit, the second sub-reverse electrostatic discharge circuit comprising: and a second pole and a control pole of the fifth switching element are connected with the second end of the electrostatic protection circuit, and a first pole of the fifth switching element is connected with the first end of the electrostatic protection circuit.
Optionally, the second sub-reverse electrostatic discharge circuit further includes: and one end of the second delay release circuit is connected with the first end of the electrostatic protection circuit, the other end of the second delay release circuit is connected with the first pole of the fifth switch element, and the second delay release circuit is used for enabling the second sub-reverse electrostatic discharge loop to release electrostatic charges in a delay way compared with the first sub-reverse electrostatic discharge loop.
Optionally, the second delay release circuit includes a sixth switching element and a second capacitor, a control electrode of the sixth switching element is connected to one end of the second capacitor, a second electrode of the sixth switching element, and a first electrode of the fifth switching element, and the first electrode of the sixth switching element is connected to the other end of the second capacitor and the first end of the electrostatic protection circuit.
According to a second aspect of the present invention, there is provided a panel comprising: an electrostatic protection circuit according to any one of the first aspect of the present invention.
It can be seen from the above description that, the electrostatic protection circuit provided by the present invention has the first electrostatic discharge circuit and the second electrostatic discharge circuit with a function of delaying electrostatic discharge, and since the second electrostatic discharge circuit delays electrostatic discharge from the first electrostatic discharge circuit, even if the electrostatic ring is subjected to electrostatic discharge and the current is too large, the first electrostatic discharge circuit can be fused prior to the second electrostatic discharge circuit, and the second electrostatic discharge circuit can still work effectively, thereby improving the reliability of the electrostatic discharge circuit.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description only relate to some embodiments of the present invention and are not limiting on the present invention.
FIG. 1 is a schematic diagram illustrating an electrostatic protection circuit according to an exemplary embodiment;
FIG. 2 is a schematic diagram illustrating an electrostatic protection circuit in accordance with an exemplary embodiment;
fig. 3 is a schematic diagram illustrating an electrostatic protection circuit according to an example embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
Fig. 1 is a schematic diagram illustrating an electrostatic protection circuit according to an exemplary embodiment, as shown in fig. 1, the circuit including:
the first esd circuit 11 (as shown in fig. 1, may include a loop from the first end S1 of the esd protection circuit to the second end S2 of the esd protection circuit through the first esd circuit) and the second esd circuit 12 (as shown in fig. 1, may include a loop from the first end S1 of the esd protection circuit to the second end S2 of the esd protection circuit through the second esd circuit), the first esd circuit S1 and the second esd circuit 12 are respectively used for discharging the electrostatic charges from the first end S1 of the esd protection circuit to the second end S2 of the esd protection circuit, and the second esd circuit 12 is used for discharging the electrostatic charges after delaying the discharge of the electrostatic charges from the first end S2 of the esd protection circuit compared with the first esd circuit 11, wherein a direction indicated by an arrow shown in fig. 1 represents a flow direction of the electrostatic charges.
The electrostatic protection circuit provided by the embodiment of the invention is provided with the first electrostatic discharge loop and the second electrostatic discharge loop for delaying the electrostatic discharge, and the second electrostatic discharge loop delays the electrostatic discharge compared with the first electrostatic discharge loop, so that even if the electrostatic ring is subjected to electrostatic discharge and the current is too large, the first electrostatic discharge loop can be melted down in preference to the second electrostatic discharge loop, the second electrostatic discharge loop can still work effectively, and the reliability of the electrostatic protection circuit is improved.
Fig. 2 is a schematic diagram illustrating an electrostatic protection circuit according to an exemplary embodiment, the circuit including, as shown in fig. 2:
a first electrostatic discharge circuit and a second electrostatic discharge circuit;
the first electrostatic discharge circuit includes a first switching element M1, the first switching element M1 is connected to a first terminal of the electrostatic protection circuit, the first terminal may be a Data Line (Data Line) terminal, for example, and the first switching element M1 is configured to be turned on when a voltage of the first terminal, for example, a voltage of an a node shown in fig. 2, is greater than an on voltage of the first switching element M1 to discharge electrostatic charges from the first terminal of the electrostatic protection circuit to a second terminal of the electrostatic protection circuit, which may be a serial communication port Bus (Com Bus Line), for example;
the second esd release circuit includes a second switch element M2 and a first esd release delay circuit 21 (shown as a portion in a dashed line box in fig. 2) connected to the second switch element M2, the second switch element M2 is configured to be turned on when a voltage at a first end of the esd protection circuit, for example, a voltage at a node a shown in fig. 2, is greater than an on voltage of the second switch element M2, and the first esd release delay circuit 21 is configured to enable the second esd release circuit to release electrostatic charges with a delay compared to the first esd release circuit.
In an implementation manner, the first delay releasing circuit 21 may include a third switching element M3 and a first capacitor C0, a control electrode of the third switching element M3 is connected to a first electrode of the second switching element M2, a second electrode of the third switching element M3 and one end of a first capacitor C0, a first electrode of the third switching element M3 is connected to the other end of the first capacitor C0 and a second end of the electrostatic protection circuit, and the first capacitor in the first delay releasing circuit 21 may consume a portion of the electrostatic charge from the first end of the electrostatic protection circuit, and may buffer the electrostatic discharge, so that the second electrostatic discharging circuit discharges the electrostatic charge slower than the first electrostatic discharging circuit. Still taking the esd protection circuit shown in fig. 2 as an example, when the first terminal of the esd protection circuit suddenly receives an electrostatic high voltage, M1 and M2 are turned on, and the first esd release loop guides the electrostatic charge to the second terminal of the esd protection circuit through M1; in the second esd release circuit, the capacitor C0 (which is an example of the first capacitor) has a certain buffering effect on the esd charges, so in the esd protection circuit according to the embodiment of the present invention, the second esd release circuit is a secondary esd release circuit, the first esd release circuit is fused prior to the second esd release circuit, and after the first esd release circuit is fused, the second esd release circuit can still work normally, thereby improving the reliability of the esd protection circuit.
In one implementation, in the first esd release loop, the control electrode and the second electrode of the first switching element M1 are connected to the first terminal of the esd protection circuit, and the first electrode of the first switching element M1 is connected to the second terminal of the esd protection circuit. Still taking the esd protection circuit shown in fig. 2 as an example, when the first terminal of the esd protection circuit suddenly receives an esd high voltage, the node a is at a high level H, which is applied to the gates of M1 and M2, so that M1 and M2 are turned on; meanwhile, the node B is also at the high level H, and the high level is input into the node G and the node C through the opening of M1 and M2; the electrostatic charge on the node G directly flows to the node F, and then flows to the second end of the electrostatic protection circuit, and the electrostatic discharge process of the first electrostatic discharge circuit is completed.
In an implementation manner, in the second esd loop, the control electrode and the first electrode of the second switch element M2 are connected to the first end of the esd protection circuit, the first electrode of the second switch element M2 is connected to the first delay circuit 11, the first delay circuit 11 is connected to the second end of the esd protection circuit, and still taking the esd protection circuit shown in fig. 2 as an example, a part of the electrostatic charge at the node C flows to the capacitor C0 to charge the capacitor, and another part of the electrostatic charge acts on the control electrode of M3 to turn on the M3, and flows to the node E through the M3 to flow to the second end of the esd protection circuit, and the esd discharge process of the second esd loop is finished. In this process, since the capacitor C0 consumes a part of the charges and acts as a buffer for the second esd release circuit, the second esd release circuit releases the static electricity at a slower speed than the first esd release circuit, and thus the first esd release circuit is fused preferentially over the second esd release circuit if the second esd release circuit is fused.
In one implementation, the electrostatic protection circuit may further include: still taking the electrostatic protection circuit shown in fig. 2 as an example, the reverse electrostatic discharge circuit is used for discharging electrostatic charges flowing from the second terminal of the electrostatic protection circuit to the first terminal of the electrostatic protection circuit, and for example, the reverse electrostatic discharge circuit can discharge electrostatic charges from the Com Bus Line terminal to the Data Line terminal.
Fig. 3 is a schematic diagram illustrating an electrostatic protection circuit according to an exemplary embodiment, and as shown in fig. 3, the reverse electrostatic discharge circuit may include: a first sub-reverse electrostatic discharge circuit, the first sub-reverse electrostatic discharge circuit comprising: the fourth switching element M4, the control electrode and the second electrode of the fourth switching element M4 are connected to the second terminal of the electrostatic protection circuit, and the first electrode of the fourth switching element M4 is connected to the first terminal of the electrostatic protection circuit. As shown in FIG. 3, when the electrostatic charge flows from the Com Bus Line to the Data Line, the Com Bus Line is suddenly subjected to an electrostatic high voltage, the node F is at a high level H, and the electrostatic charge at the node flows to the nodes G and E; the high level H of the node G acts on the control electrode of the fourth switching element M4, so that M4 is turned on, the electrostatic charge of the node F flows to the node H through M4, and further flows to Data Line, and the electrostatic discharge process of the first sub-reverse electrostatic discharge loop is ended.
In one implementation, as shown in fig. 3, the reverse electrostatic discharge circuit may further include: a second sub-reverse electrostatic discharge circuit, which may include: the second pole and the control pole of the fifth switching element M5, M5 are connected to the second terminal of the electrostatic protection circuit, and the first pole of the fifth switching element M5 is connected to the first terminal of the electrostatic protection circuit.
In one implementation, as shown in fig. 3, the second sub-reverse electrostatic discharge loop may further include: and a second delay circuit 22, wherein one end of the second delay circuit 22 is connected to the first end of the esd protection circuit, the other end of the second delay circuit 22 is connected to the first pole of the fifth switch element M5, and the second delay circuit 22 is configured to delay the second sub-reverse esd discharging loop from discharging the electrostatic charge compared to the first sub-reverse esd discharging loop.
In one implementation, as shown in fig. 3, the second delay releasing circuit may include a sixth switching element M6 and a second capacitor C1, a control electrode of the sixth switching element M6 is connected to one end of the second capacitor C1, a second electrode of the sixth switching element M6 and a first electrode of a fifth switching element M5, and a first electrode of the sixth switching element M6 is connected to the other end of the second capacitor C1 and a first end of the electrostatic protection circuit. Still taking the esd protection circuit shown in fig. 3 as an example, the high level H of the node E is applied to the gate of M4, so that M4 is turned on, and the electrostatic charge of the node F flows to the node D through M4; the node D is at a high level, the electrostatic charge at the node flows to the capacitor C1 on one hand, and charges the capacitor C1, the high point at the node is flatly applied to the control electrode of M6, so that M6 is turned on, and the electrostatic charge flows to the node H through M6, and then flows to Data Line, and the electrostatic discharge process of the second electrostatic discharge loop is finished. The capacitor C1 consumes part of the charge and acts as a buffer for electrostatic discharge, so that the second sub-reverse electrostatic discharge loop discharges static electricity slower than the first sub-reverse electrostatic discharge loop. Therefore, if the fuse occurs, the first sub-reverse electrostatic discharge circuit is fused prior to the second sub-reverse electrostatic discharge circuit. That is, when the M4 of the first sub-reverse electrostatic discharge circuit is destroyed, the second sub-reverse electrostatic discharge circuit can still work normally.
The electrostatic protection circuit of the embodiment of the invention comprises two electrostatic discharge loops, wherein the second electrostatic discharge loop can delay the discharge of static electricity compared with the first electrostatic discharge loop, in the two electrostatic discharge loops, the static electricity is preferentially discharged through the first electrostatic discharge loop, when the input end (such as the first end or the second end) of the electrostatic protection circuit is subjected to sudden electrostatic high voltage, the first electrostatic discharge loop is preferentially melted, and when the first electrostatic discharge loop is melted, the second electrostatic discharge loop can still normally work, thereby achieving the purpose of secondary electrostatic protection. Meanwhile, in the normal use process of the panel, the probability that the panel is subjected to more than two times of ESD is low, so that the panel with two electrostatic discharge circuits provided by the embodiment of the invention can sufficiently meet the requirement of electrostatic protection in actual production, and the reliability is high.
Embodiments of the present invention further provide a panel, such as a display panel, which may include any one of the above electrostatic protection circuits provided in embodiments of the present invention.
The switching element in each of the above embodiments may be a Transistor, which may be independently selected from one of a polycrystalline silicon Thin Film Transistor, an amorphous silicon Thin Film Transistor, an oxide Thin Film Transistor, and an organic Thin Film Transistor, and may be, for example, a Thin Film Transistor (TFT). The "control electrode" referred to in this embodiment may specifically refer to a gate or a base of a transistor, the "first electrode" may specifically refer to a source or an emitter of the transistor, and the corresponding "second electrode" may specifically refer to a drain or a collector of the transistor.
In addition, the first switch element M1, the second switch element M2, the third switch element M3, the fourth switch element M4, the fifth switch element M5 and the sixth switch element M6 in the above embodiments are all N-type transistors, which is a preferable solution that is convenient to implement in this embodiment, and does not limit the technical solution of the present invention. It should be understood by those skilled in the art that the type (N-type or P-type) of each transistor and the polarities of the output voltages of each power source terminal and the control signal line are simply changed to implement the same on or off operation for each transistor as in the present embodiment, and all of them belong to the protection scope of the present application. The specific cases are not illustrated here.
The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except for the gate, one of the two poles is referred to as a source, and the other pole is referred to as a drain. Further, the transistors may be classified into N-type transistors or P-type transistors according to their characteristics. In the driving circuit provided by the embodiment of the present invention, all the transistors are illustrated as N-type transistors, and it is conceivable that those skilled in the art can easily conceive of the implementation of P-type transistors without creative efforts, and therefore, the present invention is also within the protection scope of the embodiment of the present invention.
In the embodiment of the invention, the first electrode is the source and the second electrode is the drain for the N-type transistor, and the first electrode is the drain and the second electrode is the source for the P-type transistor.
The display device in this embodiment may be: any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator and the like.
The technical scheme of the invention is explained in detail in the above with reference to the accompanying drawings, and it is considered that in the prior art, the source and drain electrodes and the active layer are in different layers, so that the thickness of the substrate is large, and the manufacturing process is complex. According to the technical scheme, the source electrode, the drain electrode, the data line and the active layer can be prepared in the same layer by doping the copper nitride, so that the thickness of the array substrate is reduced, and the manufacturing process of the array substrate is simplified.
It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intermediate layer or element can also be present. Like reference numerals refer to like elements throughout.
In the present invention, the terms "first", "second", "third", and "fourth" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "plurality" means two or more unless expressly limited otherwise.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Those of ordinary skill in the art will understand that: the invention is not to be considered as limited to the specific embodiments thereof, but is to be understood as being modified in all respects, all changes and equivalents that come within the spirit and scope of the invention.
Claims (7)
1. An electrostatic protection circuit, comprising:
the first electrostatic discharge circuit comprises a first switch element, the first switch element is connected with a first end of the electrostatic protection circuit, and the first switch element is used for conducting when the voltage of the first end is greater than the turn-on voltage of the first switch element so as to discharge electrostatic charges from the first end to a second end of the electrostatic protection circuit;
the second electrostatic discharge loop comprises a second switch element and a first delay release circuit connected with the second switch element, the control electrode and the first electrode of the second switch element are connected with the first end, and the second electrode of the second switch element is connected with the first delay release circuit;
the second switch element is used for conducting when the voltage of the first end is greater than the turn-on voltage of the second switch element, and the first delay release circuit is used for absorbing the electrostatic charge from the first end so as to enable the second electrostatic release circuit to release the electrostatic charge in a delay way compared with the first electrostatic release circuit;
the first delay release circuit comprises a third switching element and a first capacitor, wherein a control electrode of the third switching element is connected with a second electrode of the second switching element, the second electrode of the third switching element and one end of the first capacitor, and a first electrode of the third switching element is connected with the other end of the first capacitor and the second end of the first capacitor.
2. The electrostatic protection circuit according to claim 1, further comprising:
and the reverse electrostatic discharge loop is used for discharging the electrostatic charge flowing from the second end of the electrostatic protection circuit to the first end of the electrostatic protection circuit.
3. The esd protection circuit of claim 2, wherein the reverse esd release loop comprises:
a first sub-reverse electrostatic discharge circuit, the first sub-reverse electrostatic discharge circuit comprising: and a control electrode and a second electrode of the fourth switching element are connected with the second end of the electrostatic protection circuit, and a first electrode of the fourth switching element is connected with the first end of the electrostatic protection circuit.
4. The esd protection circuit of claim 3, wherein the reverse esd release loop further comprises:
a second sub-reverse electrostatic discharge circuit, the second sub-reverse electrostatic discharge circuit comprising: and a second pole and a control pole of the fifth switching element are connected with the second end of the electrostatic protection circuit, and a first pole of the fifth switching element is connected with the first end of the electrostatic protection circuit.
5. The ESD protection circuit of claim 4, wherein the second sub-reverse electrostatic discharge circuit further comprises:
and one end of the second delay release circuit is connected with the first end of the electrostatic protection circuit, the other end of the second delay release circuit is connected with the first pole of the fifth switch element, and the second delay release circuit is used for enabling the second sub-reverse electrostatic discharge loop to release electrostatic charges in a delay way compared with the first sub-reverse electrostatic discharge loop.
6. The ESD protection circuit of claim 5, wherein the second delay-release circuit comprises a sixth switching element and a second capacitor, a control electrode of the sixth switching element is connected to one end of the second capacitor, a second electrode of the sixth switching element and a first electrode of the fifth switching element, and the first electrode of the sixth switching element is connected to the other end of the second capacitor and the first end of the ESD protection circuit.
7. A panel, comprising:
an electrostatic protection circuit as claimed in any one of claims 1 to 6.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107123646A (en) * | 2017-05-25 | 2017-09-01 | 京东方科技集团股份有限公司 | A kind of electrostatic discharge protective circuit, electrostatic protection method, array base palte and display device |
| US9917079B2 (en) * | 2011-12-20 | 2018-03-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrostatic discharge protection circuit and method for radio frequency circuit |
| CN108512208A (en) * | 2018-05-26 | 2018-09-07 | 丹阳恒芯电子有限公司 | A kind of electrostatic discharge protective circuit in chip |
| CN109545782A (en) * | 2018-11-29 | 2019-03-29 | 上海华力集成电路制造有限公司 | A kind of electrostatic discharge protective circuit and semiconductor structure |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4320038B2 (en) * | 2007-03-16 | 2009-08-26 | Ｏｋｉセミコンダクタ株式会社 | Semiconductor integrated circuit |
| US10234887B2 (en) * | 2012-12-26 | 2019-03-19 | Allegro Microsystems, Llc | Output driver having reduced electromagnetic susceptibility and associated methods |
| CN103151769B (en) * | 2013-03-22 | 2015-05-06 | 无锡力芯微电子股份有限公司 | Electrostatic discharge protection circuit and integrated circuit |
| CN106611762B (en) * | 2017-01-11 | 2019-06-18 | 京东方科技集团股份有限公司 | Electrostatic discharge protective circuit, method and display device |
| CN110085585B (en) * | 2019-05-05 | 2021-02-02 | 深圳市华星光电半导体显示技术有限公司 | Electrostatic protection device and display panel |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9917079B2 (en) * | 2011-12-20 | 2018-03-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrostatic discharge protection circuit and method for radio frequency circuit |
| CN107123646A (en) * | 2017-05-25 | 2017-09-01 | 京东方科技集团股份有限公司 | A kind of electrostatic discharge protective circuit, electrostatic protection method, array base palte and display device |
| CN108512208A (en) * | 2018-05-26 | 2018-09-07 | 丹阳恒芯电子有限公司 | A kind of electrostatic discharge protective circuit in chip |
| CN109545782A (en) * | 2018-11-29 | 2019-03-29 | 上海华力集成电路制造有限公司 | A kind of electrostatic discharge protective circuit and semiconductor structure |
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