CN106934258B - Embedded system - Google Patents
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- CN106934258B CN106934258B CN201511030896.9A CN201511030896A CN106934258B CN 106934258 B CN106934258 B CN 106934258B CN 201511030896 A CN201511030896 A CN 201511030896A CN 106934258 B CN106934258 B CN 106934258B
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- 238000000034 method Methods 0.000 claims abstract description 16
- 238000013507 mapping Methods 0.000 claims description 35
- 230000003068 static effect Effects 0.000 claims description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- 238000013500 data storage Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000033772 system development Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/10—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM]
- G06F21/12—Protecting executable software
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
- G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
Abstract
The invention discloses an embedded system, comprising: the device comprises a flash memory controller, a CPU and a flash memory chip, wherein the flash memory controller is respectively connected with the CPU and the flash memory chip; the flash memory chip includes: a flash memory main storage area for storing general program data; the flash memory system configuration area is used for configuring state information of the flash memory chip; further comprises: a flash memory extended storage area for storing specific user data; the flash memory controller is used for interacting the state information of the flash memory chip with the flash memory system configuration area, reading the user data from the flash memory expansion storage area according to the state information of the flash memory chip, and executing the user data by the CPU or rewriting the user data stored in the flash memory expansion storage area; and is also used for performing read-write access to the flash memory main storage area. According to the technical scheme, the flash memory expansion storage area is increased to provide independent storage space for users, so that safe storage of private data of the users is realized, and meanwhile, the flash memory expansion storage area multiplexing method has the beneficial effects of multiplexing and no additional hardware cost.
Description
Technical Field
The embodiment of the invention relates to the technical field of computers, in particular to an embedded system.
Background
The microcontroller (Micro Control Unit, MCU) is very widely used, as small as a child toy and as large as engineering machinery can be used.
Most of the storage space in the current universal MCU chip is used indiscriminately by all users, namely the storage space shared by the users, and the data stored by the users are very easy to read and even rewrite by the users who can access the chip, so that the security of the data stored by the users is lower. Particularly, in some industry applications with very high confidentiality, when confidential information such as some key keys needs to be stored, some independent private storage space is usually required, but the existing MCU chip cannot independently meet the requirement of user-customized storage, and the implementation needs to be achieved by means of external connection to other chips, for example, by externally connecting a small flash Memory chip or EEPROM (Electrically Erasable Programmable Read-Only Memory) to the MCU chip, so as to store some key confidential information unique to the user.
However, by adopting the existing method of externally connecting other chips with the MCU chip, firstly, the MCU chip is required to support access to another flash memory chip or EEPROM; and secondly, the whole occupied space of other external chips can be increased, the workload of operators is increased, the operation is relatively complicated, and the cost and the system development difficulty are obviously increased.
Disclosure of Invention
The invention provides an embedded system to solve the security problem of user data storage.
The embodiment of the invention provides an embedded system, which comprises: a flash controller, a central processing unit (Central Processing Unit, CPU) and a flash chip, the flash controller being connected to the CPU and the flash chip, respectively; wherein,
the flash memory chip includes:
a flash memory main storage area for storing general program data;
a flash memory system configuration area for configuring state information of the flash memory chip;
the flash memory chip further includes:
a flash memory extended storage area for storing specific user data;
the flash memory controller is used for interacting the state information of the flash memory chip with the flash memory system configuration area, reading the user data from the flash memory expansion storage area according to the state information of the flash memory chip, and executing by the CPU or rewriting the user data stored in the flash memory expansion storage area; and the method is also used for performing read-write access on the flash memory main storage area.
Further, the flash memory controller includes:
a flash memory system bus interface;
a flash memory configuration register connected with the flash memory system bus interface;
The main control unit is respectively connected with the flash memory system bus interface and the flash memory configuration register;
the flash memory control unit is respectively connected with the flash memory configuration register, the main control unit and the flash memory chip;
the flash memory system bus interface is configured to send a first read instruction and a corresponding address sent by a system bus to the main control unit, where the first read instruction is used to perform read access on the flash memory extended storage area; the system is also used for sending a first write instruction and a corresponding address sent by the system bus to the main control unit, wherein the first write instruction is used for performing write access on the flash memory expansion storage area;
the flash memory configuration register is configured to automatically read status information of the flash memory chip in the flash memory system configuration area after the embedded system is powered on, where the status information of the flash memory chip includes: whether the flash memory expansion storage area is valid or not; mapping an address corresponding to the first read instruction or an address corresponding to the first write instruction interacted with the flash memory system bus interface into physical address information of the flash memory expansion storage area in the flash memory chip, and taking the physical address information as address mapping information of the flash memory expansion storage area; providing address mapping information of a flash memory expansion storage area and whether the flash memory expansion storage area is effective or not to the main control unit;
The main control unit is used for judging whether a first reading instruction sent by a system bus and a corresponding address are valid or not according to the address mapping information and the valid information of the flash memory expansion storage area, and if yes, the flash memory control unit is controlled to read user data stored in the flash memory expansion storage area of the flash memory chip; the flash memory control unit is further used for judging whether a first write instruction sent by the system bus and a corresponding address are valid or not according to the address mapping information and the valid information of the flash memory expansion storage area, and if yes, the flash memory control unit is controlled to rewrite user data stored in the flash memory expansion storage area of the flash memory chip;
and the flash memory control unit is used for reading or rewriting the user data stored in the flash memory expansion storage area in the flash memory chip according to the control of the main control unit.
Further, the flash configuration register includes:
an extended storage enabling register, configured to automatically read, after power-up, whether an extended storage area is valid or not from the flash memory system configuration area in the flash memory chip, and provide the valid information to the main control unit;
an extended memory mapped address register, configured to map an address corresponding to the first read instruction or an address corresponding to the first write instruction interacted with the flash memory system bus interface into physical address information of the flash memory extended memory area in the flash memory chip, and provide the physical address information as address mapped information of the flash memory extended memory area to the main control unit;
Correspondingly, the flash memory system bus interface is also used for directly performing read-write access on the flash memory configuration register.
Further, the flash configuration register further includes: a flash key register and/or a flash operation register;
the flash memory key register is used for storing a key for accessing the flash memory system configuration area in the flash memory chip;
the flash memory operation register is used for erasing, writing or reading the data of the flash memory system configuration area in the flash memory chip.
Further, the main control unit includes:
an operation control unit, configured to control the flash memory control unit to perform an erase, write or read operation on the flash memory chip;
and the extended storage address comparison unit is used for judging whether the received first read instruction and the corresponding address sent by the system bus or the sent first write instruction and the corresponding address are valid or not.
Further, the system further comprises: a static random access memory (Static Random Access Memory, SRAM) for storing general program data and user data in the flash memory chip after power-up;
the flash memory controller further includes: the SRAM control unit is respectively connected with the flash memory system bus interface, the main control unit, the flash memory control unit and the SRAM;
The main control unit is further configured to determine whether a first read instruction and a corresponding address sent by a system bus are valid according to the address mapping information and the valid information of the extended storage area, and if yes, control the SRAM control unit to read user data stored in the SRAM; the memory controller is also used for judging whether a first write instruction sent by a system bus and a corresponding address are valid or not according to the address mapping information and the valid information of the extended memory area, and if so, controlling the SRAM control unit to rewrite user data stored in the SRAM or controlling the flash memory control unit to rewrite the user data stored in the flash memory chip;
and the SRAM control unit is used for reading or rewriting the user data stored in the SRAM according to the control of the main control unit.
Further, the flash memory extended storage area comprises at least one flash memory extended storage block;
correspondingly, the extended storage enabling register is used for automatically reading whether any one or a plurality of flash memory extended storage blocks are effective information from the flash memory system configuration area in the flash memory chip after power-on, and providing the effective information to the main control unit.
Further, the extended memory mapped address register is further configured to map a plurality of different addresses corresponding to the first read instruction or addresses corresponding to the first write instruction interacted with the flash memory system bus interface to the same physical address information of the flash memory extended memory area in the flash memory chip, and provide the same physical address information as address mapping information of the flash memory extended memory area to the main control unit.
Further, the storage space of the flash memory expansion storage area is smaller than the storage space of the flash memory main storage area.
According to the technical scheme provided by the embodiment of the invention, the flash memory expansion storage area is added in the flash memory chip, so that the flash memory expansion storage area can be customized for special users to independently use, an independently used storage space is provided for the users, and any other users are invisible, so that the safe storage of private data of the users is realized, and the flash memory expansion storage area can be accessed by reading and writing through the flash memory controller; meanwhile, the flash memory chip generally has a plurality of idle spaces, and by adopting the technical scheme, the idle spaces of the flash memory chip can be used as a flash memory expansion storage area without increasing the area of the flash memory chip, meanwhile, a small flash memory chip or EEPROM (electrically erasable programmable read only memory) is externally connected, no extra hardware cost is required to be increased, and the method has the beneficial effects that the logic of reading and erasing the flash memory expansion storage area can be multiplexed with the logic of reading and erasing the flash memory main storage area.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:
fig. 1 is a schematic structural diagram of an embedded system according to a first embodiment of the present invention;
fig. 2A is a schematic structural diagram of an embedded system according to a second embodiment of the present invention;
FIG. 2B is a flowchart of a method for rewriting a configuration area of a flash memory system in a flash memory chip in an embedded system according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of an embedded system according to a third embodiment of the present invention;
FIG. 4A is a schematic diagram of a flash memory extended storage area according to a fourth embodiment of the present invention;
fig. 4B is a flowchart of a method for reading and writing an extended flash memory area of an embedded system according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Example 1
Fig. 1 is a schematic structural diagram of an embedded system according to an embodiment of the present invention, as shown in fig. 1, where the embedded system provided in the embodiment includes: a flash controller 110, a Central Processing Unit (CPU) 120, and a flash chip 130, the flash controller 110 being connected to the CPU120 and the flash chip 130, respectively; the CPU120 is configured to control operations of the flash controller 110 and the flash chip 130; flash memory chip 130 is readable and erasable, and the stored data information is not lost in the event of a power failure.
The flash memory controller 110 and the CPU120 are disposed on a main chip of the embedded system, and the main chip and the flash memory chip can be manufactured in the same package by adopting MCP (Multiple Chip Package) technology to form the embedded system.
In an embodiment of the present invention, the flash memory chip 130 includes: a flash main storage area 131 and a flash system configuration area 132.
The flash main memory area 131 is used for storing general program data, and is generally a memory area that is available to all users, and generally occupies a relatively large space in the flash chip 130, for example, several hundred kilobytes to several megabytes. The flash memory system configuration area 132 is used to configure status information of the flash memory chip. The flash memory system configuration area 132 is typically pre-configured in the flash memory chip, and during actual use, the flash memory system configuration area 132 is typically not visible or modifiable by a user. The flash memory system configuration area 132 is generally relatively small, and may vary from a few bytes to tens of bytes, for example.
The flash memory chip 130 further includes: the flash memory extension memory area 133 is used to store specific user data. The flash memory expansion storage area 133 is particularly suitable for storing user data with key confidentiality, such as passwords, etc., and the user data stored in the flash memory expansion storage area 133 cannot be directly accessed by any other user, so that the security and confidentiality of the user data can be effectively ensured, and the requirement of the user on independent storage of private data can be met.
The flash memory controller 110 is configured to interact with the flash memory system configuration area 132 to obtain status information of the flash memory chip 130, and read the user data from the flash memory expansion storage area 133, for execution by the CPU 120, or rewrite the user data stored in the flash memory expansion storage area 133; but also for read and write access to the flash main memory area 131. The operation of the embedded system to the flash memory chip 130 by the flash memory controller 110 is generally mainly a read operation, and user data can be directly read from the flash memory chip 130; when the data in the flash memory chip 130 needs to be modified, a write operation may also be performed, where the write operation needs to erase the corresponding location in the flash memory chip 130 first, and then rewrite the data by programming.
According to the technical scheme provided by the embodiment of the invention, the flash memory expansion storage area is added in the flash memory chip, so that the flash memory expansion storage area can be customized for special users to independently use, an independently used storage space is provided for the users, and any other users are invisible, so that the safe storage of private data of the users is realized, and the flash memory expansion storage area can be accessed by reading and writing through the flash memory controller; meanwhile, the flash memory chip generally has a plurality of idle spaces, and by adopting the technical scheme, the idle spaces of the flash memory chip can be used as a flash memory expansion storage area without increasing the area of the flash memory chip, meanwhile, a small flash memory chip or EEPROM (electrically erasable programmable read only memory) is externally connected, no extra hardware cost is required to be increased, and the method has the beneficial effects that the logic of reading and erasing the flash memory expansion storage area can be multiplexed with the logic of reading and erasing the flash memory main storage area.
Example two
Fig. 2A is a schematic structural diagram of an embedded system according to a second embodiment of the present invention, as shown in fig. 2, and the preferred implementation scheme of the flash memory controller 210 is provided based on the above embodiment.
The flash memory controller 210 includes: a flash system bus interface 211, a flash configuration register 212, a main control unit 213, and a flash control unit 214.
Wherein the flash configuration register 212 is connected with the flash system bus interface 211; the main control unit 213 is connected to the flash memory system bus interface 211 and the flash memory configuration register 212, respectively; the flash control unit 214 is connected to the flash configuration register 212, the main control unit 213, and the flash chip 230, respectively.
A flash memory system bus interface 211, configured to send a first read instruction and a corresponding address sent by the system bus 220 to the main control unit 213, where the first read instruction is used for performing a read access to the flash memory extended storage area; and is further configured to send a first write instruction and a corresponding address sent by the system bus 220 to the master control unit 213, where the first write instruction is used to perform write access on the flash memory extended storage area specifically, and may be sent to the master control unit 213 through the control path 1.
The flash configuration register 212 is configured to automatically read status information of the flash chip 230 in the flash system configuration area after the embedded system is powered on, where the status information of the flash chip 230 includes: whether the flash memory expansion storage area is valid or not; mapping an address corresponding to the first read instruction or an address corresponding to the first write instruction interacted with the flash memory system bus interface 211 into physical address information of the flash memory expansion storage area in the flash memory chip 230 as address mapping information of the flash memory expansion storage area; and provides address mapping information of the flash extended memory area and whether the flash extended memory area is valid information to the main control unit 213.
The main control unit 213 may be configured to determine whether the first read instruction and the corresponding address sent by the system bus 220 are valid according to the address mapping information and the valid information of the extended storage area, and if yes, control the flash memory control unit 214 to read the user data stored in the flash memory extended storage area of the flash memory chip 230; and is further configured to determine whether the first write command issued by the system bus 220 and the corresponding address are valid according to the address mapping information and the valid information of the extended storage area, and if yes, control the flash memory control unit 214 to rewrite the user data stored in the flash memory extended storage area of the flash memory chip 230.
Further, the main control unit 213 may send the first read command and the corresponding address or the first write command and the corresponding address of the system bus 220 to the flash memory control unit 214 through the control path 2.
The flash memory control unit 214 may be configured to read or rewrite the user data stored in the flash memory extended storage area of the flash memory chip 230 according to the control of the main control unit 213. Flash control unit 214 may provide status information of flash memory chips 230 in a flash memory system configuration area in flash memory chips 230 to flash configuration register 212 via data path 2, and further, flash configuration register 212 may provide general program data and user data information in flash memory chips 230 to master control unit 213 via control path 3.
In addition, the system bus 220 may also configure the information of the flash configuration registers 212 via data path 1 (which is the data path between the flash system bus interface 211 to the flash configuration registers 212).
The function of flash memory system bus interface 211, in addition to converting read and write access to system bus 220 to read and write access to flash memory chip 230, may also be used to convert read and write access to system bus 220 to read and write access to flash configuration register 212, distinguishable from an address. When reading from and writing to flash configuration register 212, it is read directly from or written to flash configuration register 212 via data path 1.
On the basis of the above embodiment, the main control unit 213 may include: an operation control unit 2131 and an extended memory address comparing unit 2132.
Wherein, the operation control unit 2131 is used for controlling the flash memory control unit 214 to erase, write or read the flash memory chip 230; specifically, when the flash memory control unit 214 is controlled to perform an erase, write or read operation on the flash memory extended storage area in the flash memory chip 230, the operation needs to be performed only when the extended storage address comparing unit 2132 determines that the current operation is valid.
An extended memory address comparing unit 2132, configured to determine whether the received first read instruction and the corresponding address issued by the system bus or the issued first write instruction and the corresponding address are valid.
That is, the main control unit 213 may obtain an operation to be performed by the system bus 220, such as a read operation or a write operation, from the flash memory system bus interface 211 through the control path 1. Through control path 2, flash control unit 214 is instructed to erase, program, or read instructions, etc. Specifically, if user data in the flash memory expansion memory area in the flash memory chip 230 is read and written, a read and write instruction and an address sent by the system bus 220 are obtained from the control path 1, address mapping information of the flash memory expansion memory area and whether the expansion memory area is valid or not are obtained from the control path 3, and whether the read and write instruction and the address sent by the system bus 220 are valid or not is judged by the expansion memory address comparing unit, if valid, the read and write operation is performed on the flash memory expansion memory area in the flash memory chip 230, if invalid, the operation of the system bus 220 is ignored.
Based on the above embodiment, the flash configuration register 212 may include:
an extended storage enable register 2123 for automatically reading, after power-up, whether flash extended storage area is valid information from the flash system configuration area in the flash chip 230, and providing the information to the main control unit 213; it should be noted that, the read valid information of the flash extended storage area is one of the status information of the flash chip 230 configured by the flash system configuration area in the flash chip 230.
An extended memory mapped address register 2124, configured to map an address corresponding to the first read instruction or an address corresponding to the first write instruction interacted with the flash memory system bus interface 211 into physical address information of the flash memory extended memory area in the flash memory chip 230, and provide the physical address information as address mapped information of the flash memory extended memory area to the main control unit 213.
Correspondingly, the flash memory system bus interface 211 is further configured to directly perform read-write access to the flash memory configuration register 212, and the system bus 220 may configure flash memory register 212 information through the data path 1 between the flash memory system bus interface 211 and the flash memory configuration register 212; the flash system configuration area of flash chip 230 also includes extended memory enable register 2123 and extended memory mapped address register 2124 status information. Upon power up, the status information of the extended memory enable register 2123 and the extended memory mapped address register 2124 may be automatically updated into the extended memory enable register 2123 and the extended memory mapped address register 2124.
Based on the above embodiments, the determining whether the received first read instruction and the corresponding address issued by the system bus 220 or the issued first write instruction and the corresponding address are valid may specifically be:
1. determining whether an address corresponding to the first read command issued by the system bus 220 is within an effective address range set by the flash memory expansion storage area;
2. determining whether the current address is within the address mapping range by comparing the address of the extended memory mapped address register 2124 with the address corresponding to the first read command issued by the system bus 220;
3. it is determined whether the flash extended memory area corresponding to the current address is valid or not by the extended memory enable register 2123.
When the 3 steps are determined to be successful, the operation control unit 2131 issues a corresponding read operation instruction.
Here, taking the example of reading the flash memory expansion area in the flash memory chip 230 as an example, the determination of whether the writing, erasing or programming instruction and the corresponding address are valid is similar to the flash memory expansion area.
Based on the above embodiment, the flash configuration register 212 may further include: a flash key register 2121 and/or a flash operation register 2122. The flash key register 2121 is used for storing a key for accessing the flash system configuration area in the flash memory chip 230, the key is usually pre-configured in the flash key register 2121, and when the data in the flash system configuration area needs to be rewritten, it is necessary to determine whether the key is correct, and the flash key register 2121 can effectively prevent illegal rewriting. The flash memory system configuration area in the flash memory chip 230 is configured by a manufacturer, is not available to a user, is invisible, and prevents illegal overwriting by judging whether the key is correct.
Flash operation registers 2122 may be used to erase, write, or read data from the flash system configuration area in flash chip 230. Specifically, when the manufacturer needs to rewrite the configuration area of the flash memory system in the flash memory chip 230, the manufacturer can issue an erase operation command and a program operation command through the flash operation register 2122 to achieve the purpose of rewriting the configuration area of the flash memory system in the flash memory chip 230.
The embodiment also provides a method for rewriting a configuration area of a flash memory system in a flash memory chip in an embedded system, referring to fig. 2B, where the method specifically includes:
s210, power-on reset is performed, and system state information in a flash memory system configuration area in the flash memory chip is read.
S220, the CPU reads general program data in the flash memory chip through a system bus and controls the system to run. Program data are read from the flash memory chip and provided to the CPU through a program data bus of the system bus, and the embedded system starts to operate normally.
S230, judging whether the main control unit receives a first write instruction and a corresponding address of the system bus, if so, executing S240, and if not, returning to S220. That is, it is determined whether the system configuration needs to be rewritten, and if so, the step of writing the key is entered.
S240, the flash memory key register judges whether the received key is correct, if yes, S250 is executed, and if not, S210 is returned. And executing corresponding operation of erasing the state information of the flash memory chip only if the flash memory key register judges that the received key is correct, otherwise, regarding the received first write instruction of the system bus and the corresponding address as illegal operation.
S250, according to the first write command and the corresponding address of the system bus, erasing and writing state information of the corresponding flash memory chip in a flash memory system configuration area in the flash memory chip. In this case, the system bus writes the values to be updated in the extended storage enable register and the extended storage mapping address register, and the flash memory operation register rewrites the status information of the flash memory chip in the flash memory system configuration area through the data path 2 according to the first write command and the corresponding address of the system bus.
On the basis of the technical scheme, the method can further comprise the following steps: and the flash memory operation register updates the state information of the flash memory chip in the current flash memory system configuration area into the flash memory configuration register according to the first reading instruction written in by the system bus. Further, reading the current state information of the flash memory chip through a system bus, and comparing the current state information with the first write instruction; and determining the system configuration state of the current flash memory system configuration area according to the comparison result. Specifically, if the current state information of the flash memory chip is consistent with the first write instruction, the state information of the flash memory chip is determined to be correct, otherwise, the state information of the flash memory chip is determined to be incorrect, and the flash memory chip can be directly discarded or reconfigured according to the requirement.
By adopting the technical scheme, the expansion memory enabling register, the expansion memory mapping address register and the expansion memory address comparing unit are added, so that the requirements of users who need to store key secret information are met, the users can develop conveniently, the memory space of the users is expanded, the privacy and the independence of the user data are protected, and the safety of the data of the flash memory chip is effectively protected.
Example III
Fig. 3 is a schematic structural diagram of an embedded system according to a second embodiment of the present invention, as shown in fig. 3, where the technical solution of this embodiment is further optimized based on the foregoing embodiment, and compared with the foregoing embodiment, the system further includes:
a Static Random Access Memory (SRAM) 310 for storing general program data and user data in the flash memory chip 320 after power-up. The embedded system can directly read from the flash memory chip 320 by reading operation of the flash memory chip 320, and preferably can read through the SRAM 310 due to the slower reading speed of the flash memory chip 320, so that the real-time reading of the general program data and the user data in the flash memory chip 320 can be realized, and the reading speed of the general program data and the user data in the flash memory chip 320 is improved.
In order to better satisfy the fast reading of general program data and user data in the flash memory chip 320, and considering the SRAM area and the occupied address space, the SRAM310 may include a main SRAM and an auxiliary SRAM, and the address space of the main SRAM generally cannot be too large, for example, may be several tens of kilobytes, and in a specific operation, the auxiliary SRAM may be used when the address space of the main SRAM is insufficient.
The flash controller 330 further includes: the SRAM control unit 331 is connected to the flash memory system bus interface 332, the main control unit 333, the flash memory control unit 334, and the SRAM310, respectively.
The main control unit 333 is further configured to determine whether the first read instruction and the corresponding address sent by the system bus 340 are valid according to the address mapping information and the valid information of the flash memory extended storage area, and if yes, control the SRAM control unit 331 to read the user data stored in the SRAM 310; and the method is further used for judging whether the first write command and the corresponding address sent by the system bus 340 are valid or not according to the address mapping information and the valid information of the flash memory expansion storage area, if yes, the SRAM control unit 331 is controlled to rewrite the user data stored in the SRAM310, or the flash memory control unit 334 is controlled to rewrite the user data stored in the flash memory chip 320.
Based on the above embodiment, the system bus 340 may further issue an instruction and a corresponding address for rewriting the general program data stored in the flash memory main storage area of the flash memory chip 320, and the flash memory control unit 334 interacts the instruction and the corresponding address with the flash memory system bus interface 332 through the data path 5, so as to rewrite the general program data stored in the flash memory main storage area of the flash memory chip 320.
In this embodiment, the specific structure and function of the flash configuration register 335 are the same as those of the above embodiment.
The main control unit 333 receives the first read command and the corresponding address sent by the system bus 340 through the control channel 1, and determines whether the first read command and the corresponding address sent by the system bus 340 are valid according to the address mapping information and the extended memory area valid information provided by the flash configuration register 335, preferably, the data in the flash memory chip 320 is read by the SRAM 310. If the target data to be read by the main control unit 333 is stored in the SRAM 310 after the embedded system is powered on, the target data is directly read from the SRAM 310 and sent to the system bus 340 through the data path 1; if the target data is not stored in the SRAM 310, the target data may be read from the flash memory chip 320 into the SRAM 310 and then read from the SRAM 310.
Specifically, the user data stored in the SRAM 310 may read the general program data and the user data in the flash memory chip 320 into the SRAM 310 through the data path 4 between the flash memory control unit and the SRAM control unit, and after the embedded system is powered on, the SRAM 310 may automatically read and store the general program data in the flash memory main memory area or the user data in the flash memory expansion memory area in the flash memory chip 320.
The SRAM control unit 331 is configured to read or rewrite user data stored in the SRAM 310 according to control of the main control unit 333. The SRAM control unit 331 may translate the received first read instruction and corresponding address of the main control unit 333 via the control path 4 into the first read instruction and corresponding address of the SRAM 310, and may translate the received first write instruction and corresponding address of the main control unit 333 into the first write instruction and corresponding address of the SRAM 310.
In the above embodiment, the main control unit 333 may read the general program data and the user data in the flash memory chip 320 through the main SRAM 310, for example, the main SRAM may specifically copy the general program data that needs to be responded in real time in the flash memory main storage area in the flash memory chip 320 1:1, and provide the general program data to the flash memory system bus interface 332 through the data path 4, that is, the part of the data system bus may be directly read from the main SRAM, and the reading speed is the fastest for real-time reading without waiting period; the general program data and the user data in the flash memory chip 320 may also be read through the auxiliary SRAM, if the auxiliary SRAM has corresponding target data, the data may be directly read from the auxiliary SRAM, if the auxiliary SRAM has no corresponding data, the data to be read may be read from the flash memory chip 320 into the auxiliary SRAM, and the auxiliary SRAM provides the data to the flash memory system bus interface 332 through the data path 3. That is, through the operation mode similar to the cache, if the auxiliary SRAM has corresponding data (similar to the cache hit), the data is directly read from the auxiliary SRAM, if the auxiliary SRAM has no corresponding data (similar to the cache miss), the data to be read is firstly read from the flash memory chip into the auxiliary SRAM, and then the system bus is read from the auxiliary SRAM.
Auxiliary SRAMs typically store large amounts of data that is not often altered. The requirement on the reading speed is not high, and a certain waiting period is generally reserved for reading. In this case, the flash memory expansion area is relatively small (e.g., 1K bytes), and 1:1 copying can be performed by the main SRAM, so that the flash memory expansion area can be read in real time, but the area of the SRAM is increased. The method of reading can be consistent with the method described above by assisting the SRAM reading, so that the reading can increase some waiting period, but the SRAM area is not increased.
In summary, the above technical solution reads the general program data and the user data in the flash memory chip 320 through the SRAM 310, so that the speed of the embedded system for reading the general program data and the user data in the flash memory chip 320 is effectively increased, and real-time reading is realized, thereby greatly improving the user experience.
Example IV
The embodiment of the invention provides two embedded systems, and based on the above embodiments, multi-user storage is realized.
Mode one
Fig. 4A is a schematic structural diagram of a flash memory expansion storage area according to a fourth embodiment of the present invention, as shown in fig. 4A, where the technical solution of this embodiment is further optimized based on the above embodiment, and compared with the above embodiment, the difference is that, preferably, the flash memory expansion storage area 410 includes at least one flash memory expansion storage block 411. The size of the flash memory expansion block 411 may be set according to actual requirements, which is not limited herein. For example, the flash extended memory area 410 is 128 kbytes in total, divided into 32 extended memory blocks 411, each block being 4 kbytes in size.
Correspondingly, the extended storage enable register is configured to automatically read whether any one or any plurality of flash extended storage blocks 411 are valid information from the flash system configuration area in the flash chip after power-up, and provide the valid information to the main control unit. By adopting the technical scheme, the flash memory expansion storage area 410 can be divided into a plurality of flash memory expansion storage blocks 411, so that whether each flash memory expansion storage block 411 is effective or not can be configured, thus being capable of being configured for a plurality of users, and the flash memory expansion storage blocks 411 of each user are isolated in physical storage. Moreover, any one or more flash memory expansion storage blocks 411 can be flexibly configured to be effective so as to meet the requirements of different users on the size of the expansion storage blocks 411.
For example, assume that the flash extended memory area 410 has 32 flash extended memory blocks 411, each flash extended memory block 411 having 4Kbytes (bytes), taking up 128 Kbytes of space; the extended memory enable register is 32bits, and each bit controls whether 1 flash extended memory block 411 is valid. The existing 6 users respectively need expansion storage areas with the sizes of 4KB, 8KB, 16KB, 32KB and 64KB, and then the expansion storage enabling registers can be respectively configured to be 32'h1 (the lowest bit is 1, the other is 0), 32' h2, 32'hC, 32' hF0, 32'hFF00 and 32' hFFFF_0000. All other general standard users, except the above 6 users, have no extended storage area, and are configured to be 32' h0 (all bits are 0). Thus, the 6 users can use different flash memory expansion storage blocks 411, so that the data stored in the flash memory expansion storage area 410 by the 6 users are isolated from each other, and the confidentiality effect is achieved.
Mode two
In the first embodiment, since the same physical space needs to be added to the flash chip for each flash expansion memory block 411, in order to make the flash expansion memory area 410 meet the data storage requirement of more users, the expansion memory mapped address register is preferably further configured to map a plurality of different addresses corresponding to the first read instruction or addresses corresponding to the first write instruction, which interact with the flash system bus interface, into the same physical address information of the flash expansion memory area 410 in the flash chip, and provide the same as the address mapped information of the flash expansion memory area to the host unit.
The address mapping information of the flash memory expansion storage area is generally used as logic address information of the same physical address information of the flash memory expansion storage area 410, so that a user can realize read-write access to the flash memory expansion storage area 410 through a system bus.
For example, assuming that the first user needs 4K expansion memory area corresponding to the first flash expansion memory block, the expansion memory enable register is 32' h1, the configurable expansion memory map address register is 0, if the logical address range of the total 4K bytes, the mapped system bus addresses are 32' h00c0_0000 to 32' h00c0_0fff; the second user also uses the first flash extended memory block, the extended memory enable register is still 32' h1, and the extended memory mapped address register is configured to be 1, and the mapped system bus addresses are 32' h00c2_0000 to 32' h00c2_0fff. Therefore, as the logical addresses of two users accessing the flash memory expansion storage area are different, the effects of data isolation and mutual confidentiality can be achieved.
According to the technical scheme, the physical address information of the same flash memory control speed is mapped into a plurality of different logic address information of the system bus by adopting the extended memory mapping address register, and as users usually only need to use the logic address information of the system bus in actual operation, the same flash memory extended memory block can be configured for different users, so that the data storage requirement of more users can be met, and the limited physical space of a flash memory chip is better configured for more users to store data.
In order to better meet the requirements of users on the flash memory chip, the space is reasonably allocated, and preferably, the storage space of the flash memory expansion storage area is smaller than that of the flash memory main storage area.
By adopting the embedded system provided by the technical scheme, even if the flash memory chip A storing the data information of the user A is cracked by the user B, the user B can only read the general program data of the flash memory main storage area in the flash memory chip A, and the physical address or the logical address used by the flash memory expansion storage area of the chip of the user A is different from the physical address and/or the logical address used by the expansion storage area of the user B, so that the general program data of the flash memory main storage area in the flash memory chip A cannot be used on the flash memory chip B of the user B, the privacy and the independence of the data storage of each user are fully protected, and the safety is greatly improved.
Fig. 4B is a flowchart of a method for reading and writing an extended flash memory area of an embedded system according to the present embodiment, where the method includes:
s410, power-on reset is performed, and system state information in a flash memory system configuration area in the flash memory chip is read. Specifically, after power-on reset, the information of the extended storage enabling register and the information of the extended storage mapping address register stored in the flash memory system configuration area in the flash memory chip can be automatically updated to the extended storage enabling register and the extended storage mapping address register.
S420, the CPU reads general program data in the flash memory chip through a system bus and controls the system to run.
S430, judging whether the instruction of the system bus is to read and write a flash memory expansion storage area in a flash memory chip, if so, executing S440; if not, return to S420.
S440, the main control unit executes corresponding operation according to the instruction of the system bus.
S450, if the system bus instruction is a first read instruction and a corresponding address, the main control unit judges whether the first read instruction and the corresponding address sent by the system bus are valid or not according to the address mapping information and the valid information of the extended storage area, if yes, S470 is executed, and if not, S420 is returned.
S460, if the system bus command is a first write command and a corresponding address, the main control unit configures the flash memory controller according to the system state information of the flash memory system configuration area in the flash memory chip, and S480 is executed.
S470, the CPU reads the corresponding data of the flash memory expansion storage area through the flash memory control unit.
S480, the main control unit judges whether a first write instruction sent by a system bus and a corresponding address are valid or not according to the address mapping information and the valid information of the extended storage area, if so, S490 is executed; if not, return to S420.
In S450 and S480, the main control unit may determine, through the extended memory address comparing unit, whether the first read command and the corresponding address or the first write command and the corresponding address issued by the system bus are valid addresses of the flash memory extended memory area.
For example, assume that the extended memory enable register 2123 is 32bits, there are a total of 32 extended memory blocks, 4KBytes per block, and the variable is set to ext_en [31:0] (from 0-31, a total of 32 configurations). The extended memory mapped address register 2124 may map the physical address of each extended memory block to 32 different logical addresses, and the variable is set to ext_ad [4:0], where a logical address range of 32× KBx32 =4096 KB is required, and the logical address range of the flash extended memory area may be set to 32'h00c0_0000 to 32' h00ff_ffff, where the mapping range of each logical address is 4096/32=128 KB, and each 128KB is divided into 32 extended memory blocks. Each flash extension storage block is 128 KB/32=4kb. At this time, the system bus issues a read command, and the read address is addr. At this time, it is necessary to determine whether the current address is an effective address of the flash memory extended storage area by the extended storage address comparing unit, which includes the steps of:
Addr < = 32'h00ff_ffff and addr > = 32' h00c0_0000;
2.addr[21:17]＝＝ext_ad[4:0]；
ext_en [ addr [16:12] ] is 1.
When all 3 judging conditions are met, the current address is the effective address of the extended storage area.
S490, the CPU erases the flash memory expansion storage area through an operation control unit in the main control unit.
By adopting the technical scheme, the requirement of private storage of multiple users can be met, and the safety of data is fully ensured by judging the validity of the address when the flash memory is read and written in the extended storage area.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (9)
1. An embedded system, comprising: the device comprises a flash memory controller, a Central Processing Unit (CPU) and a flash memory chip, wherein the flash memory controller is respectively connected with the CPU and the flash memory chip; wherein,
the flash memory chip includes:
a flash memory main storage area for storing general program data;
a flash memory system configuration area for configuring state information of the flash memory chip;
the flash memory chip further includes:
a flash memory extended storage area for storing specific user data;
the flash memory controller is used for interacting the state information of the flash memory chip with the flash memory system configuration area, reading the user data from the flash memory expansion storage area according to the state information of the flash memory chip, and executing by the CPU or rewriting the user data stored in the flash memory expansion storage area; the method is also used for performing read-write access on the flash memory main storage area;
the embedded system comprises a flash memory controller, a CPU, a memory controller and a control circuit, wherein the flash memory controller and the CPU are configured on a main chip of the embedded system, and the main chip and the flash memory chip are manufactured in the same package by adopting an MCP technology to form the embedded system;
the flash memory controller includes:
A flash memory system bus interface;
a flash memory configuration register connected with the flash memory system bus interface;
the main control unit is respectively connected with the flash memory system bus interface and the flash memory configuration register;
the flash memory configuration register is configured to automatically read status information of the flash memory chip in the flash memory system configuration area after the embedded system is powered on, where the status information of the flash memory chip includes: whether the flash memory expansion storage area is valid or not; mapping an address corresponding to the first read instruction or an address corresponding to the first write instruction interacted with the flash memory system bus interface into physical address information of the flash memory expansion storage area in the flash memory chip, and taking the physical address information as address mapping information of the flash memory expansion storage area; and providing address mapping information of the flash memory expansion storage area and whether the flash memory expansion storage area is effective or not to the main control unit.
2. The system of claim 1, wherein the flash memory controller further comprises:
the flash memory control unit is respectively connected with the flash memory configuration register, the main control unit and the flash memory chip;
the flash memory system bus interface is configured to send a first read instruction and a corresponding address sent by a system bus to the main control unit, where the first read instruction is used to perform read access on the flash memory extended storage area; the system is also used for sending a first write instruction and a corresponding address sent by the system bus to the main control unit, wherein the first write instruction is used for performing write access on the flash memory expansion storage area;
The main control unit is used for judging whether a first reading instruction sent by a system bus and a corresponding address are valid or not according to the address mapping information and the valid information of the flash memory expansion storage area, and if yes, the flash memory control unit is controlled to read user data stored in the flash memory expansion storage area of the flash memory chip; the flash memory control unit is further used for judging whether a first write instruction sent by the system bus and a corresponding address are valid or not according to the address mapping information and the valid information of the flash memory expansion storage area, and if yes, the flash memory control unit is controlled to rewrite user data stored in the flash memory expansion storage area of the flash memory chip;
and the flash memory control unit is used for reading or rewriting the user data stored in the flash memory expansion storage area in the flash memory chip according to the control of the main control unit.
3. The system of claim 2, wherein the flash configuration register comprises:
an extended storage enabling register, configured to automatically read, after power-up, whether an extended storage area is valid or not from the flash memory system configuration area in the flash memory chip, and provide the valid information to the main control unit;
An extended memory mapped address register, configured to map an address corresponding to the first read instruction or an address corresponding to the first write instruction interacted with the flash memory system bus interface into physical address information of the flash memory extended memory area in the flash memory chip, and provide the physical address information as address mapped information of the flash memory extended memory area to the main control unit;
correspondingly, the flash memory system bus interface is also used for directly performing read-write access on the flash memory configuration register.
4. The system of claim 3, wherein the flash configuration register further comprises: a flash key register and/or a flash operation register;
the flash memory key register is used for storing a key for accessing the flash memory system configuration area in the flash memory chip;
the flash memory operation register is used for erasing, writing or reading the data of the flash memory system configuration area in the flash memory chip.
5. The system of any one of claims 2-4, wherein the master control unit comprises:
an operation control unit, configured to control the flash memory control unit to perform an erase, write or read operation on the flash memory chip;
And the extended storage address comparison unit is used for judging whether the received first read instruction and the corresponding address sent by the system bus or the sent first write instruction and the corresponding address are valid or not.
6. The system of claim 2, wherein the system further comprises: the static random access memory SRAM is used for storing general program data and user data in the flash memory chip after power-on;
the flash memory controller further includes: the SRAM control unit is respectively connected with the flash memory system bus interface, the main control unit, the flash memory control unit and the SRAM;
the main control unit is further configured to determine whether a first read instruction and a corresponding address sent by a system bus are valid according to the address mapping information and the valid information of the extended storage area, and if yes, control the SRAM control unit to read user data stored in the SRAM; the memory controller is also used for judging whether a first write instruction sent by a system bus and a corresponding address are valid or not according to the address mapping information and the valid information of the extended memory area, and if so, controlling the SRAM control unit to rewrite user data stored in the SRAM or controlling the flash memory control unit to rewrite the user data stored in the flash memory chip;
The SRAM control unit is used for reading the user data stored in the SRAM according to the control of the main control unit.
7. The system according to claim 5, wherein: the flash memory expansion storage area comprises at least one flash memory expansion storage block;
correspondingly, the extended storage enabling register is used for automatically reading whether any one or a plurality of flash memory extended storage blocks are effective information from the flash memory system configuration area in the flash memory chip after power-on, and providing the effective information to the main control unit.
8. The system according to claim 7, wherein: the extended memory mapped address register is further configured to map a plurality of different addresses corresponding to the first read instruction or addresses corresponding to the first write instruction, which interact with the flash memory system bus interface, to the same physical address information of the flash memory extended memory area in the flash memory chip, and provide the same physical address information as the address mapping information of the flash memory extended memory area to the main control unit.
9. The system according to claim 1, wherein: the storage space of the flash memory expansion storage area is smaller than that of the flash memory main storage area.
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