CN106920851A - A kind of non-volatile programmable pn-junction memory - Google Patents
A kind of non-volatile programmable pn-junction memory Download PDFInfo
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- CN106920851A CN106920851A CN201710141635.7A CN201710141635A CN106920851A CN 106920851 A CN106920851 A CN 106920851A CN 201710141635 A CN201710141635 A CN 201710141635A CN 106920851 A CN106920851 A CN 106920851A
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- 230000015654 memory Effects 0.000 title abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 17
- 230000005684 electric field Effects 0.000 claims abstract description 5
- 239000000203 mixture Substances 0.000 claims abstract description 3
- 239000013078 crystal Substances 0.000 claims description 4
- 230000006870 function Effects 0.000 abstract description 13
- 230000005693 optoelectronics Effects 0.000 abstract description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- 230000000704 physical effect Effects 0.000 abstract description 2
- 229910003090 WSe2 Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000006386 memory function Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention discloses the non-volatile programmable pn-junction memory of one kind.The device is based primarily upon the physical characteristic of bipolar semiconductor material, by the structure design of half floating gate fet, realize effective modulation of the control gate to channel layer, allow channel layer logical conversion between the pn-junction storage state different from non-pn-junction etc., with the storable function of Nonvolatile programmable.Because pn-junction has different physical properties from non-pn-junction, thus new application can be produced in electronics and opto-electronic device, expand the function and application field of conventional semiconductors pn-junction and floating-gate memory.The device primary structure and function are as follows：(1) with the device configuration of half floating gate fet；(2) material of composition channel layer is mainly bipolar semiconductor material, and the carrier type (p-type or N-shaped) of the material can carry out dynamic regulation by electric field；(4) be half FGS floating gate structure, i.e. floating boom covering part channel layer.
Description
Technical field
The present invention relates to the use of semiconductor technology and prepare the device junction with Nonvolatile programmable pn-junction memory function
Structure.
Background technology
Floating-gate memory has a wide range of applications field.In traditional floating-gate memory, main utilization is applied to control
Pulse voltage control channel layer on grid changes between different resistance memory states, and can not be in other storage states, such as
Change between pn-junction and non-pn-junction.This is mainly due to for traditional semi-conducting material, such as silicon, their current-carrying subclass
Type (p-type or N-shaped) is main to be produced by doping, once after being formed, just cannot dynamically realize semi-conducting material in different electric charges
Change between type.That is, for the channel layer of N-shaped, control gate can only regulate and control channel layer has different resistance, but
Principal carrier is still electronics (N-shaped)；It is also the same for the channel layer of p-type.Additionally, for these reasons, for passing
The semi-conducting material of system, even with half floating gate fet structure, channel layer also can be only in different resistive memories
State.
The content of the invention
It was found by the inventors of the present invention that some nano materials, such as WSe2Two dimensional crystal, black phosphorus etc., their current-carrying subclass
Type can be by Electric Field Modulated, and (we define this material for bipolar semiconductor material to dynamic change between p-type and N-shaped
Material).This provides possibility for design prepares new device structure.For example using this property, people can be dynamic for preparing
The pn-junction structure of modulation, the present invention further discloses the pn-junction structure has storage performance.
The present invention needs the technical scheme to be protected to be：
The present invention provides a kind of with the storable pn-junction structure of Nonvolatile programmable, it is used for non-volatile volume
The aspects such as journey pn-junction memory.The present invention is based on half floating gate fet structure of ambipolar two dimensional crystal by design,
Realize becoming device in the storage of the different conditions such as pn-junction and non-pn-junction and logic using applying pulse voltage on the control gate
Change.
Further public technology scheme, a kind of device architecture with Nonvolatile programmable pn-junction memory function, its
It is characterised by, the structure of design is followed successively by,
Including electrode 1；
Including channel layer 2, positioned at the lower floor of electrode 1, and bipolar semiconductor material is used；
Including about two two dielectric layers (3,5)；
Including half floating boom 4, between described two dielectric layers (3,5), and the area of half floating boom 4 is less than the channel layer
2 areas；Half floating boom 4 by one and half floating booms (Fig. 1) or can extend to multiple half floating booms and constitute；
Including control gate 6, positioned at the lower floor of the dielectric layer 5.
The channel layer can be modulated for bipolar semiconductor, i.e. its carrier type by extra electric field.
The device can carry out logic change between pn-junction and non-pn-junction, and with it is non-volatile can store function.
Different pulse voltages are input into by the control gate 6, acquisition different type electric charge is in half floating boom 4
Storage, so as to modulate the channel layer 2 change between pn-junction and non-pn-junction.Storage due to half floating boom 4 to electric charge, Ke Yishi
The existing channel layer 2 the different conditions such as pn-junction and non-pn-junction storage, so as to have non-volatile storability energy.By defeated
Enter different pulse voltages, it is possible to achieve logic transition of the channel layer 2 between different conditions, so that programmable
Energy.
The device architecture and function of the proposition Nonvolatile programmable pn-junction memory of the invention.Due to material
Can limit, traditional floating-gate memory can only realize storage and logic change of the channel layer between different resistance states, it is impossible to
Realize that channel layer changes in the storage of the different conditions such as pn-junction and non-pn-junction and logic.Due to pn-junction and non-pn-junction have it is different
Electricity and photoelectronics performance, the device architecture of present invention design thus can produce many new applications.
A kind of new device architecture of the invention, is expected to expand the function and application field of traditional pn-junction, in electricity
New application is produced in son and opto-electronic device.
Brief description of the drawings
Fig. 1 is device architecture schematic diagram of the present invention.
Fig. 2 is the device architecture schematic diagram for extending.
Fig. 3 be embodiment in different storage states, a is pn-junction, and b is non-pn (n+N) tie.
Fig. 4 is demonstrated for the device non-volatile memories application of function of embodiment.
Fig. 5 is demonstrated for the programmable functions application of embodiment.
Numeral mark：
1 electrode
2 channel layers:Using bipolar semiconductor material
3 dielectric layers one
4 half floating booms one
5 dielectric layers 2
6 control gates
7 half floating booms two
Specific embodiment
The invention discloses it is a kind of with Nonvolatile programmable can store function new pn-junction device architecture.The device
The physical characteristic of bipolar semiconductor material is based primarily upon, by the structure design of half floating gate fet, control is realized
Effective modulation of the grid to channel layer, allows channel layer logical conversion between the pn-junction storage state different from non-pn-junction etc.,
With the storable function of Nonvolatile programmable.Because pn-junction and non-pn-junction have a different physical properties, thus can be
New application is produced in electronics and opto-electronic device, conventional semiconductors pn-junction is expanded and is led with the function and application of floating-gate memory
Domain.The device primary structure and function are as follows：(1) with the device configuration of half floating gate fet；(2) channel layer is constituted
Material be mainly bipolar semiconductor material, the carrier type (p-type or N-shaped) of the material can enter Mobile state by electric field
Regulation and control；(4) be half FGS floating gate structure, i.e. floating boom covering part channel layer；(5) by this structure design, it is possible to achieve raceway groove
Logic change of the layer between pn-junction and non-pn-junction, and the pn-junction storage state different from non-pn-junction etc. is may be at, have
Non-volatile and programmability feature.
Technical solution of the present invention is described further below in conjunction with accompanying drawing.
The structure of device of the present invention is as shown in Figure 1 and Figure 2：
Including electrode 1；
It is bipolar semiconductor material including channel layer 2；
Including two dielectric layers (3,5)；
Be that half FGS floating gate structure, i.e. floating boom do not cover whole channel layer including floating boom 4, can by one and half floating booms (Fig. 1) or
Extend to multiple half floating boom (Fig. 2) compositions；
Including control gate 6.
Different pulse voltages are input into by the control gate 6, obtain the channel layer 2 in pn-junction or non-pn-junction etc. no
With storage state, it is possible to change between pn-junction and non-pn-junction so that the channel layer has non-volatile the storage can
The function of programming.
The present invention is described further by example further below.
Embodiment
Based on bipolar semiconductor material WSe2Nonvolatile programmable pn-junction memory.
The device is gold using the device architecture shown in Fig. 1, wherein electrode 1, and channel layer 2 is bipolar semiconductor WSe2Two
Dimension crystal, dielectric layer 3 is boron nitride, and half floating boom 4 is Graphene, and dielectric layer 5 is SiO2, control gate 6 is silicon.
Fig. 3, it is shown that when different positive pulse voltages are applied, channel layer is in pn-junction state, tool
There is rectification characteristic；When different negative pulse voltages are applied, channel layer is in non-pn (n+N) state is tied, with opposite
Rectification characteristic.
As shown in figure 4, channel layer can store the state with non-pn-junction in pn-junction, with non-volatile.
As shown in figure 5, channel layer logic can change between different states, thus with programmable feature.
Claims (5)
1. it is a kind of that there is the storable pn-junction structure of Nonvolatile programmable, it is characterised in that to be based on ambipolar two by design
Tie up half floating gate fet structure of crystal, realize using apply pulse voltage on the control gate to device pn-junction with
The storage of the different conditions such as non-pn-junction and logic change.
2. device architecture as claimed in claim 1, it is characterised in that the structure of design is followed successively by,
Including electrode (1)；
Including channel layer (2), positioned at the lower floor of electrode (1), and bipolar semiconductor material is used；
Including about two two dielectric layers (3,5)；
Including half floating boom (4), between described two dielectric layers (3,5), and the area of half floating boom 4 is less than the channel layer
(2) area；
Including control gate (6), positioned at the dielectric layer (5) lower floor.
3. device architecture as claimed in claim 1, it is characterised in that half floating boom (4) by one and half floating booms or can be extended to
Multiple half floating boom compositions.
4. device architecture as claimed in claim 1, it is characterised in that the channel layer is bipolar semiconductor, i.e. its current-carrying
Subtype can be modulated by extra electric field.
5. device architecture as claimed in claim 1, it is characterised in that the device can be carried out between pn-junction and non-pn-junction
Logic change, and with it is non-volatile can store function.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710141635.7A CN106920851B (en) | 2017-03-10 | 2017-03-10 | A kind of non-volatile programmable pn-junction memory |
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| CN201710141635.7A CN106920851B (en) | 2017-03-10 | 2017-03-10 | A kind of non-volatile programmable pn-junction memory |
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| Publication Number | Publication Date |
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| CN106920851A true CN106920851A (en) | 2017-07-04 |
| CN106920851B CN106920851B (en) | 2019-12-03 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109801921A (en) * | 2019-01-16 | 2019-05-24 | 复旦大学 | A kind of non-volatile charge trap memory of double grid and preparation method thereof |
| CN113594167A (en) * | 2021-07-29 | 2021-11-02 | 上海集成电路制造创新中心有限公司 | Non-volatile programmable heterojunction memory |
| CN114005883A (en) * | 2021-10-19 | 2022-02-01 | 北京纳米能源与系统研究所 | Semi-floating gate transistor, artificial synapse and synapse weight control method |
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| CN103579119A (en) * | 2012-07-27 | 2014-02-12 | 上海华虹Nec电子有限公司 | Manufacturing method of EEPROM memory cell |
| JP2016151558A (en) * | 2015-02-19 | 2016-08-22 | 富士通株式会社 | Gas sensor |
| CN106409886A (en) * | 2016-11-10 | 2017-02-15 | 同济大学 | Logic application method for bipolar semiconductor photoelectronic device |
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2017
- 2017-03-10 CN CN201710141635.7A patent/CN106920851B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103579119A (en) * | 2012-07-27 | 2014-02-12 | 上海华虹Nec电子有限公司 | Manufacturing method of EEPROM memory cell |
| JP2016151558A (en) * | 2015-02-19 | 2016-08-22 | 富士通株式会社 | Gas sensor |
| CN106409886A (en) * | 2016-11-10 | 2017-02-15 | 同济大学 | Logic application method for bipolar semiconductor photoelectronic device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109801921A (en) * | 2019-01-16 | 2019-05-24 | 复旦大学 | A kind of non-volatile charge trap memory of double grid and preparation method thereof |
| CN113594167A (en) * | 2021-07-29 | 2021-11-02 | 上海集成电路制造创新中心有限公司 | Non-volatile programmable heterojunction memory |
| WO2023005563A1 (en) * | 2021-07-29 | 2023-02-02 | 上海集成电路制造创新中心有限公司 | Non-volatile programmable heterojunction memory |
| CN113594167B (en) * | 2021-07-29 | 2024-03-12 | 上海集成电路制造创新中心有限公司 | Nonvolatile programmable heterojunction memory |
| CN114005883A (en) * | 2021-10-19 | 2022-02-01 | 北京纳米能源与系统研究所 | Semi-floating gate transistor, artificial synapse and synapse weight control method |
| CN114005883B (en) * | 2021-10-19 | 2024-04-30 | 北京纳米能源与系统研究所 | Semi-floating gate transistor, artificial synapse and synapse weight control method |
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| CN106920851B (en) | 2019-12-03 |
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