CN106910714A - A kind of semiconductor devices and preparation method thereof and electronic installation - Google Patents
A kind of semiconductor devices and preparation method thereof and electronic installation Download PDFInfo
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- CN106910714A CN106910714A CN201510976485.2A CN201510976485A CN106910714A CN 106910714 A CN106910714 A CN 106910714A CN 201510976485 A CN201510976485 A CN 201510976485A CN 106910714 A CN106910714 A CN 106910714A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Abstract
The present invention relates to a kind of semiconductor devices and preparation method thereof and electronic installation.Methods described includes step S1：Semiconductor substrate is provided, NMOS area and PMOS area are formed with the semiconductor substrate, wherein, the interlayer dielectric layer in gap between the NMOS area and the PMOS area are respectively formed on dummy gate and fill the dummy gate, the hard mask layer of patterning is formed with the PMOS area, to expose the dummy gate in the NMOS area；Step S2：The dummy gate exposed in the NMOS area is removed, is virtually open with forming NMOS；Step S3：From HBr, NF3Combination or H with Ar2Combination with Ar carries out overetch, to remove the dummy gate completely, and the residue on the virtual opening sidewalls is processed from Ar after the overetch；Step S4：Repeating said steps S3 at least 4 times；Step S5：Remove the residue on the virtual opening sidewalls.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to a kind of semiconductor devices and its making
Method and electronic installation.
Background technology
With developing rapidly for microelectric technique, the core of microelectric technique -- CMOS is partly led
Body (CMOS) technology has become the support technology of modern electronic product.In semiconductor fabrication process,
Various materials can be used as the gate electrode and gate-dielectric of complementary mos device,
Traditional complementary mos device generally by silicon oxynitride (SiON) as gate dielectric layer,
Using the polysilicon of doping as gate material.But, with constantly entering for integrated circuit fabrication process
Step, the continuous improvement of chip integration, the reduction of technology node is advanced in the trend that size changes
Complementary mos device more and more using metal gate material replace traditional polycrystalline
Silicon materials, high-k dielectric replaces oxide layer materials, i.e., using high-k dielectric/metal gates (HK/MG)
Structure replaces gate oxide/virtual polysilicon gate construction, with avoid by virtual polysilicon gate cause it is many
The problems such as crystal silicon depletion effect, the diffusion of doping boron atom and electric leakage of the grid higher.
The manufacture method of high-k dielectric/metal gates common at present includes grid at rear (gate-last)
Technique, wherein, grid removal of virtual polysilicon gate in rear technique is one of crucial step.Mesh
There is a problem of in the technique of preceding removal dummy gate a lot：1) dummy gate is removed in dry etching
During can produce polymer and/or by-product deposition on the side wall of the dummy gate opening so that
Cause the worse borderless contacts of NMOS and PMOS.Therefore, for the performance of retainer member, it is necessary to apply
Plus bigger voltage, more serious situation is, if NMOS the and PMOS borders are opened, will to cause
Component failure.2) during the dummy gate is removed, the loss of interlayer dielectric layer turns into one mainly
Parameter, dry etching and wet etching can consume interlayer dielectric layer, wherein, a large amount of interlayer dielectric layers
Consumption can cause metal residue, the process window of influence CMP.
In the prior art by the method using hard mask layer, to obtain more preferable line end profile and CD
LWR, but the enough overetch of hard mask must be kept in this process, to prevent the residual of dummy gate
Stay, but excessive overetch can cause to the damage of PMOS device and more interlayer dielectric layers
Loss, the loss of interlayer dielectric layer can also cause the short circuit of NMOS and PMOS.
Accordingly, it would be desirable to the preparation method of the current semiconductor devices is improved, to solve existing skill
Problem present in art.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be in specific embodiment party
Further described in formula part.Summary of the invention is not meant to attempt to limit
Go out the key feature and essential features of technical scheme required for protection, do not mean that more and attempt really
The protection domain of fixed technical scheme required for protection.
The present invention is in order to overcome the problem of presently, there are, there is provided a kind of preparation method of semiconductor devices, including：
Step S1：There is provided Semiconductor substrate, be formed with the semiconductor substrate NMOS area and
PMOS area, wherein, it has been respectively formed on virtual grid in the NMOS area and the PMOS area
The interlayer dielectric layer in gap, forms in the PMOS area between pole and the filling dummy gate
There is the hard mask layer of patterning, to expose the dummy gate in the NMOS area；
Step S2：The dummy gate exposed in the NMOS area is removed, to form NMOS
Virtual opening；
Step S3：From HBr, NF3Combination or H with Ar2Combination with Ar carries out overetch,
To remove the dummy gate completely, and Ar is selected after the overetch to the virtual opening sidewalls
On residue processed；
Step S4：Repeating said steps S3 at least 4 times；
Step S5：Remove the residue on the virtual opening sidewalls.
Alternatively, the step S1 includes：
Step S11：There is provided Semiconductor substrate, be formed with the semiconductor substrate NMOS area and
PMOS area, the NMOS area and the PMOS area be respectively formed on the dummy gate with
And fill the interlayer dielectric layer in gap between the dummy gate；
Step S12：Deposition forms SiO on the interlayer dielectric layer and the dummy gate2Layer,
To cover the top surface of the interlayer dielectric layer and the dummy gate；
Step S13：The dummy gate in the PMOS area is removed, it is virtual to form PMOS
Opening；
Step S14：Virtually it is open in the PMOS and neutralizes the SiO2Deposition forms work function gold on layer
Category layer, is virtually open with filling up the PMOS；
Step S15：Flatening process is performed, until exposing the interlayer dielectric layer；
Step S16：The hard mask layer of patterning is formed in the PMOS area.
Alternatively, in the step S3, described HBr, Ar and H2Gas flow be 100~800
Sccm, the NF3Gas flow be 10~50sccm.
Alternatively, methods described also includes step S6：Perform etching aftertreatment technology.
Alternatively, the etching aftertreatment technology selects CF4And Ar.
Alternatively, N is selected in the step S52Remove the residue.
Alternatively, repeating said steps S34-5 times in the step S4.
Alternatively, the process time of the step S3 is 8-12S.
Alternatively, HBr, H are selected in the step S22And O2In removing the NMOS area
The dummy gate for exposing.
Present invention also offers a kind of semiconductor devices adopted and manufacture with the aforedescribed process.
Present invention also offers a kind of electronic installation, the electronic installation includes above-mentioned semiconductor devices.
The present invention also provides a kind of semiconductor devices of use above method manufacture.
The present invention also provides a kind of electronic installation, and the electronic installation includes the semiconductor devices.
The present invention is caused for the damage and etch residues, the residual of accessory substance that solve interlayer dielectric layer
A kind of inadequate clearly problem in NMOS and PMOS borders, there is provided preparation method of new semiconductor devices,
Methods described selects HBr, NF during the overetch after the etching removal dummy gate3And Ar
Combination or H2Combination with Ar carries out overetch, to remove the dummy gate completely, and in institute
State and the residue on the virtual opening sidewalls is processed from Ar after overetch, and repeat should
Step 4-5 times, can not only preferably remove removal of residue, can also reduce the loss of interlayer dielectric layer,
Cleaner NMOS and PMOS borders can be obtained simultaneously, the property of semiconductor devices is further improved
Energy and yield.
Brief description of the drawings
Drawings below of the invention is in this as a part of the invention for understanding the present invention.In accompanying drawing
Embodiments of the invention and its description are shown, for explaining device of the invention and principle.In accompanying drawing
In,
Fig. 1 is the process chart that the semiconductor devices is made according to one embodiment of the present invention；
Fig. 2 is the technological process that the semiconductor devices is made according to another implementation method of the invention
Figure.
Specific embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more thoroughly
Understand.It is, however, obvious to a person skilled in the art that the present invention can be without one
Or multiple these details and be carried out.In other examples, in order to avoid obscuring with the present invention,
It is not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and should not be construed as being limited to this
In propose embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will be originally
The scope of invention fully passes to those skilled in the art.In the accompanying drawings, for clarity, Ceng He areas
Size and relative size may be exaggerated.Same reference numerals represent identical element from start to finish.
It should be understood that be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to " or " coupling
Close " other elements or during layer, it can directly on other elements or layer, adjacent thereto, connection
Or other elements or layer are coupled to, or there may be element or layer between two parties.Conversely, when element is claimed
It is " on directly existing ... ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other units
When part or layer, then in the absence of element or layer between two parties.Although it should be understood that term first, the can be used
2nd, the third various elements of description, part, area, floor and/or part, these elements, part, area,
Layer and/or part should not be limited by these terms.These terms be used merely to distinguish element, part,
Area, floor or part and another element, part, area, floor or part.Therefore, the present invention is not being departed from
Under teaching, the first element discussed below, part, area, floor or part be represented by the second element,
Part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ",
" ... on ", " above " etc., can describe for convenience herein and by using so as in description figure
A shown element or feature and other elements or the relation of feature.It should be understood that except shown in figure
Orientation beyond, spatial relationship term be intended to also include use and operate in device different orientation.Example
Such as, if device upset in accompanying drawing, then, it is described as " below other elements " or " its it
Under " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, example
Property term " ... below " and " ... under " may include it is upper and lower two orientation.Device can additionally take
Correspondingly explained to (being rotated by 90 ° or other orientations) and spatial description language as used herein.
The purpose of term as used herein is only that description specific embodiment and not as limit of the invention
System.When using herein, " one " of singulative, " one " and " described/should " be also intended to include plural number
Form, unless context is expressly noted that other mode.It is also to be understood that term " composition " and/or " including ",
When using in this specification, the feature, integer, step, operation, element and/or part are determined
Presence, but be not excluded for one or more other features, integer, step, operation, element, part
And/or the presence or addition of group.When using herein, term "and/or" includes any of related Listed Items
And all combinations.
Cross-sectional view herein with reference to the schematic diagram as desirable embodiment of the invention (and intermediate structure) comes
Description inventive embodiment.As a result, it is contemplated that by caused by such as manufacturing technology and/or tolerance from institute
Show the change of shape.Therefore, embodiments of the invention should not necessarily be limited to the specific shape in area shown here
Shape, but including due to for example manufacturing caused form variations.For example, the injection region for being shown as rectangle exists
Its edge generally have circle or bending features and/or implantation concentration gradient, rather than from injection region to non-note
The binary for entering area changes.Equally, by injecting the disposal area for being formed the disposal area and the injection can be caused to carry out
When the surface passed through between area in some injections.Therefore, the area for being shown in figure is substantially to illustrate
Property, their shape is not intended the true form in the area of display device and is not intended to limit the present invention
Scope.
In order to thoroughly understand the present invention, detailed step and detailed knot will be proposed in following description
Structure, to explain technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but
In addition to these detailed descriptions, the present invention can also have other embodiment.
Embodiment one
The method of the invention is illustrated below in conjunction with the accompanying drawings, wherein, Fig. 1 is according to the present invention
One implementation method makes the process chart of the semiconductor devices.
First, perform step 101, there is provided Semiconductor substrate, be formed with the semiconductor substrate
NMOS area and PMOS area, wherein, in the NMOS area and the PMOS area
It is formed with dummy gate and fills the interlayer dielectric layer in gap between the dummy gate, described
The hard mask layer of patterning is formed with PMOS area, to expose the void in the NMOS area
Intend grid.
Specifically, there is provided Semiconductor substrate, the Semiconductor substrate may include any semi-conducting material, institute
The material for stating semiconductor may include but be not limited to：Si, SiC, SiGe, SiGeC, Ge alloy, GeAs,
InAs, InP, and other III-V or group Ⅱ-Ⅵ compound semiconductor
The Semiconductor substrate can also include organic semiconductor or such as Si/SiGe, silicon-on-insulator
(SOI) layered semiconductor of SiGe (SGOI) or on insulator.The Semiconductor substrate 200
Including various isolation structures, such as shallow trench isolation.
Include NMOS area and PMOS area in the Semiconductor substrate, the NMOS area has
The NMOS dummy gate stacked structures on the channel region of Uniform Doped are formed in, PMOS area has shape
Into the PMOS dummy gate stacked structures on the channel region of Uniform Doped.
The NMOS dummy gates stacked structure includes high-pound dielectric layer (not shown), barrier layer (not
Show) and NMOS dummy gates, it is formed with the both sides of the NMOS dummy gates stacked structure
Grid gap wall (not shown).The PMOS dummy gates stacked structure includes high-pound dielectric layer (not
Show), barrier layer (not shown) and PMOS dummy gates, in PMOS dummy gates stacking
The both sides of structure are formed with grid gap wall (not shown).
Wherein, the material of the high-k dielectric layer can select high-g value, and depositional mode can be by changing
Learn the mode of vapour deposition (CVD) or ald (ALD).Material can be hafnium silica
(HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium zirconium oxide (HfZrO)
In a kind of or their any combination, can also be perovskite-type material.Barrier deposition mode can
With by other methods, the barrier layer such as ALD, CVD, physical vapour deposition (PVD) (PVD), sputterings
The preferred titanium nitride of material, 10~20 angstroms of thickness range
In a specific embodiment of the invention, the NMOS dummy gates and the PMOS are empty
The forming method for intending grid can select low-pressure chemical vapor phase deposition (LPCVD) technique, and the NMOS is virtual
The material of grid and the PMOS dummy gates is polysilicon.Form the process conditions of the polysilicon layer
Including：Reacting gas is silane (SiH4), the range of flow of the silane can for 100~200 cubic centimetres/
Minute (sccm), such as 150sccm；Temperature range can be 700~750 degrees Celsius in reaction chamber；Reaction chamber
Interior pressure can be 250~350 milli millimetress of mercury (mTorr), such as 300mTorr；In the reacting gas also
Buffer gas is may include, the buffer gas can be the stream of helium (He) or nitrogen, the helium and nitrogen
Amount scope can be 5~20 liters/min (slm), such as 8slm, 10slm or 15slm.It should be noted that
Above-described embodiment is only used for clearly illustrating embodiment of the present invention, it is not limited to above-mentioned numerical value
Scope and preparation method.
The material of the grid gap wall can for it is a kind of in silica, silicon nitride, silicon oxynitride or he
Combine composition.Preferably, the clearance wall is silica, silicon nitride collectively constituting, concrete technology
For：The first silicon oxide layer, first but silicon oxide layer and the second silicon oxide layer are formed on a semiconductor substrate,
Then clearance wall is formed using engraving method.The material of grid gap wall commonly used in the art can also be selected
And forming method, will not be repeated here.
Exemplarily, described in the both sides of the NMOS dummy gates and the PMOS dummy gates
Source/drain is formed with Semiconductor substrate.
Then, interlayer dielectric layer (ILD) is formed on the semiconductor substrate.Interlayer dielectric layer can make
With such as SiO2, fluorocarbon (CF), carbon doped silicon oxide (SiOC) or carbonitride of silicium (SiCN) etc..
Or, it is also possible to use and form film of SiCN films etc. on fluorocarbon (CF).Fluorocarbon
With fluorine (F) and carbon (C) as main component.Fluorocarbon can also be using with noncrystal (amorphism) structure
The material made.Interlayer dielectric layer can also be constructed using such as Porous such as carbon doped silicon oxide (SiOC).Can
With using thermal chemical vapor deposition method, plasma process.The formation of the interlayer dielectric layer can be selected
Method commonly used in the art is used, be will not be repeated here.
Exemplarily, flatening process is carried out to the interlayer dielectric layer, to remove the interlayer dielectric layer
The part of the NMOS dummy gates and the PMOS dummy gates is higher by, in other words, to described
Interlayer dielectric layer carries out flatening process, so that the interlayer dielectric layer is around the NMOS dummy gates
With the PMOS dummy gates and expose the NMOS dummy gates and the PMOS is virtual
Grid top surface.
Then, the PMOS dummy gates in the etching removal PMOS area, to form PMOS
Virtual opening.In a specific embodiment of the invention, coating is formed on the interlayer dielectric layer,
Coating covers the NMOS area and exposes the PMOS area, can be using commonly used in the art each
Suitable material is planted as above-mentioned coating, such as silicon nitride, above-mentioned coating can also use photoresist
Agent.As an example, the photoresist layer of patterning is formed on the interlayer dielectric layer to cover
Expose the PMOS area in the NOMS regions.
The PMOS dummy gates in the etching removal PMOS area, with the PMOS
The original position of dummy gate forms PMOS and is virtually open, and can remove the PMOS using dry etching
Dummy gate, dry method etch technology is included but is not limited to：Reactive ion etching (RIE), ion beam milling,
Plasma etching or laser cutting.Dry etching is carried out preferably by one or more RIE step.
After the PMOS dummy gates are removed using dry etching, a soft wet-cleaning (soft is can perform
WET) step is removing the residue in the PMOS dummy gates.Or, can be lost using wet method
The removal PMOS dummy gates are carved, wet etch method can use hydrofluoric acid solution, such as buffer oxide
Thing etchant or hydrofluoric acid cushioning liquid.Or, part dry method part wet etch can be used.
Then, the described virtual opening in PMOS area neutralizes to be deposited on the interlayer dielectric layer and is formed
Workfunction layers, the workfunction layers fill up the virtual opening.The workfunction layers
Material is including copper, aluminium, TiN or TaN etc., preferably, the material of the workfunction layers is copper,
The workfunction layers have compression stress.The workfunction layers forming method can be CVD or
PVD.The workfunction layers can also select metal material and forming method commonly used in the art,
Will not be repeated here.
Then, the workfunction layers are processed using flatening process until exposing the interlayer dielectric layer.
In other words, the portion that the workfunction layers are higher by the interlayer dielectric layer is removed using flatening process
Point.
In a specific embodiment of the invention, flatening process is performed, it is possible to use semiconductor manufacturing is led
Conventional flattening method realizes the planarization on surface in domain.The non-limiting examples of the flattening method
Including mechanical planarization method and cmp (CMP) flattening method.Cmp is put down
Smoothization method is more often used.
Deposition forms hard mask layer on the semiconductor substrate, the material of the hard mask layer include TaN,
TiN, TaC, TaSiN, WN, TiAl, TiAlN or combinations of the above.Form the hard mask layer
Method non-limiting examples include chemical vapour deposition technique (CVD), such as low temperature chemical vapor deposition
(LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), etc. from
Daughter chemical vapor deposition (PECVD).
In a specific embodiment of the invention, the material of the hard mask layer is TiN.The hard mask
Layer can select material and forming method commonly used in the art, will not be repeated here.
Then, etching hard mask layer is so that hard mask layer covering PMOS area exposes NMOS
Region.
First use photoetching process that the photoresist layer of patterning is formed on the hard mask layer to cover
State PMOS area and expose the NMOS area.The covering PMOS is formed on the hard membrane layer
The patterned blanket layer that the NMOS area is exposed in region can select material and shape commonly used in the art
Into method, above-described embodiment is only used for clearly illustrating embodiment of the present invention, it is not limited to
Above-mentioned material and preparation method.
Then, the cause resist layer according to patterning etches the metal hard mask layer, is covered firmly with described
Opening is formed in film layer.Dry etching, such as plasma etching, etching gas can be used includes chlorine
Change boron, chlorine, and some addition gas such as nitrogen, argon gas.The range of flow of the boron chloride and chlorine
Can be 0~150 cc/min (sccm) and 50~200 cc/mins (sccm), in reative cell
Pressure can be 5~20 millitorrs (mTorr), such as 15mTorr.It should be noted that above-described embodiment is only used
In clearly illustrating embodiment of the present invention, it is not limited to above-mentioned number range and preparation method.
Continuation is etched to the hard mask layer, so that the hard mask layer 205 covers the PMOS
Expose the NMOS area in region.Terminal engraving method commonly used in the art can be selected, herein no longer
Repeat.
Step 102 is performed, the dummy gate exposed in the NMOS area is removed, to be formed
NMOS is virtually open.
Specifically, in the hard mask layer etching removal NMOS area according to patterning
NMOS dummy gates.
The NMOS in the hard mask layer etching removal NMOS area according to patterning
Dummy gate, forms NMOS and is virtually open in the original position of the NMOS dummy gates 202.
In a specific embodiment of the invention, the polysilicon etch can use dry etching, for example instead
Answer any combination of ion(ic) etching, ion beam milling, plasma etching, laser ablation or these methods.
Single engraving method can be used, or more than one engraving method can also be used.Preferably by
One or more RIE step carries out dry etching.
NF is generally included using etching gas3、HBr、Cl2、CH2F2、O2One or several gases,
With some addition gas such as nitrogen, argon gas.The range of flow of the etching gas can be 0~150 cube li
M/min (sccm), reaction room pressure can be 3~50 millitorrs (mTorr), radio-frequency power be 600W~
Plasma etching is carried out under conditions of 1500W.It should be noted that above-described embodiment is only used for more
Clearly demonstrate embodiment of the present invention, it is not limited to above-mentioned number range and preparation method, ability
Field technique personnel can be unknown herein according to other method commonly used in the art is selected the need for preparing device
Carefully repeat.
In this embodiment, from HBr, H2And O2Remove expose in the NMOS area described
Dummy gate.
Exemplarily, the execution time of the polysilicon etch process is 15s to 25s, the polysilicon end
The execution time of point etch process is 10s to 20s.
Step 103 is performed, from HBr, NF3Combination with Ar carries out overetch, to remove institute completely
Dummy gate is stated, and the residue on the virtual opening sidewalls is entered from Ar after the overetch
Row treatment.
Specifically, in this step in order to remove the dummy gate completely, it is necessary to be with the mask layer
Mask carries out overetch, in this step HBr, NF3The overetch is carried out with the combination of Ar, while
In order to avoid a large amount of losses of interlayer dielectric layer, Ar treatment steps are performed after overetch step each time
Suddenly, residue or accessory substance in the virtual opening can be made to be more prone to removal by the treatment,
But also can become apparent from the border of NMOS and PMOS.
Alternatively, the time of the overetch and Ar treatment is 8-12S in this step, for example may be used
To select 10s.
Alternatively, the overetch is repeated in this step and the Ar is processed 4-5 times, and be every
Overetch followed by carries out the Ar treatment.
Alternatively, in this step, the gas flow of described HBr, Ar is 100~800sccm, institute
State NF3Gas flow be 10~50sccm.
Step 104 is performed, the residue on the virtual opening sidewalls is removed.
Alternatively, in this step from N2Remove the residue.
Step 105 is performed, etching aftertreatment technology (PET) is performed.
Etching aftertreatment technology is performed, the gas that the etching aftertreatment technology is used includes CF4It is mixed with Ar
Gas is closed, to reduce the process time of chip and keep the cleaning of the hard mask layer boundary layer.
The present invention is caused for the damage and etch residues, the residual of accessory substance that solve interlayer dielectric layer
A kind of interface problem that NMOS and PMOS borders are present, there is provided preparation method of new semiconductor devices,
Methods described selects HBr, NF during the overetch after the etching removal dummy gate3And Ar
Combination carry out overetch, to remove the dummy gate completely, and Ar is selected after the overetch
Residue on the virtual opening sidewalls is processed, and repeats the step 4-5 times, can not only
It is enough preferably to remove removal of residue, the loss of interlayer dielectric layer can also be reduced, while can obtain more dry
Net NMOS and PMOS borders, further improve the performance and yield of semiconductor devices.
Embodiment two
The method of the invention is illustrated below in conjunction with the accompanying drawings, wherein, Fig. 2 is according to the present invention
One implementation method makes the process chart of the semiconductor devices.
First, perform step 101, there is provided Semiconductor substrate, be formed with the semiconductor substrate
NMOS area and PMOS area, wherein, in the NMOS area and the PMOS area
It is formed with dummy gate and fills the interlayer dielectric layer in gap between the dummy gate, described
The hard mask layer of patterning is formed with NMOS area and the PMOS area, it is described to expose
The dummy gate in NMOS area.
Specifically, there is provided Semiconductor substrate, the Semiconductor substrate may include any semi-conducting material, institute
The material for stating semiconductor may include but be not limited to：Si, SiC, SiGe, SiGeC, Ge alloy, GeAs,
InAs, InP, and other III-V or group Ⅱ-Ⅵ compound semiconductor
The Semiconductor substrate can also include organic semiconductor or such as Si/SiGe, silicon-on-insulator
(SOI) layered semiconductor of SiGe (SGOI) or on insulator.The Semiconductor substrate 200
Including various isolation structures, such as shallow trench isolation.
Include NMOS area and PMOS area in the Semiconductor substrate, the NMOS area has
The NMOS dummy gate stacked structures on the channel region of Uniform Doped are formed in, PMOS area has shape
Into the PMOS dummy gate stacked structures on the channel region of Uniform Doped.
The NMOS dummy gates stacked structure includes high-pound dielectric layer (not shown), barrier layer (not
Show) and NMOS dummy gates, it is formed with the both sides of the NMOS dummy gates stacked structure
Grid gap wall (not shown).The PMOS dummy gates stacked structure includes high-pound dielectric layer (not
Show), barrier layer (not shown) and PMOS dummy gates, in PMOS dummy gates stacking
The both sides of structure are formed with grid gap wall (not shown).
Wherein, the material of the high-k dielectric layer can select high-g value, and depositional mode can be by changing
Learn the mode of vapour deposition (CVD) or ald (ALD).Material can be hafnium silica
(HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium zirconium oxide (HfZrO)
In a kind of or their any combination, can also be perovskite-type material.Barrier deposition mode can
With by other methods, the barrier layer such as ALD, CVD, physical vapour deposition (PVD) (PVD), sputterings
The preferred titanium nitride of material, 10~20 angstroms of thickness range
In a specific embodiment of the invention, the NMOS dummy gates and the PMOS are empty
The forming method for intending grid can select low-pressure chemical vapor phase deposition (LPCVD) technique, and the NMOS is virtual
The material of grid and the PMOS dummy gates is polysilicon.Form the process conditions of the polysilicon layer
Including：Reacting gas is silane (SiH4), the range of flow of the silane can for 100~200 cubic centimetres/
Minute (sccm), such as 150sccm；Temperature range can be 700~750 degrees Celsius in reaction chamber；Reaction chamber
Interior pressure can be 250~350 milli millimetress of mercury (mTorr), such as 300mTorr；In the reacting gas also
Buffer gas is may include, the buffer gas can be the stream of helium (He) or nitrogen, the helium and nitrogen
Amount scope can be 5~20 liters/min (slm), such as 8slm, 10slm or 15slm.It should be noted that
Above-described embodiment is only used for clearly illustrating embodiment of the present invention, it is not limited to above-mentioned numerical value
Scope and preparation method.
The material of the grid gap wall can for it is a kind of in silica, silicon nitride, silicon oxynitride or he
Combine composition.Preferably, the clearance wall is silica, silicon nitride collectively constituting, concrete technology
For：The first silicon oxide layer, first but silicon oxide layer and the second silicon oxide layer are formed on a semiconductor substrate,
Then clearance wall is formed using engraving method.The material of grid gap wall commonly used in the art can also be selected
And forming method, will not be repeated here.
Exemplarily, described in the both sides of the NMOS dummy gates and the PMOS dummy gates
Source/drain is formed with Semiconductor substrate.
Then, interlayer dielectric layer (ILD) is formed on the semiconductor substrate.Interlayer dielectric layer can make
With such as SiO2, fluorocarbon (CF), carbon doped silicon oxide (SiOC) or carbonitride of silicium (SiCN) etc..
Or, it is also possible to use and form film of SiCN films etc. on fluorocarbon (CF).Fluorocarbon
With fluorine (F) and carbon (C) as main component.Fluorocarbon can also be using with noncrystal (amorphism) structure
The material made.Interlayer dielectric layer can also be constructed using such as Porous such as carbon doped silicon oxide (SiOC).Can
With using thermal chemical vapor deposition method, plasma process.The formation of the interlayer dielectric layer can be selected
Method commonly used in the art is used, be will not be repeated here.
Exemplarily, flatening process is carried out to the interlayer dielectric layer, to remove the interlayer dielectric layer
The part of the NMOS dummy gates and the PMOS dummy gates is higher by, in other words, to described
Interlayer dielectric layer carries out flatening process, so that the interlayer dielectric layer is around the NMOS dummy gates
With the PMOS dummy gates and expose the NMOS dummy gates and the PMOS is virtual
Grid top surface.
Then, the PMOS dummy gates in the etching removal PMOS area, to form PMOS
Virtual opening.In a specific embodiment of the invention, coating is formed on the interlayer dielectric layer,
Coating covers the NMOS area and exposes the PMOS area, can be using commonly used in the art each
Suitable material is planted as above-mentioned coating, such as silicon nitride, above-mentioned coating can also use photoresist
Agent.As an example, the photoresist layer of patterning is formed on the interlayer dielectric layer to cover
Expose the PMOS area in the NOMS regions.
The PMOS dummy gates in the etching removal PMOS area, with the PMOS
The original position of dummy gate forms PMOS and is virtually open, and can remove the PMOS using dry etching
Dummy gate, dry method etch technology is included but is not limited to：Reactive ion etching (RIE), ion beam milling,
Plasma etching or laser cutting.Dry etching is carried out preferably by one or more RIE step.
After the PMOS dummy gates are removed using dry etching, a soft wet-cleaning (soft is can perform
WET) step is removing the residue in the PMOS dummy gates.Or, can be lost using wet method
The removal PMOS dummy gates are carved, wet etch method can use hydrofluoric acid solution, such as buffer oxide
Thing etchant or hydrofluoric acid cushioning liquid.Or, part dry method part wet etch can be used.
Then, the described virtual opening in PMOS area neutralizes to be deposited on the interlayer dielectric layer and is formed
Workfunction layers, the workfunction layers fill up the virtual opening.The workfunction layers
Material is including copper, aluminium, TiN or TaN etc., preferably, the material of the workfunction layers is copper,
The workfunction layers have compression stress.The workfunction layers forming method can be CVD or
PVD.The workfunction layers can also select metal material and forming method commonly used in the art,
Will not be repeated here.
Then, the workfunction layers are processed using flatening process until exposing the interlayer dielectric layer.
In other words, the portion that the workfunction layers are higher by the interlayer dielectric layer is removed using flatening process
Point.
In a specific embodiment of the invention, flatening process is performed, it is possible to use semiconductor manufacturing is led
Conventional flattening method realizes the planarization on surface in domain.The non-limiting examples of the flattening method
Including mechanical planarization method and cmp (CMP) flattening method.Cmp is put down
Smoothization method is more often used.
Deposition forms hard mask layer on the semiconductor substrate, the material of the hard mask layer include TaN,
TiN, TaC, TaSiN, WN, TiAl, TiAlN or combinations of the above.Form the hard mask layer
Method non-limiting examples include chemical vapour deposition technique (CVD), such as low temperature chemical vapor deposition
(LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), etc. from
Daughter chemical vapor deposition (PECVD).
In a specific embodiment of the invention, the material of the hard mask layer is TiN.The hard mask
Layer can select material and forming method commonly used in the art, will not be repeated here.
Then, etching hard mask layer is so that hard mask layer covering PMOS area exposes NMOS
Region.
First use photoetching process that the photoresist layer of patterning is formed on the hard mask layer to cover
State PMOS area and expose the NMOS area.The covering PMOS is formed on the hard membrane layer
The patterned blanket layer that the NMOS area is exposed in region can select material and shape commonly used in the art
Into method, above-described embodiment is only used for clearly illustrating embodiment of the present invention, it is not limited to
Above-mentioned material and preparation method.
Then, the cause resist layer according to patterning etches the metal hard mask layer, is covered firmly with described
Opening is formed in film layer.Dry etching, such as plasma etching, etching gas can be used includes chlorine
Change boron, chlorine, and some addition gas such as nitrogen, argon gas.The range of flow of the boron chloride and chlorine
Can be 0~150 cc/min (sccm) and 50~200 cc/mins (sccm), in reative cell
Pressure can be 5~20 millitorrs (mTorr), such as 15mTorr.It should be noted that above-described embodiment is only used
In clearly illustrating embodiment of the present invention, it is not limited to above-mentioned number range and preparation method.
Continuation is etched to the hard mask layer, so that the hard mask layer 205 covers the PMOS
Expose the NMOS area in region.Terminal engraving method commonly used in the art can be selected, herein no longer
Repeat.
Step 102 is performed, the dummy gate exposed in the NMOS area is removed, to be formed
NMOS is virtually open.
Specifically, in the hard mask layer etching removal NMOS area according to patterning
NMOS dummy gates.
The NMOS in the hard mask layer etching removal NMOS area according to patterning
Dummy gate, forms NMOS and is virtually open in the original position of the NMOS dummy gates 202.
In a specific embodiment of the invention, the polysilicon etch can use dry etching, for example instead
Answer any combination of ion(ic) etching, ion beam milling, plasma etching, laser ablation or these methods.
Single engraving method can be used, or more than one engraving method can also be used.Preferably by
One or more RIE step carries out dry etching.
NF is generally included using etching gas3、HBr、Cl2、CH2F2、O2One or several gases,
With some addition gas such as nitrogen, argon gas.The range of flow of the etching gas can be 0~150 cube li
M/min (sccm), reaction room pressure can be 3~50 millitorrs (mTorr), radio-frequency power be 600W~
Plasma etching is carried out under conditions of 1500W.It should be noted that above-described embodiment is only used for more
Clearly demonstrate embodiment of the present invention, it is not limited to above-mentioned number range and preparation method, ability
Field technique personnel can be unknown herein according to other method commonly used in the art is selected the need for preparing device
Carefully repeat.
In this embodiment, from HBr, H2And O2Remove expose in the NMOS area described
Dummy gate.
Exemplarily, the execution time of the polysilicon etch process is 15s to 25s, the polysilicon end
The execution time of point etch process is 10s to 20s.
Step 103 is performed, from H2Combination with Ar carries out overetch, described virtual to remove completely
Grid, and after the overetch from Ar to the residue on the virtual opening sidewalls at
Reason.
Specifically, in this step in order to remove the dummy gate completely, it is necessary to be with the mask layer
Mask carries out overetch, in this step H2The overetch is carried out with the combination of Ar, while in order to keep away
Exempt from a large amount of losses of interlayer dielectric layer, Ar process steps are performed after overetch step each time, pass through
The treatment can make residue or accessory substance in the virtual opening be more prone to removal, but also can
So that the border of NMOS and PMOS becomes apparent from.
Alternatively, the time of the overetch and Ar treatment is 8-12S in this step, for example may be used
To select 10s.
Alternatively, the overetch is repeated in this step and the Ar is processed 4-5 times, and be every
Overetch followed by carries out the Ar treatment.
Alternatively, in this step, the H2Gas flow be 100~800sccm, the NF3
Gas flow be 10~50sccm.
Step 104 is performed, the residue on the virtual opening sidewalls is removed.
Alternatively, in this step from N2Remove the residue.
Step 105 is performed, etching aftertreatment technology (PET) is performed.
Etching aftertreatment technology is performed, the gas that the etching aftertreatment technology is used includes CF4It is mixed with Ar
Gas is closed, to reduce the process time of chip and keep the cleaning of the hard mask layer boundary layer.
The present invention is caused for the damage and etch residues, the residual of accessory substance that solve interlayer dielectric layer
A kind of problem of NMOS and PMOS borders Presence of an interface layer, there is provided preparation side of new semiconductor devices
Method, methods described selects H during the overetch after the etching removal dummy gate2With Ar's
Combination carries out overetch, to remove the dummy gate completely, and Ar is selected after the overetch
Residue on the virtual opening sidewalls is processed, and repeats the step 4-5 times, can not only
It is enough preferably to remove removal of residue, the loss of interlayer dielectric layer can also be reduced, while can obtain more dry
Net NMOS and PMOS borders, further improve the performance and yield of semiconductor devices.
Embodiment three
Present invention also offers a kind of semiconductor devices, the semiconductor devices is by embodiment one and implements
Methods described in example two is prepared, and the semiconductor devices being prepared into by methods described avoids interlayer
The loss of dielectric layer, improves the performance bounds of NMOS and PMOS, further increases semiconductor device
The performance and yield of part.
Example IV
The present invention also provides a kind of electronic installation in addition, and it includes foregoing semiconductor devices.Or it includes
The semiconductor devices for obtaining is made using the methods described in embodiment one and embodiment two.
Because the semiconductor devices for including has performance higher, the electronic installation equally has above-mentioned advantage.
The electronic installation can be mobile phone, panel computer, notebook computer, net book, game machine,
Television set, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP
Etc. any electronic product or equipment, or any intermediate products including the semiconductor devices.Institute
Electronic installation is stated, due to having used the semiconductor devices, thus with better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-mentioned implementation
Example is only intended to citing and descriptive purpose, and is not intended to limit the invention to described embodiment
In the range of.In addition it will be appreciated by persons skilled in the art that the invention is not limited in above-mentioned implementation
Example, teaching of the invention can also make more kinds of variants and modifications, these variants and modifications
Within all falling within scope of the present invention.Protection scope of the present invention will by attached right
Book and its equivalent scope is asked to be defined.
Claims (11)
1. a kind of preparation method of semiconductor devices, including：
Step S1：There is provided Semiconductor substrate, be formed with the semiconductor substrate NMOS area and
PMOS area, wherein, it has been respectively formed on virtual grid in the NMOS area and the PMOS area
The interlayer dielectric layer in gap, forms in the PMOS area between pole and the filling dummy gate
There is the hard mask layer of patterning, to expose the dummy gate in the NMOS area；
Step S2：The dummy gate exposed in the NMOS area is removed, to form NMOS
Virtual opening；
Step S3：From HBr, NF3Combination or H with Ar2Combination with Ar carries out overetch,
To remove the dummy gate completely, and Ar is selected after the overetch to the virtual opening sidewalls
On residue processed；
Step S4：Repeating said steps S3 at least 4 times；
Step S5：Remove the residue on the virtual opening sidewalls.
2. method according to claim 1, it is characterised in that the step S1 includes：
Step S11：There is provided Semiconductor substrate, be formed with the semiconductor substrate NMOS area and
PMOS area, the NMOS area and the PMOS area be respectively formed on the dummy gate with
And fill the interlayer dielectric layer in gap between the dummy gate；
Step S12：Deposition forms SiO on the interlayer dielectric layer and the dummy gate2Layer,
To cover the top surface of the interlayer dielectric layer and the dummy gate；
Step S13：The dummy gate in the PMOS area is removed, it is virtual to form PMOS
Opening；
Step S14：Virtually it is open in the PMOS and neutralizes the SiO2Deposition forms work function gold on layer
Category layer, is virtually open with filling up the PMOS；
Step S15：Flatening process is performed, until exposing the interlayer dielectric layer；
Step S16：The hard mask layer of patterning is formed in the PMOS area.
3. method according to claim 1, it is characterised in that described in the step S3
HBr, Ar and H2Gas flow be 100~800sccm, the NF3Gas flow be 10~50
sccm。
4. method according to claim 1, it is characterised in that methods described also includes step S6：
Perform etching aftertreatment technology.
5. method according to claim 4, it is characterised in that the etching aftertreatment technology is selected
CF4And Ar.
6. method according to claim 1, it is characterised in that N is selected in the step S52
Remove the residue.
7. method according to claim 1, it is characterised in that institute is repeated in the step S4
State step S34-5 times.
8. method according to claim 1, it is characterised in that the process time of the step S3
It is 8-12S.
9. method according to claim 1, it is characterised in that in the step S2 from HBr,
H2And O2Remove the dummy gate exposed in the NMOS area.
10. the semiconductor devices that a kind of one of use claim 1-9 described method is manufactured.
A kind of 11. electronic installations, the electronic installation includes the semiconductor devices described in claim 10.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020058374A1 (en) * | 2000-11-16 | 2002-05-16 | Tae-Kyun Kim | Method of forming dual-metal gates in semiconductor device |
| US20040137750A1 (en) * | 2003-01-15 | 2004-07-15 | Tokyo Electron Limited | Method and apparatus for removing material from chamber and wafer surfaces by high temperature hydrogen-containing plasma |
| CN103681670A (en) * | 2012-08-30 | 2014-03-26 | 台湾积体电路制造股份有限公司 | Metal gate structure of a semiconductor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020058374A1 (en) * | 2000-11-16 | 2002-05-16 | Tae-Kyun Kim | Method of forming dual-metal gates in semiconductor device |
| US20040137750A1 (en) * | 2003-01-15 | 2004-07-15 | Tokyo Electron Limited | Method and apparatus for removing material from chamber and wafer surfaces by high temperature hydrogen-containing plasma |
| CN103681670A (en) * | 2012-08-30 | 2014-03-26 | 台湾积体电路制造股份有限公司 | Metal gate structure of a semiconductor device |
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