CN106899502A - A kind of trigger signal Segment routing device and method for PXIe backboards - Google Patents
A kind of trigger signal Segment routing device and method for PXIe backboards Download PDFInfo
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- CN106899502A CN106899502A CN201510954066.9A CN201510954066A CN106899502A CN 106899502 A CN106899502 A CN 106899502A CN 201510954066 A CN201510954066 A CN 201510954066A CN 106899502 A CN106899502 A CN 106899502A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/14—Routing performance; Theoretical aspects
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Abstract
The invention discloses a kind of trigger signal Segment routing device and method for PXIe backboards.The device includes that PXIe monitoring units are used to send control command to triggering routing unit according to the configuration information of pci bus；Triggering routing unit is used to be controlled the trigger signal route between two pci bus sections to enable according to the enable bit of control command, the intersegmental trigger signal route direction of two pci bus of direction position control according to control command.The present invention by the way that triggering routing unit is separately configured, can effectively reduce it is high for the performance requirement of FPGA in PXI monitoring units, while by simple logic control be capable of achieving triggering route control, effectively reduce interconnection high cost.
Description
Technical field
Road is segmented the present invention relates to observation and control technology field, more particularly to a kind of trigger signal for PXIe backboards
By device and method.
Background technology
Continued to develop with observation and control technology, the test object of the TT＆C system based on PXIe buses is also increasingly
Complexity, amount of test data is also increasing, and this has the cooperating of higher precision between being accomplished by test equipment
Ability.And the key that route is cooperating between guarantee test equipment is triggered, it is also between ensureing test data
The basis of temporal associativity and test result validity.One trigger source is routed to triggering terminal by triggering route,
The transmission that can be realized between event is route by triggering.The function is particularly important synchronization between multimode, strictly according to the facts
Existing multichannel logic analyser, multi-channel high-speed capture card, multichannel generator etc..
For large-scale synthesis integrated measurement system, pumping signal and test signal is more and relevance more
By force, it is the necessary condition that system realizes complicated test to trigger route.In currently available technology, PXIe backboards
A piece of fpga chip is controlled to complete by pci bus by host computer.But this kind of method is to FPGA's
Performance requirement is high, and chip pin quantity is more, and interconnects high cost.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of trigger signal for PXIe backboards to be segmented road
By device and method, it is used to solve performance requirement of the trigger signal route for fpga chip in the prior art
Height, while interconnecting the problem of high cost.
According to an aspect of of the present present invention, there is provided a kind of trigger signal Segment routing device for PXIe backboards,
Including：
PXIe monitoring units are used to send control life to triggering routing unit according to the configuration information of pci bus
Order；
The triggering routing unit is used for according to the enable bit of the control command two pci bus sections of control
Between trigger signal route enable, the described two pci bus sections of direction according to control command position control
Between trigger signal route direction.
Preferably, the triggering routing unit includes：
Positive transport module is used to be carried out and the result after logical operation according to enable bit signal and direction position signal
The positive transmission of the control intersegmental trigger signal of pci bus；
Backward transmissing module be used for according to enable bit signal and direction position non-signal carry out with after logical operation
The reverse transfer of the intersegmental trigger signal of output control pci bus.
Preferably, the triggering routing unit includes：
Triggering route reseting module is used to control the positive transport module and the backward transmissing module to be answered
Position.
Preferably, the triggering routing unit is used for：
In the control command, in units of every 2n data, the data according to each unit control two
The trigger signal route of pci bus section；Wherein, the n-bit data positioned at higher bit position is the enable bit,
N-bit data positioned at low bit position is the direction position, and n is positive integer.
Preferably, the triggering routing unit uses complex programmable logic device (CPLD), the PXIe prisons
Control unit uses on-site programmable gate array FPGA.
Preferably, the CPLD is communicated with the FPGA by universal serial bus.
According to another aspect of the present invention, there is provided a kind of trigger signal segmental routing method for PXIe backboards,
Including：
PXIe monitoring units are according to the configuration information of peripheral element extension interface pci bus to triggering routing unit
Send control command；
The triggering routing unit is controlled between two pci bus sections according to the enable bit of the control command
Trigger signal route is enabled, and the described two pci bus of direction position control according to the control command are intersegmental
Trigger signal route direction.
Preferably, methods described also includes：
The triggering routing unit is carried out and the result after logical operation according to enable bit signal and direction position signal
The positive transmission of the control intersegmental trigger signal of pci bus；And, according to enable bit signal and direction position it is non-
Signal carries out the reverse transfer with the intersegmental trigger signal of output control pci bus after logical operation.
Preferably, methods described also includes：
In the control command, in units of every 2n data, the triggering routing unit is according to each list
The data of position control two trigger signal routes of pci bus section；Wherein, positioned at the n digits of higher bit position
According to the enable bit is, the n-bit data positioned at low bit position is the direction position, and n is positive integer.
Preferably, methods described also includes：
The digit of higher bit position is relative with the digit of low bit position where the position of the direction where the enable bit
Should.
The present invention has following technique effect：
Trigger signal Segment routing device provided by the present invention controls two by the enable bit in control command
The intersegmental outlet signal route of bus is enabled, by between two total segments of direction position control in control command
Trigger signal route direction.By the way that triggering routing unit is separately configured in the present invention, can effectively reduce
For the performance requirement of FPGA in PXI monitoring units, while being to be capable of achieving to touch by simple logic control
The control of route is sent out, interconnection cost is effectively reduced.
Described above is only the general introduction of technical solution of the present invention, in order to better understand technology of the invention
Means, and being practiced according to the content of specification, and in order to allow above and other objects of the present invention,
Feature and advantage can become apparent, below especially exemplified by specific embodiment of the invention.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to implementing
Example or the accompanying drawing to be used needed for description of the prior art are briefly described, it should be apparent that, retouch below
Accompanying drawing in stating only some embodiments of the present invention, for those of ordinary skill in the art, not
On the premise of paying creative labor, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is that the PXIe backboards principle of applications trigger signal subsection route device in the embodiment of the present invention is illustrated
Figure；
Fig. 2 is the principle schematic of trigger signal Segment routing device in the embodiment of the present invention；
Fig. 3 is the schematic diagram of the configuration mode of trigger signal Segment routing in the embodiment of the present invention；
Fig. 4 is the logic circuit schematic diagram of triggering routing unit use in the embodiment of the present invention；
Fig. 5 is the flow chart of trigger signal segmental routing method in the embodiment of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly
Chu, it is fully described by, it is clear that described embodiment is only a part of embodiment of the invention, rather than
Whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not making creation
Property work under the premise of the every other embodiment that is obtained, belong to the scope of protection of the invention.
Referring to Fig. 1, the trigger signal Segment routing device for PXIe backboards provided by the present invention, including：
PXI monitoring units are used to send control command to triggering routing unit according to the configuration information of pci bus；
Triggering routing unit is used to control the triggering between two pci bus sections according to the enable bit of control command
Signal route is enabled, the intersegmental trigger signal route of two pci bus of direction position control according to control command
Direction.
Trigger signal Segment routing device provided by the present invention controls two by the enable bit in control command
The intersegmental trigger signal route of bus is enabled, by between two total segments of direction position control in control command
Trigger signal route direction.By the way that triggering routing unit is separately configured in the present invention, can effectively reduce
For the performance requirement of FPGA in PXI monitoring units, while being to be capable of achieving to touch by simple logic control
The control of route is sent out, interconnection cost is effectively reduced.
Referring to Fig. 2, in one embodiment provided by the present invention, PXI monitoring units use fpga chip,
Can not only realize triggering the control of routing unit, while being additionally operable to detect that backboard supply voltage, backboard dissipate
The status display of enthusiasm condition and backboard.Triggering routing unit is CPLD chips.Wherein, triggering route
Unit is realized using 1 CPLD chip of model EPM240F100.Bus Interface Unit is using multiple
Pci bus section, by the control of CPLD chips, realizes the signal transmission between each pci bus section.
When being triggered, host computer sends configuration information to fpga chip, FPGA by pci bus
Control command is sent to CPLD chips by the IP kernel of chip by universal serial bus.CPLD chips are according to serial
Bus control signal configures the route of trigger signal, to triggering route carries out Discrete control.In the present embodiment,
Routing configuration information will be triggered by PC control FPGA it will be sent to CPLD chips and realize function, will drop
The low complexity of fpga chip function, improves the stability of performance, reduces chip pin quantity,
Reduce interconnection cost.
Specifically, there are 3 pci bus sections in PXIe backboards, each total segment includes 6 groove positions.Wherein,
1~6 groove is pci bus 1 (PXI BUS SEG1) of section, 7~12 groove pci bus section, 2 (PXI BUS SEG
2), 13~18 groove pci bus section, 3 (PXI BUS SEG 3).Wherein, pci bus section 3 is relative to PCI
The total segment high of total segment 2；Pci bus section 2 is total segment high relative to pci bus section 1.Different PCI
The PXI Trigger Bus acquiescence of total segment is physically-isolated, if necessary to be triggered between different bus section, is needed
Triggering route is set.Triggering route in the present embodiment has 7 kinds of Setting patterns, specific as follows：
PXI BUS SEG1→PXI BUS SEG 2
PXI BUS SEG 2→PXI BUS SEG 3
PXI BUS SEG 1←PXI BUS SEG 2
PXI BUS SEG 2←PXI BUS SEG 3
PXI BUS SEG 1→PXI BUS SEG 2→PXI BUS SEG 3
PXI BUS SEG 1←PXI BUS SEG 2←PXI BUS SEG 3
PXI BUS SEG 1←PXI BUS SEG 2→PXI BUS SEG 3
CPLD chips are described in detail to the detailed process that triggering route pattern is controlled below.Tool
Body ground, the control command that FPGA sends need to be the multiple of 2n.In control command, CPLD is with every 2n
In units of the data of position, triggering routing unit controls two triggerings of pci bus section according to the data of each unit
Signal route；Wherein, the n-bit data positioned at higher bit position is enable bit, positioned at n of low bit position
Data are direction position, and n is positive integer.Enable bit is in the digit of higher bit position and direction position in low bit position
Digit need correspond.Enable bit and corresponding direction position coordinate, you can realize pci bus
Route test.Illustrated with the control command of the integer data of 32-bit below.
Specifically, CPLD chips are whole when the Segment routing of trigger signal is controlled according to 32-bit integer datas
Type data distribution mode can be found in Fig. 3.When data are distributed, the low 16-bit controls PCI of 32-bit control signals
Connection between total segment 1, pci bus section 2；Between control pci bus section 2, pci bus section 3
Connection.And 16-bit high and low 16-bit include that triggering route enables signal and triggering route direction signal respectively.
Specifically, 8-bit high is triggering route enable signal in 16-bit control signals, in control pci bus section
The signal triggering of PXI_TRIG0~7；, low 8-bit is triggering route direction signal, in each pci bus section
The corresponding route direction signal in PXI_TRIG0~7.8-bit triggerings route ena-bung function high is touched with low 8-bit's
Hair route direction signal is corresponded.For example in Fig. 3, bit [8] and bit [0] in the low bit position of control command
It is corresponding, the Trigger Bus TRIG0 of lowest order in control PXI total segments；Bit [15] is corresponding with bit [7],
The Trigger Bus PXI_TRIG7 of highest order in control pci bus section.
Specifically, as shown in figure 3, CPLD chips according to control command trigger the specific reality of route test
Existing mode is as follows.Only illustrated by taking the trigger process of low level Trigger Bus TRIG0 as an example in the present embodiment.
If bit [0]=1, bit [8]=1, then PXI BUS SEG1_trig0 triggerings are routed to PXI BUS SEG
2_trig0, if now bit [24]=0, this time routing configuration is PXI BUS SEG1_trig0 → PXI BUS
SEG 2_trig0.If now bit [24]=1, bit [16]=1, then this time routing configuration is PXI BUS SEG1_trig0
→PXI BUS SEG 2_trig0→PXI BUS SEG 3_trig0。
If bit [0]=0, bit [8]=1, then PXI BUS SEG2_trig0 triggerings are routed to PXI BUS SEG
1_trig0, if now bit [24]=0, this time routing configuration is PXI BUS SEG2_trig0 → PXI BUS
SEG 1_trig0.If now bit [24]=1, bit [16]=0, then this time routing configuration is PXI BUS SEG3_trig0
→PXI BUS SEG 2_trig0→PXI BUS SEG 1_trig0.If now bit [24]=1, bit [16]=1,
Then this time routing configuration is PXI BUS SEG 1_trig0 ← PXI BUS SEG 2_trig0 → PXI BUS SEG
3_trig0。
If bit [8]=0, if now bit [24]=1, bit [16]=0, then this time routing configuration is PXI BUS
SEG3_trig0→PXI BUS SEG 2_trig0.If now bit [24]=1, bit [16]=1, PXI BUS
SEG2_trig0→PXI BUS SEG 3_trig0。
Further, the logic control that CPLD chips are used includes positive transport module and reverse transfer mould
Block.Wherein, positive transport module is used to be carried out and the knot after computing according to enable bit signal and direction position signal
Fruit control PCI total segments high are exported to the low total segments of PCI；Backward transmissing module is used for according to enable bit signal
The low total segments of output control PCI after computing are carried out with the non-signal of direction position to export to PCI total segments high.
Specifically, when enable bit is 1, triggering route is enabled；Triggering route is forbidden when enable bit is 0；Direction position
It is 1, controls the PCI low total segments of total segment → PCI high；When direction position is 0, the low total segments of control PCI →
PCI total segments high.Referring to Fig. 4, the control logic of CPLD inside PXI_TRIG0 trigger signal routes.Figure
In, rst is triggering route reset signal, and trig_left0 connects the PXI_TRIG0, trig_right0 of low total segment
The PXI_TRIG0 of total segment high is connected, en [8] is triggering route shielded signal, and en [0] is triggering route direction
Signal.
Further, triggering route reseting module is also included in the logic control circuit, for controlling positive biography
Defeated module and backward transmissing module are resetted.Specifically, the triggering route reset signal rst in figure makees respectively
For two with the Enable Pin of logical device.After electricity on backboard, triggering route reset signal rst keeps low level,
Two inputs of the low total segments of PCI and PCI total segments high are off-state.After triggering route is set, rst is put
It is high level.Referring in Fig. 4, rst keeps low level after electricity on backboard, and trig_left0, trig_right0 are
Off-state.After triggering route is set, rst is put for high level.
Referring to Fig. 5, present invention also offers a kind of trigger signal segmental routing method for PXIe backboards,
Based on above-mentioned trigger signal Segment routing device.The method comprises the following steps：
Step 101, PXIe monitoring units are according to the configuration information of peripheral element extension interface pci bus to touching
Hair routing unit sends control command；
Step 102, triggering routing unit controls PCI total segments high and PCI according to the enable bit of control command
The intersegmental trigger signal route of low bus is enabled, direction according to control command position control PCI total segments high with
The intersegmental trigger signal route direction of the low buses of PCI.
Further, method also includes：
Triggering routing unit is carried out and the output control PCI after computing according to enable bit signal and direction position signal
Total segment high is to the low total segments of PCI；
It is defeated that non-signal according to enable bit signal and direction position carries out the low total segments of output control PCI after computing
Go out to PCI total segments high.
Further, the method also includes：
Control command is the integral multiple of 2n, and triggering routing unit controls two PCI total according to per 2n data
The trigger signal route of line segment；Wherein, in per 2n data, higher bit position is enable bit, low bit position
It is direction position；Wherein, n is positive integer.
Further, the method also includes：
The digit of higher bit position is corresponding with the digit of low bit position where the position of direction where enable bit.Each makes
The corresponding direction position in energy position is engaged, you can realize the control of corresponding pci bus.
One of ordinary skill in the art will appreciate that all or part of flow in realizing above-described embodiment method,
Computer program be can be by instruct the hardware of correlation to complete, program can be stored in embodied on computer readable
In storage medium, the program is upon execution, it may include such as the flow of the embodiment of above-mentioned each method.
Although describing the application by embodiment, it will be apparent to one skilled in the art that the application has many changes
Shape and change are without departing from the spirit and scope of the present invention.So, if these modifications of the invention and modification
Belong within the scope of the claims in the present invention and its equivalent technologies, then the present invention is also intended to be changed comprising these
Including modification.
Claims (10)
1. a kind of trigger signal Segment routing device for PXIe backboards, it is characterised in that including：
PXIe monitoring units are used to be route to triggering according to the configuration information of peripheral element extension interface pci bus
Unit sends control command；
The triggering routing unit is used for according to the enable bit of the control command two pci bus sections of control
Between trigger signal route enable, the described two pci bus sections of direction according to control command position control
Between trigger signal route direction.
2. device as claimed in claim 1, it is characterised in that the triggering routing unit includes：
Positive transport module is used to be carried out and the result after logical operation according to enable bit signal and direction position signal
The positive transmission of the control intersegmental trigger signal of pci bus；
Backward transmissing module be used for according to enable bit signal and direction position non-signal carry out with after logical operation
The reverse transfer of the intersegmental trigger signal of output control pci bus.
3. device as claimed in claim 2, it is characterised in that the triggering routing unit also includes：
Triggering route reseting module is used to control the positive transport module and the backward transmissing module to be answered
Position.
4. device as claimed in claim 1, it is characterised in that the triggering routing unit is used for：
In the control command, in units of every 2n data, the data according to each unit control two
The trigger signal route of pci bus section；Wherein, the n-bit data positioned at higher bit position is the enable bit,
N-bit data positioned at low bit position is the direction position, and n is positive integer.
5. device as claimed in claim 1, it is characterised in that
The triggering routing unit uses complex programmable logic device (CPLD), the PXIe monitoring units to adopt
Use on-site programmable gate array FPGA.
6. device as claimed in claim 5, it is characterised in that
The CPLD is communicated with the FPGA by universal serial bus.
7. a kind of trigger signal segmental routing method for PXIe backboards, it is characterised in that including：
PXIe monitoring units are according to the configuration information of peripheral element extension interface pci bus to triggering routing unit
Send control command；
The triggering routing unit is controlled between two pci bus sections according to the enable bit of the control command
Trigger signal route is enabled, and the described two pci bus of direction position control according to the control command are intersegmental
Trigger signal route direction.
8. method as claimed in claim 7, it is characterised in that methods described also includes：
The triggering routing unit is carried out and the result after logical operation according to enable bit signal and direction position signal
The positive transmission of the control intersegmental trigger signal of pci bus；And, according to enable bit signal and direction position it is non-
Signal carries out the reverse transfer with the intersegmental trigger signal of output control pci bus after logical operation.
9. method as claimed in claim 7, it is characterised in that methods described also includes：
In the control command, it is described triggering routing unit in units of every 2n data, according to each list
The data of position control two trigger signal routes of pci bus section；Wherein, positioned at the n digits of higher bit position
According to the enable bit is, the n-bit data positioned at low bit position is the direction position, and n is positive integer.
10. method as claimed in claim 9, it is characterised in that methods described also includes：
The digit of higher bit position is relative with the digit of low bit position where the position of the direction where the enable bit
Should.
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| CN201510954066.9A CN106899502B (en) | 2015-12-17 | 2015-12-17 | trigger signal segmented routing device and method for PXIe backboard |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117170282A (en) * | 2023-09-04 | 2023-12-05 | 苏州异格技术有限公司 | Trigger method and device of logic analyzer based on FPGA |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202976064U (en) * | 2012-10-29 | 2013-06-05 | 北京航天测控技术有限公司 | Integrated trigger routing device applied to PXI intelligent test platform equipment |
| CN103678238A (en) * | 2013-12-30 | 2014-03-26 | 北京航天测控技术有限公司 | LXI-PXI\PXIe adaptation system |
| CN103870323A (en) * | 2012-12-17 | 2014-06-18 | 美国亚德诺半导体公司 | Trigger routing unit |
-
2015
- 2015-12-17 CN CN201510954066.9A patent/CN106899502B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202976064U (en) * | 2012-10-29 | 2013-06-05 | 北京航天测控技术有限公司 | Integrated trigger routing device applied to PXI intelligent test platform equipment |
| CN103870323A (en) * | 2012-12-17 | 2014-06-18 | 美国亚德诺半导体公司 | Trigger routing unit |
| CN103678238A (en) * | 2013-12-30 | 2014-03-26 | 北京航天测控技术有限公司 | LXI-PXI\PXIe adaptation system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117170282A (en) * | 2023-09-04 | 2023-12-05 | 苏州异格技术有限公司 | Trigger method and device of logic analyzer based on FPGA |
| CN117170282B (en) * | 2023-09-04 | 2024-05-17 | 苏州异格技术有限公司 | Trigger method and device of logic analyzer based on FPGA |
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