CN106899313A - A kind of Turbo code code translator and method for supporting LTE standard - Google Patents

Abstract

The present invention relates to a kind of Turbo code code translator and method for supporting LTE standard.The device includes two component decoder serially concatenateds, is connected by interleaver and deinterleaver between the two, and interleaver is identical with used interleaver is deinterleaved, and deinterleaving is the inverse operation of the interleaver.The method realizes the Turbo code of LTE standard using the Turbo decoding frameworks of base 2, and optimizes treatment to key component therein.This method by using the adjustable length design of sliding window so as to support 188 kinds of patterns of different code block lengths in LTE standard, simultaneously by using the unit-modularized mentality of designing of core calculations, reduce the computing resource that algorithm is realized taking, accelerate the decoding speed of algorithm simultaneously, improve the handling capacity of decoding.

Description

A kind of Turbo code code translator and method for supporting LTE standard

Technical field

The invention belongs to GSM technical field, more particularly to a kind of Turbo code code translator and method.

Background technology

Turbo code has intrinsic concurrency, coding gain high, and because Turbo code applies Shannon Channel well Randomness coding and decoding condition in coding theorem and obtain the decoding performance and error-correcting performance close to shannon limit, therefore, Turbo Code is adopted by many communication standards such as WiMax, CCSDS, 3GPP LTE, HSDPA.

LTE standard is a communication standard having been widely adopted, and the rsc encoder that it is used is (13,15) systematic code, rule 188 kinds of Turbo codes of different Turbo code code block lengths are determined, code block length is from 40~6144.Therefore, it can both be used In the fewer short frame of transmission this data volume of control information, it is also possible to for the very big length of this data volume of transmitting data information Frame.The decoder of Turbo code realized using 2-base algorithm or Radix 4 algorithm mostly at present, the basic thought of Radix 4 algorithm be by Former and later two moment of 2-base algorithm merge into a moment and are processed, when log-likelihood ratio is calculated, by 1 input of base 2 It is changed into 2 inputs, therefore, the access times of the decoding algorithm memory of base 4 only have the 1/2 of 2-base algorithm, the front and rear recurrence that need to be stored Variable is also changed into original half, however it is necessary that the branch metric number for considering then is changed into original 2 times, it is necessary to more massive Circuit is processed, and single branch metric computation complexity increase, cause not processed in clock, generally require Accelerate decoding speed, but this processing mode by the way of parallel piecemeal due to by piecemeal number, calculation of initial value Tend not to support whole patterns of LTE standard etc. the limitation of factor.

The content of the invention

Therefore, to solve the above problems, the present invention is special to propose a kind of Turbo code code translator for supporting LTE standard and side Method, the method realizes the Turbo code of LTE standard using base 2Turbo decoding frameworks, and key component therein is carried out excellent Change is processed.

Using the benefit of base 2Turbo decoding architectures：

1st, can be completed with being calculated in a clock when alpha and beta values are calculated using base 2Turbo decoding algorithms, subtracted The length of critical path is lacked, therefore, there is no need to by the way of multiple data blocks carry out parallel computation, such that it is able to save meter Calculate the computing resource spent by beta value initial values；

Although the 2nd, fast using calculating speed of the base 2Turbo decoding algorithms without base 4Turbo decoding algorithms, the former compares the latter Calculating process it is simply too much, shared resource is also many less；

3rd, not only calculating process is simple for base 2Turbo decoding algorithms, and because status number is largely reduced, accordingly, it would be desirable to calculate The number of branch metric gamma also greatly reduces, so as to save area；

4th, base 4Turbo decoding algorithms by deinterleaving the aspects such as parameter, degree of parallelism due to being constrained, and some code block lengths are uncomfortable Base 4Turbo decoding algorithms, the particularly shorter situation of code block length are preferably used, and base 2Turbo decoding algorithms are then to Turbo Code code block length does not have particular/special requirement.

The basic structure of the Turbo decoders of base 2 is as shown in figure 1, it is a process for iterative recursive.It is by two points Amount decoder (DEC1) and (DEC2) serially concatenated is formed.First, system position information and the check bit information one by selector First component decoder (DEC1) of feeding, the external information of generation by interleaver, with the system position information by interweaving and Second component decoder (DEC2) is imported into together by the check bit information two of selector, and the external information of generation is by solution It is sent to after intertexture in first component decoder (DEC1), by such interative computation for several times, to component decoder (DEC2) feeding judging module makes decisions and can obtain final decoding result after the log-likelihood ratio of output is deinterleaved. Wherein, the interleaver between two component decoders is identical with the interleaver that decoder internal is used, and deinterleaving is the intertexture The inverse operation of device.

As shown in figure 1, each component decoder has 3 inputs,

(1) the system position information received from channelOr the system position information by interweaving；

(2) the check bit information of the corresponding encoded device received from channel

(3) the likelihood information L of the every bit obtained from another component decoder^a(u_k)。

A kind of method that Turbo code for supporting 188 kinds of code block lengths of LTE standard is decoded, using base 2Turbo decoding frameworks To realize the Turbo code of LTE standard, and treatment is optimized to key component therein, particular content includes being based on Log- The Gabi selection arithmetic element of Max-MAP algorithms, the recursive calculation unit realized based on sliding window and sliding window is long under different code block length The control unit of degree.

MAP algorithms need to travel through each paths in convolutional code trrellis diagram, are the algorithms of best performance.Its basic thought be Receiving sequence is under conditions of Y, calculating often decodes the probability that bit is+1 or -1.This is equivalent to the logarithm for calculating posterior probability seemingly So it is worth, i.e. L (u_k| Y), it can be obtained by formula (1)

Wherein, (s', s)=＞ u_k=+1 is represented in trrellis diagram, and u is input into when the kth moment_kWhen=+ 1, by the moment of kth -1 state S_k-1=s' to kth moment state S_kThe all possible state transfer of=s, (s', s)=＞ u_k=-1 implication is similar. α_kS () is kth moment state S_kThe forward state metric of=s, β_kS () is kth moment state S_kThe backward state measurement of=s, γ_k (s' s) is the moment of kth -1 state S_k-1=s' shifts kth moment state S_kBranch's transfering sheet of=s, their computing formula Respectively

α_k(s)=∑_{all s'}α_k-1(s')γ_k(s',s) (2)

β_k-1(s')=∑_{all s}β_k(s)γ_k(s',s) (3)

Wherein, u in formula (4)_kThe input information at kth moment is represented,Represent that the input of kth moment is u_kUnder conditions of encoder Pth (p=1,2) individual output,Represent pth (p=1,2) the individual observation signal at kth moment.

Notice that MAP algorithms test log-likelihood ratio L (u after computation_k| Y) when, substantial amounts of multiplication, division arithmetic are directed to, Cleverly be put into log-domain for these computings and carry out by Max-Log-MAP algorithms, can so be converted into multiplication and division method and add, subtracts Method computing, such that it is able to greatly simplify computation complexity.Make A_k(s)=ln (α_k(s)), B_k(s)=ln (β_k(s)), Γ_k(s',s) =ln (γ_k(s', s)), then can obtain

In order to be calculated the log-likelihood ratio of every bit, it is necessary to first calculate forward and backward state measurement and branch's transfering sheet. But due to forward and backward state measurement iteration order contrast, it is necessary to enter to forward state metric (or backward state measurement) Row storage, until corresponding backward state measurement iterative calculation is completed, can just carry out the calculating of log-likelihood ratio, and this will lead Cause decoding latency it is very big, particularly Turbo code code block length it is larger in the case of, therefore, be difficult to bear in systems in practice.

In order to solve the problems, such as that decoding delay is excessive, realized using sliding window method.Its general principle is the Max- of base 2 The sliding window structure of Log-MAP algorithms is as shown in Fig. 2 it mainly includes branch metric Gamma computing modules, forward state metric Alpha recursive calculation module RU_A, for after module RU_B1 from recursive calculation to state measurement Beta initial values, for recurrence Calculate the RU_B2 modules and log-likelihood ratio LLR computing modules of Beta right values.

As can be seen that sliding window method only needs to wait for a less decoding latency, 3~5 times of constraint degree code elements are about transmitted Several time, then can just start to calculate log-likelihood ratio, this decoding latency changes with the forward metrics of whole code elements are waited In generation, calculates to finish and compares, and greatly reduces decoding latency.

In the present invention in order to support various code lengths, while in order to simplify design, therefore it is variable to be considered as sliding window length Form realize.188 kinds of initial code block lengths are translated into the integral multiple of corresponding sliding window length, while considering sliding window Length can influence the accuracy of result, therefore, the sliding window distributed should be big as far as possible.On the other hand, Turbo in LTE standard The minimum code block length of code is 40.Therefore, in order to compromise, the present invention is using 256 as maximum sliding window length, that is to say, that sliding window Length is between 40~256.The length for so calculating sliding window will meet 2 conditions：

1st, the length of sliding window<=256；

2nd, code block length is the integral multiple and as far as possible close 256 of the length of sliding window.

In intleav_addr modules, it is after being completed by calculated in advance for calculating of the design on sliding window length Store a high position of ROM.Therefore, the f of correspondence code length is found first with the low order address of ROM in the design₁, f₂Parameter, Ran Houzeng Increase the sliding window length that bit address finds correspondence code block length, so as to make full use of ROM Space.

The beneficial effects of the invention are as follows：

The invention provides a kind of Turbo code code translator that can support in LTE standard 188 kinds of different code block lengths and side Method.It is vulnerable to the factors such as degree of parallelism, calculation of initial value compared to base 4Turbo decoding algorithms and device and restricts it in Turbo code block Immalleable problem under conditions of length is shorter, this method be advantageous in that by using sliding window it is adjustable length design so as to 188 kinds of patterns of different code block lengths in LTE standard can be supported, while by using the unit-modularized design of core calculations Thinking, reduces the computing resource that algorithm is realized taking, while accelerating the decoding speed of algorithm, improves the handling capacity of decoding.

Brief description of the drawings

Fig. 1 base 2Turbo code decoder structural representations；

The sliding window structure of Fig. 2 base 2Max-Log-MAP algorithms；

Fig. 3 is based on the base 2Turbo decoder structure charts of sliding window；

The module computing unit of Fig. 4 base 2SISO decoding units；

The computing flow of the module computing unit of Fig. 5 bases 2SISO decodings；

The performance curve of Fig. 6 base 2Turbo code translators.

Specific embodiment

To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention Accompanying drawing, clear, complete description is carried out to the technical scheme in the present invention, it is clear that described embodiment be the present invention one Divide embodiment, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not making The every other embodiment obtained under the premise of creative work, belongs to the scope of the present invention.

The embodiment of the present invention discloses a kind of base 2Turbo decoders and method, refers to Fig. 3, and it includes 1. be input into altogether Information cache, 2. external information caching, the 3. calculating of beta values initial value, 4. system information caching, 5. alpha value caching, 6. alpha Value calculates, 7. the calculating of beta values, 8. interleave and deinterleave module, 9. control module and 10. export computing module.

1. it is input into information cache module

It is interval for caching input information that this module is mainly used in opening up N number of buffering, and it is 1 frame to cache interval size, and N can be with It is configured by parameter IN_BUFFER；

2. external information cache module

Because external information is all currently calculated, while there is other controls writing outer letter while external information is taken Breath.Ping-pong operation has been done for such case external information；

3. beta values initial value computing module

Due to using sliding window structure so needing to calculate the initial value of beta, the length for generally calculating is the length of sliding window Degree, but last sliding window is due to the presence of tail bit, therefore only need to be can be obtained by using 4 values of tail bit calculating The exact value of beta initial values.Interleaving treatment on system information when completing reading inside this module simultaneously；

4. system information cache module

The module is used to cache the system information of sliding window size, and due to alpha computing modules, beta computing modules and beta values rise Initial value computing module is required for operating this ram, and they need the system information used to belong to three adjacent sliding windows, because This, the wheel for being inside 3 ram seeks operation, so that conflict when effectively avoiding data storage；

5. alpha value cache module

The ram of the module is used to store the intermediate variable of alpha calculating, although do not existed the operation such as intertexture now, but Because the calculating of beta values is backward, it is phase that the output of current alpha computing modules and beta computing modules is corresponding respectively Alpha the and beta values of adjacent sliding window, therefore, it is necessary to store the value of alpha when calculating LLR value using them, so at this Operation the inside needs to use ping-pong operation；

6. alpha value computing module

Alpha is calculated and calculated according to alpha operation rules；

7. beta values computing module

The module needs to complete to also need to outside the calculating beta of the task to complete to calculate external information and maximum and feels relieved information, and produces Existence storage external information and maximum required deinterleaving address of feeling relieved；

8. interleave and deinterleave module

Interleave and deinterleave is a nucleus module in Turbo code coding and decoding, is used with pseudo-random characteristics in the present invention QPP interleavers.During Turbo decodings, the calculating of alpha value is carried out in order, and beta values are calculated by reverse calculating, because This is, it is necessary to produce the interleaving/deinterleaving address of beta：

Address (i)=f₁×i+f₂×i² (6)

Address (i+1)=f₁×(i+1)+f₂×(i+1)² (7)

Address (i+1)=(f₁×i+f₂×i²)+2f₂×i+f₁+f₂ (8)

Wherein, i=0,1 ..., K, K represent decoding code block length, f₁And f₂It is QPP interleaver parameters.Therefore, by above-mentioned point Analysis understands that interleaving/deinterleaving address can be realized by way of iteration, such that it is able to save multiplier resources.According to formula (8) Understand, the increment of interleaving address is 2 × f₂, initial value is f₁+f₂, only need to know that current interleave address increases for reverse derivation It is -2 × f to measure₂Required interleaving address can just be derived.Therefore, f is obtained in intleav_addr modules₁And f₂Parameter Afterwards, by the interleaving address of each sliding window position storage to specified RAM, then no matter subsequent arithmetic can to which sliding window Corresponding interleaving address is found out so as to be easy to derive next interleaving address；

9. control module

Control module is used to control the iterations of whole module, and DEC1 or DEC2 is belonged to always according to current Turbo decodings, right System information and external information selection interweave, deinterleave operation；

10. computing module is exported

Output computing module, is only intended to deinterleave calculating, and completion descrambling is calculated.In calculating is descrambled, translated to reduce Code time delay, it is possible to use the characteristic of ram, disposable output 8bit is descrambled parallel.

According to above-mentioned analysis, the core calculations unit of the decoding of base 2Turbo shown in Fig. 3 can stand alone as a module, such as scheme Shown in 4.As can be seen that what is either currently calculated is sequence address or interleaving address, this module is all available, and suitable Interleaving address difference is that the system information used in beta calculation of initial value modules and beta values are calculated to sequence address in other words Whether the external information that module is obtained needs plus interleaving address or is to deinterleave address.Therefore, under this decoding framework, can Unify with by the calculation of different address.

The computing flow of sliding window process is as shown in Figure 5.In order to realize the pipeline processes of sliding window calculating process, carry out first Calculating for beta initial values, the beta initial values for this time calculating will not be used, but it can store system information To 4. system information memory module.Beta initial values then in the adjacent sliding window of synchronization parallel computation, beta values and alpha Value, so as to improve the handling capacity of system decoding.

The situation of FPGA resource shared by the base 2Turbo decoders that Fig. 6 gives in the present invention, wherein, system information, Check information etc. uses 12 bit quantizations, and alpha value, beta values etc. then use 16 bit quantizations, Turbo decoding iterations 4 times. As can be seen that the resource that the Turbo decoders of invention take is relatively fewer.

The situation map of different Turbo code block length thresholding signal to noise ratios gives the Turbo code translators difference Turbo of invention The situation of the pattern of code block length its thresholding signal to noise ratio under conditions of bit error rate is met less than 10e-3.Signal in emulation It is qpsk modulation signal, it can be seen that the measured curve of snr threshold is basically identical with trend-analysis curves, works as code block length When smaller, its thresholding signal to noise ratio is higher, for example, when code length is 48, snr threshold is 2.01dB；And work as code block length compared with Hour, its thresholding signal to noise ratio is relative lower, for example, when code block length is 2944,3072,4224,5696,6016 etc., its Thresholding signal to noise ratio is only -1dB.

Claims (2)

1. a kind of Turbo code code translator for supporting LTE standard, by component decoder DEC1 and component decoder DEC2 serial stages Connection is formed, it is characterised in that first, and system position information and the check bit information one by selector send into component decoder DEC1, the external information of generation is by interleaver, the system position information interweaved with process and the check bit information by selector Two are imported into component decoder DEC2 together, the external information of generation in component decoder DEC1 is sent to after deinterleaving, By such interative computation for several times, judgement mould is sent into after being deinterleaved to the log-likelihood ratio that component decoder DEC2 is exported Block makes decisions and obtains final decoding result,

Each component decoder has 3 inputs,

(1) the system position information for being received from channelOr the system position information by interweaving；

(2) the check bit information of the corresponding encoded device for being received from channel

(3) the likelihood information L of the every bit for being obtained from another component decoder^a(u_k)。

2. a kind of method that Turbo code for supporting LTE standard is decoded, LTE standard is realized using base 2Turbo decoding frameworks Turbo code, it is characterised in that including based on Log-Max-MAP algorithms, the recursive calculation method realized based on sliding window and different codes The control method of sliding window length under block length,

It is described to be specially based on Log-Max-MAP algorithms：

Under conditions of receiving sequence is Y, the probability that often decoding bit is+1 or -1 is calculated, it is right equivalent to calculating posterior probability Number likelihood value, i.e. L (u_k| Y), it is obtained by formula (1)

$L\left(u_k\right|Y)=ln\left(\frac{{\mathrm{\&Sigma;}}_{(s^{\&prime;},s)=>u_k=+1}{\mathrm{\&alpha;}}_{k-1}\left(s^{\&prime;}\right){\mathrm{\&gamma;}}_k(s^{\&prime;},s){\mathrm{\&beta;}}_k\left(s\right)}{{\mathrm{\&Sigma;}}_{(s^{\&prime;},s)=>u_k-1}{\mathrm{\&alpha;}}_{k-1}\left(s^{\&prime;}\right){\mathrm{\&gamma;}}_k(s^{\&prime;},s){\mathrm{\&beta;}}_k\left(s\right)}\right)---\left(1\right)$

Wherein, (s', s)=＞ u_k=+1 is represented in trrellis diagram, and u is input into when the kth moment_kWhen=+ 1, by the moment of kth -1 state S_k-1 =s' to kth moment state S_kThe all possible state transfer of=s, (s', s)=＞ u_k=-1 implication is similar, α_k S () is kth moment state S_kThe forward state metric of=s, β_kS () is kth moment state S_kThe backward state measurement of=s, γ_k (s' s) is the moment of kth -1 state S_k-1=s' shifts kth moment state S_kBranch's transfering sheet of=s, their computing formula Respectively

α_k(s)=∑_{all s'}α_k-1(s')γ_k(s',s) (2)

β_k-1(s')=∑_{all s}β_k(s)γ_k(s',s) (3)

${\mathrm{\&gamma;}}_k(s^{\&prime;},s)=\exp \&lsqb;\frac{1}{2}{u}_k{L}^a\left(u_k\right)+\frac{1}{2}{u}_k{y}_k^s+\frac{1}{2}{x}_k^p{y}_k^p\&rsqb;---\left(4\right)$

Wherein, u in formula (4)_kThe input information at kth moment is represented,Represent that the input of kth moment is u_kUnder conditions of encoder Pth (p=1,2) individual output,Pth (p=1,2) the individual observation signal at kth moment is represented,

Log-likelihood ratio L (u are tested after computation_k| Y) when, be put into log-domain for these computings and carry out by Max-Log-MAP algorithms, will Multiplication and division method be converted into plus, subtraction so that simplify computation complexity, make A_k(s)=ln (α_k(s)), B_k(s)=ln (β_k (s)), Γ_k(s', s)=ln (γ_k(s', s)), then can obtain

$\begin{array}{c}{A}_k\left(s\right)=\ln \left({\mathrm{\&alpha;}}_k\right(s))=\ln \left({\mathrm{\&Sigma;}}_{{\mathrm{alls}}^{\&prime;}}{\mathrm{\&alpha;}}_{k-1}\right(s^{\&prime;}\left){\mathrm{\&gamma;}}_k\right(s^{\&prime;},s\left)\right)\\ =\ln \left({\mathrm{\&Sigma;}}_{{\mathrm{alls}}^{\&prime;}}\exp \right(A_{k-1}\left(s^{\&prime;}\right)+{\mathrm{\&Gamma;}}_k\left(s^{\&prime;},s\right)\left)\right)\&ap;\underset{s^{\&prime;}}{\max }\left(A_{k-1}\right(s^{\&prime;})+{\mathrm{\&Gamma;}}_k(s^{\&prime;},s\left)\right)\end{array}---\left(5\right);$

The recursive calculation method realized based on sliding window is specially：

Including branch metric Gamma computing modules, forward state metric Alpha recursive calculation module RU_A, for recursive calculation The module RU_B1 of backward state measurement Beta initial values, for the RU_B2 modules and log-likelihood of recursive calculation Beta right values Than LLR computing module, a less decoding latency is only needed to wait for, transmit 3~5 times of times of constraint degree he number, then Start to calculate log-likelihood ratio, this decoding latency compared with the forward metrics iterative calculation for waiting whole code elements is finished, significantly Reduce decoding latency；

The control method of sliding window length is specially under the different code block lengths：

The length for calculating sliding window meets 2 conditions：

(1), the length of sliding window<=256；

(2), code block length is the integral multiple and as far as possible close 256 of the length of sliding window.