CN106898651B - Manufacturing method of selectively etched LDMOS device - Google Patents

Manufacturing method of selectively etched LDMOS device Download PDF

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Publication number
CN106898651B
CN106898651B CN201710066412.9A CN201710066412A CN106898651B CN 106898651 B CN106898651 B CN 106898651B CN 201710066412 A CN201710066412 A CN 201710066412A CN 106898651 B CN106898651 B CN 106898651B
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layer
window
source
mask layer
interval
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CN106898651A (en
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柳志亨
郑志星
乔伊·迈克格雷格
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Chengdu Monolithic Power Systems Co Ltd
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

The invention provides a method for manufacturing an LDMOS device in a well region on a semiconductor substrate, which comprises the following steps: forming a body region and a source layer in the well region through the polysilicon layer window over the well region, wherein the body region has a junction depth deeper than the source layer; forming a space on the side wall of the inner side of the window of the polycrystalline silicon layer; and etching the source layer through the window formed by the space until the source layer is penetrated, wherein an area right below the space in the source layer is protected in the etching process of the source layer and is defined as a source area of the LDMOS device. The source region width is determined by the thickness of the spacers. The invention adopts interval and selective etching to form a narrower N +/P +/N + source/body region, thereby not only reducing the source region, but also effectively reducing the cost for manufacturing the LDMOS.

Description

A kind of manufacturing method of the LDMOS device of selective etch
Technical field
The present invention relates to semiconductor devices, it is more particularly related to manufacture horizontal proliferation type metal oxide half The method of conductor (LDMOS, Laterally Diffused Metal Oxide Semiconductor) device.
Background technique
LDMOS device be widely used in because of its high-breakdown-voltage, high current and good temperature characterisitic laptop, Server and DC/DC voltage conversion circuit.
As shown in Figure 1, LDMOS device include well region 16, drain contact region 11, source area 12, grid 13, body area 14 and Body contact zone 15.Those of ordinary skill in the art should be understood that well region 16 is also referred to as drain-drift region.For to performance and cost The considerations of, present many applications require the smaller power device of encapsulation.Smaller power device in order to obtain, largely Research focuses on reducing the technique of drain region size, such as reduces surface field RESURF (Reduced Surface Field) And grade doping drain electrode (Graded Dope Drain) etc..And the technique for reducing source area is then focused in some research.Such as The source area 12 for including centrally located body contact zone 15 shown in Fig. 1, in source/body area and being distributed in body contact zone both sides, from And a region N+/P+/N+ is formed, source area can be reduced by reducing the region N+/P+/N+.But the minimum area of N+/P+/N+ is logical It often will receive the limitation of photomask apparatus performance.
Summary of the invention
The object of the present invention is to provide a kind of technique, which forms autoregistration in one of process masks, using interval Source area and body contact zone, substitution limited and can not be generated the photomask of smaller source/body area window by equipment performance Process.Therefore, present invention decreases the source areas of LDMOS device, and effectively reduce the cost of manufacture LDMOS device.
The embodiment of the present invention is intended to provide a kind of process flow for manufacturing LDMOS device, and wherein the LDMOS device is located at The well region with the first doping type in semiconductor substrate, comprising: thin grid oxide layer is formed on well region；The shape on thin grid oxide layer At polysilicon layer；Barrier layer is formed on the polysilicon layer, and the etching speed of the barrier layer is faster than the etching speed of thin grid oxide layer；It is logical The window for crossing the first mask layer on barrier layer, performs etching barrier layer and polysilicon layer；Pass through the first mask layer Window has the impurity of the second doping type to well region injection, forms body area；By the window of the first mask layer, infused to body area Enter the impurity with the first doping type, forms source layer；Interval is formed, is formed by polysilicon layer after the package etching of the interval The side wall of window inner side；It is formed by window by interval, source layer is performed etching to source layer and is threaded through, forms source electrode Area；It is formed by window by interval, there is the impurity of the second doping type to the injection of body area, form body contact zone；Pass through quarter Erosion removes interval and barrier layer；By the window of the second mask layer, polysilicon layer is performed etching, forms grid；And pass through The window of third mask layer has the impurity of the first doping type to well region injection, forms drain contact region.
The embodiment of the present invention is intended to describe a kind of method for manufacturing LDMOS device, comprising: passes through the polycrystalline on well region Silicon layer window forms body area and source layer in well region, and wherein body area has junction depth more deeper than source layer；In polysilicon layer window Side-walls on the inside of mouthful form interval；And window is formed by by interval, source layer is performed etching to source layer and is worn It is logical, the region immediately below interval is wherein located in source layer and is protected during source layer is etched, and is defined as The source area of LDMOS device.
The embodiment of the present invention is further intended to describe a kind of process flow for manufacturing LDMOS device, comprising: in semiconductor Well region is formed in substrate；Thin grid oxide layer is formed on well region；Polysilicon layer is formed on thin grid oxide layer；On the polysilicon layer by suitable Sequence sequentially forms grid sealant, silicon nitride layer and the first mask layer, wherein the first mask layer includes that at least one leads to nitridation The window of silicon surface；By the window of the first mask layer, silicon nitride layer, grid sealant and polysilicon layer are performed etching, Expose the window for corresponding to body area in well region；By body area window, to well region injecting p-type impurity, body area is formed in well region； By body area window, N-type impurity is injected to body area, forms source layer in body area, then removes the first mask layer；To polysilicon The side wall of layer window inner side is aoxidized；Interval is formed in the side-walls that polysilicon layer window inner side is oxidized；Pass through interval institute The window of formation, performs etching to source layer source layer and is threaded through, and forms the source area being located at immediately below interval；In Xiang Tiqu The region injecting p-type impurity being etched between source area forms body contact zone；By etching removing silicon nitride layer and Every；The second mask layer is formed on grid sealant, wherein the second mask layer has position-scheduled window；Pass through the second exposure mask The window of layer, performs etching grid sealant and polysilicon layer, forms grid, then removes the second mask layer；In grid and Third mask layer is formed on thin grid oxide layer, which includes the window that at least one corresponds to drain contact region；And By the window of third mask layer, N-type impurity is injected to well region, drain contact region is formed, then removes third mask layer.
Detailed description of the invention
In order to better understand the present invention, the embodiment of the present invention will be described according to the following drawings.These attached drawings Be only used for it is schematically illustrate, similar part have similar number designation.Attached drawing only shows the Partial Feature of device, and different Surely it is drawn on scale, the size and ratio of attached drawing may be inconsistent with actual size and ratio.
Fig. 1 shows the sectional view of existing LDMOS device；
Fig. 2 shows the process flow synoptic diagrams of existing manufacture LDMOS device；
Fig. 3 a-3i shows the processing procedure that manufacture according to an embodiment of the invention has the LDMOS device of small source area；
Fig. 4 shows according to an embodiment of the invention for manufacturing the technique stream of LDMOS device shown by Fig. 3 a-3i Journey synoptic diagram.
Specific embodiment
Specific embodiments of the present invention are described more fully below.It should be understood that these embodiments are served only for illustrating It is bright, it is not intended to restrict the invention.On the contrary, the present invention should cover substitution, modification and the modes such as equivalent, these modes may Within the spirit and scope defined in appended claims.In addition, in the following description, in order to provide to of the invention saturating Thorough understanding elaborates a large amount of specific details.It will be apparent, however, to one skilled in the art that: this need not be used A little specific details carry out the present invention.In other instances, in order to avoid obscuring the present invention, do not specifically describe well known circuit, Material or method.
The term in orientation, such as " left side " " right side " " inner " "outside" " preceding " " rear " "upper" are indicated in specification and claims "lower" " top " " bottom " " surface " " underface " etc., is served only for describing, be not meant to these relative positions be it is permanent not Become.It should be understood that terms above can be interchanged in appropriate circumstances, so that corresponding embodiment can be with It works normally in other directions.
Fig. 2 shows the process flow synoptic diagrams of existing manufacture LDMOS device.The prior art may include following step It is rapid: front end process, the formation of thin grid oxide layer, polysilicon layer deposit, gate regions process masks, polysilicon layer etching, mask layer remove, Polysilicon gate oxidation, the injection of body area, mask layer removal, the area N+ process masks, source/drain regions injection, is covered body area process masks Film layer removal, the injection of the area P+ process masks, body contact zone, mask layer removes and rear end process.Front end process can include: prepare just Beginning substrate forms n type buried layer, grown epitaxial layer and defines active area.In some applications, front end process further includes forming thick grid Oxygen layer.Rear end process can include: form source area electrode, form drain region electrode, form body contact zone electrode, form grid electricity Pole and distribution metal layer.Those of ordinary skill in the art should be known that process masks (such as " gate regions process masks "), mean Formed have several windows mask layer, these windows correspond to semiconductor substrate upper surface specific region.For example, body area Process masks are the following steps are included: form mask layer in the upper surface of semiconductor substrate；Develop to mask layer, exposes logical The window of Xiang Tiqu.Exposure mask may include photoresist.
As shown in Figure 2, body area, body contact zone and source/drain regions pass through traditional photomask and ion implantation technology shape At.Therefore, the window size in source/body area, i.e. the area N+/P+/N+ shown in Fig. 1 will obviously be by photomask equipment performance Limitation.
Fig. 3 a-3i shows the processing procedure that manufacture according to an embodiment of the invention has the LDMOS device of small source area.
Fig. 3 a shows semiconductor substrate 301.The semiconductor substrate 301 includes initial substrate 318, n type buried layer (NBL) 319, epitaxial layer 320 and well region 321, wherein well region 321 is also referred to as drain-drift region.Initial substrate 318 can be N-type, p-type Or intrinsic material；N type buried layer 319 can be substituted with other structures；Epitaxial layer 320 can be N-type, p-type or intrinsic half Conductor material.Well region 321 can be the high-pressure trap area being lightly doped.The LDMOS device is formed within well region 321.Semiconductor Substrate 301 is also possible to integrate other circuits, device or system.For example, in BCD (Bipolar-CMOS-DMOS) technique, it is bipolar Transistor npn npn (BJT, Bipolar Junction Transistor), CMOS complementary metal-oxide-semiconductor device (CMOS, Complementary Metal Oxide Semiconductor) etc. other a variety of devices can be integrated in together with LDMOS device In same substrate.In some embodiments, semiconductor substrate 301 may have other constructions, or without above-mentioned part area Domain.
In Fig. 3 a, thin grid oxide layer 302 is formed in the upper surface of semiconductor substrate 301.Then, polysilicon layer 303 passes through shallow lake Product is formed on thin grid oxide layer 302.In subsequent handling, which will be etched to the polysilicon of LDMOS device Grid.Next, carrying out oxidation operation or oxide deposition process in the upper surface of polysilicon layer 303, grid sealant 304 is formed A part.Then, silicon nitride layer 305 is formed on grid sealant 304 by deposit.Next, the first mask layer 306 It is formed on silicon nitride layer 305 by process masks.First mask layer 306 includes that at least one leads to silicon nitride layer 305 Window OP1, the window can be and dissolving specific region on the first mask layer 306 after being exposed to the first mask layer 306 It is formed.Window OP1 is also referred to as source/body area window or body area window.In one embodiment, the width d1 of window OP1 It is 0.3 micron to 0.5 micron.In some embodiments, the first mask layer 306 can use the other materials substitution except photoresist.
Thin grid oxide layer 302 is used as dielectric layer, and polysilicon layer 303 is used as the conductive layer of the grid of LDMOS device.This Field those of ordinary skill should be known that thin grid oxide layer 302 and polysilicon layer 303 can be substituted with other suitable materials.
In Fig. 3 b to Fig. 3 i, for clarity, initial substrate 318, n type buried layer 319 and epitaxial layer 320 are had been not shown.
In Fig. 3 b, silicon nitride layer 305, grid sealant 304 and polysilicon layer 303 under window OP1 are etched, thus cruelly Expose the region surface that source/body area is corresponded in the well region 321 being covered with by thin grid oxide layer 302.Next, p type impurity is logical It crosses window OP1 and is injected into well region 321, form body area 307.First mask layer 306 quilt after forming body area 307 and source layer 331 It removes.
In one embodiment, the first mask layer 306 is removed after forming body area 307.In this case, in N-type During impurity is injected into body area 307 to form source layer 331, polysilicon layer 303, grid sealant 304 and silicon nitride layer 305 are used as mask layer.
In one embodiment, annealing operation may be carried out after forming body area 307.In other embodiments, it moves back Firer's sequence may be carried out after forming body area 307 and source layer 331.
In Fig. 3 c, oxidation operation is carried out to form grid sealing side wall 303S, exposed more on the inside of window OP1 to wrap up The side wall of crystal silicon layer 303.Grid sealing side wall 303S constitutes a part of grid sealant 304.
In Fig. 3 d, silicon nitride spacer 308 is formed, to wrap up grid sealing side wall 303S.Silicon nitride spacer 308 defines source Position of the polar region in body area 307, i.e. region immediately below silicon nitride spacer 308.In addition, interval 308 yet forms window OP2, for defining body contact zone 332 in body area 307, window OP2 is also referred to as body contact zone window.
In one embodiment, the range of the thickness d 2 at each interval 308 gone out as shown in Figure 3d is 0.1 micron to 0.15 Micron.
In Fig. 3 e, the part that source layer 331 is located at immediately below window OP2 is etched to break-through, to form source area 311.The source area 311 is a part of source layer 331, guarantor during source layer 331 is etched by interval 308 Shield.Since the range of the thickness d 2 at each interval 308 is 0.1 micron to 0.15 micron, therefore the model of the width d3 of each source area Enclose also is 0.1 micron to 0.15 micron.In actual device, grid sealing side wall 303S is very thin, and thickness can be neglected Slightly.The process of etching source layer 331 should be guaranteed that source layer 331 is threaded through, but in practical applications, it is difficult control etching work Sequence is so that source layer 331 is just threaded through and does not destroy in body area 307 positioned at the underface in the region that is etched of source layer 331 Region.It is therefore preferred that body area 307 should have enough junction depths, guarantee is enough in the region that is etched of source layer 331 It is formed immediately below body contact zone 332.
In Fig. 3 f, p type impurity is injected into body area 307 by window OP2, forms body contact zone 332.In the process, nitrogen The mask layer similar with the effect at interval 308 of SiClx 305.Body contact zone 332 has than the higher doping concentration in body area 307.
In Fig. 3 g, interval 308 and silicon nitride layer 305 are etched removal.
In Fig. 3 h, the second mask layer 312 is formed on grid sealant 304 by process masks.Second mask layer 312 windows determined comprising position, for defining grid.Shape after polysilicon layer under the window of second mask layer 312 is etched At grid 322.Then, the second mask layer 312 is removed.Later, additional oxidation operation may be carried out complete to be formed Grid sealant 304.
In Fig. 3 i, third mask layer 313 is formed on grid 322 and thin grid oxide layer 302 by photo-mask process, the third Mask layer 313 includes the window OP3 that position determines, to define drain region 314.Third mask layer 313 can also be used to make simultaneously Make the N+ source area and drain region and other N+ layers of NMOS, such as emitter region and the collector region of npn bipolar transistor.N-type is miscellaneous Matter is injected into well region 321 by window OP3, forms drain contact region 314.Then, third mask layer 313 is removed.
Fig. 4 shows according to an embodiment of the invention for manufacturing the technique stream of LDMOS device shown by Fig. 3 a-3i Journey synoptic diagram.Compared to the prior art illustrated in fig. 2, polysilicon layer of the embodiment of the present invention in source/body area window inner side Side wall forms interval, to define source area.In some embodiments, the range of spacer thickness d2 is 0.1 micron micro- to 0.15 Rice.Therefore the range-controllable system of source region width is at 0.1 micron to 0.15 micron, much smaller than according to manufactured by prior art The width of LDMOS device source area.The present invention forms relatively narrow N+/P+/N+ source/body area using interval and selective etch, This is that traditional photomask equipment cannot achieve.
Those of ordinary skill in the art should be known that the doping type in each region can be replaced, such as N-doped zone can To be substituted with P-doped zone, P-doped zone is substituted with N-doped zone at the same time.In a reality as is described in the claims It applies in example, the first doping type is N-type and the second doping type is p-type.In another embodiment, the first doping type is P Type and the second doping type are N-type.
N-type impurity can select one in following substance: nitrogen, phosphorus, arsenic, antimony, bismuth and their combination.Meanwhile p type impurity can One is selected in following substance: boron, aluminium, gallium, indium, thallium and their combination.
According to above teaching, many changes of the invention and variant are obviously also feasible.It is therefore understood that It is that in claim limited range, the present invention can not have to implement according to above-mentioned specific description.It should equally manage Solution, it is disclosed above to relate only to some preferred embodiments of the invention, do not departing from essence defined by the claims in the present invention Under the premise of mind and range, change can be made to the present invention.When only one preferred embodiment is disclosed, the common skill in this field Art personnel are it is contemplated that retrofiting and being committed to implement, without departing from the spirit defined by the claims in the present invention and model It encloses.

Claims (7)

1. a kind of process flow for manufacturing LDMOS device, wherein the LDMOS device, which is located in semiconductor substrate, has first to mix The well region of miscellany type, comprising:
Thin grid oxide layer is formed on well region；
Polysilicon layer is formed on thin grid oxide layer；
Barrier layer is formed on the polysilicon layer, and the etching speed of the barrier layer is faster than the etching speed of thin grid oxide layer；
By the window of the first mask layer on barrier layer, barrier layer and polysilicon layer are performed etching；
By the window of the first mask layer, there is the impurity of the second doping type to well region injection, form body area；
By the window of the first mask layer, there is the impurity of the first doping type to the injection of body area, form source layer；
Interval is formed, the side wall of polysilicon layer window inner side is formed by after the package etching of the interval；
It is formed by window by interval, source layer is performed etching to source layer and is threaded through, forms source area；
It is formed by window by interval, there is the impurity of the second doping type to the injection of body area, form body contact zone；
Interval and barrier layer are removed by etching；
By the window of the second mask layer, polysilicon layer is performed etching, forms grid；And
By the window of third mask layer, there is the impurity of the first doping type to well region injection, form drain contact region.
2. as described in claim 1 manufacture LDMOS device process flow, among it every material and barrier layer material tool There is identical etching speed.
3. the process flow of manufacture LDMOS device as described in claim 1, among it every being nitridation with the material of barrier layer Silicon.
4. the process flow of manufacture LDMOS device as described in claim 1 further includes before forming interval, to polysilicon The side wall of layer window inner side is aoxidized.
5. the process flow of manufacture LDMOS device as described in claim 1, wherein the thickness range at each interval is 0.1 micro- Rice is to 0.15 micron.
6. the process flow of manufacture LDMOS device as described in claim 1, wherein the window width of the first mask layer is 0.3 Micron is to 0.5 micron.
7. a kind of process flow for manufacturing LDMOS device, comprising:
Well region is formed in semiconductor substrate；
Thin grid oxide layer is formed on well region；
Polysilicon layer is formed on thin grid oxide layer；
Grid sealant, silicon nitride layer and the first mask layer are sequentially formed in order on the polysilicon layer, wherein the first mask layer Lead to the window on silicon nitride layer surface including at least one；
By the window of the first mask layer, silicon nitride layer, grid sealant and polysilicon layer are performed etching, exposed in well region Window corresponding to body area；
By body area window, to well region injecting p-type impurity, body area is formed in well region；
By body area window, N-type impurity is injected to body area, forms source layer in body area, then removes the first mask layer；
The side wall of polysilicon layer window inner side is aoxidized；
Interval is formed in the side-walls that polysilicon layer window inner side is oxidized；
It is formed by window by interval, source layer is performed etching to source layer and is threaded through, is formed and is located at immediately below interval Source area；
The region injecting p-type impurity being etched in Xiang Tiqu between source area forms body contact zone；
Pass through etching removing silicon nitride layer and interval；
The second mask layer is formed on grid sealant, wherein the second mask layer has position-scheduled window；
By the window of the second mask layer, grid sealant and polysilicon layer are performed etching, grid is formed, then removes second Mask layer；
Third mask layer is formed on grid and thin grid oxide layer, which includes that at least one corresponds to drain contact region Window；And
By the window of third mask layer, N-type impurity is injected to well region, drain contact region is formed, then removes third mask layer.
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US10090409B2 (en) * 2016-09-28 2018-10-02 Monolithic Power Systems, Inc. Method for fabricating LDMOS with self-aligned body
CN111370314A (en) * 2020-04-30 2020-07-03 上海华虹宏力半导体制造有限公司 Method for manufacturing NLDMOS device by BCD process and device formed by method
US11069777B1 (en) 2020-06-09 2021-07-20 Monolithic Power Systems, Inc. Manufacturing method of self-aligned DMOS body pickup
US20220406601A1 (en) * 2021-06-16 2022-12-22 Monolithic Power Systems, Inc. Laser induced semiconductor wafer patterning
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102738215A (en) * 2011-08-18 2012-10-17 成都芯源系统有限公司 Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6252278B1 (en) 1998-05-18 2001-06-26 Monolithic Power Systems, Inc. Self-aligned lateral DMOS with spacer drift region
US6552389B2 (en) * 2000-12-14 2003-04-22 Kabushiki Kaisha Toshiba Offset-gate-type semiconductor device
US7301185B2 (en) * 2004-11-29 2007-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. High-voltage transistor device having an interlayer dielectric etch stop layer for preventing leakage and improving breakdown voltage
US9159795B2 (en) 2013-06-28 2015-10-13 Monolithic Power Systems, Inc. High side DMOS and the method for forming thereof
US9502251B1 (en) 2015-09-29 2016-11-22 Monolithic Power Systems, Inc. Method for fabricating low-cost isolated resurf LDMOS and associated BCD manufacturing process

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102738215A (en) * 2011-08-18 2012-10-17 成都芯源系统有限公司 Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof

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