CN106888173A - Universal efficient message communication system and its method - Google Patents
Universal efficient message communication system and its method Download PDFInfo
- Publication number
- CN106888173A CN106888173A CN201710093816.7A CN201710093816A CN106888173A CN 106888173 A CN106888173 A CN 106888173A CN 201710093816 A CN201710093816 A CN 201710093816A CN 106888173 A CN106888173 A CN 106888173A
- Authority
- CN
- China
- Prior art keywords
- data
- transmitter
- module
- register
- packet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/56—Queue scheduling implementing delay-aware scheduling
- H04L47/568—Calendar queues or timing rings
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9057—Arrangements for supporting packet reassembly or resequencing
Abstract
The invention discloses a kind of Universal efficient message communication system and its method, it is related to a kind of information communication mechanism.The system includes message communication system（A）With other mutually isostructural systems, it is interconnected each other；Message communication system（A）Including timer（00）, the 1st transmitter（10）, the 1st receiver（20）, data processor（30）, the 2nd transmitter（40）With the 2nd receiver（50）；Timer（00）Respectively with the 1st transmitter（10）With the 2nd transmitter（40）It is connected, the 1st transmitter（10）, the 1st receiver（20）, the 2nd transmitter（40）With the 2nd receiver（50）Respectively with data processor（30）It is connected.The present invention is capable of achieving a kind of highly versatile, the information communication mechanism of transmitting-receiving efficiency high, and the system is a kind of intercommunication system, can be as arbitrary network node for data forwarding in equipment, with the advantage such as portable strong, practical, robustness is good.
Description
Technical field
The present invention relates to a kind of information communication mechanism, more particularly to a kind of Universal efficient message communication system and its method；
Highly versatile of the present invention, efficiency of transmission are high and robustness is good.
Background technology
The control chips such as MCU or DSP drive PERCOM peripheral communication data-interface it is varied, can according to need transceiving data size,
The different demands such as speed select corresponding interface mode, such as SPI, GPIO, I2C etc..But distinct interface is called, it is necessary to change
DSP bottom layer drivings, all parameters of modification configuration.
And the message of the generally control chip such as MCU or DSP transmitting-receiving also has many message, various data in addition to business datum
Not of uniform size, some control information may only have several bit, and high-frequency opens driving interface on the contrary than transmission data in itself repeatedly
Transmission time is longer.
It can be seen that needing a kind of the good information communication mechanism of low-level details, efficiency high, highly versatile, robustness can be shielded.
The content of the invention
It is an object of the invention to provide the Universal efficient message communication system that a kind of communication efficiency is high, versatility is good and its
Method, the system is a kind of intercommunication system, can be used as arbitrary node transceiving data in network.
The object of the present invention is achieved like this：
First, Universal efficient message communication system
Including message communication system and other mutually isostructural systems, it is interconnected each other；
Message communication system includes that timer, the 1st transmitter, the 1st receiver, data processor, the 2nd transmitter and the 2nd are received
Device；
Its annexation is：
Timer is connected with the 1st transmitter and the 2nd transmitter respectively, and the 1st transmitter, the 1st receiver, the 2nd transmitter and the 2nd connect
Device is received to be connected with data processor respectively.
2nd, Universal efficient information communication method（Abbreviation method）
This method comprises the following steps：
1. the 1st receiver receives message to data processor；
2. decoder module judges whether to be destined to the data of oneself, if it is starts decoding, if not then issuing restructuring
Module；
3. recombination module will need the data-message of transmission to be sequentially placed into register, and register is N number of M byte size, M, N root
Depending on demand；
1. 2. 3. 4. repeat step, insert in register successively in order, and recombination module is read by the data that recombination module will be received
Take and be currently received size of data, if judging that current data amount adds register data storage amount no more than M byte, by number
According to being placed on behind canned data, from increasing 1, current data is stored in the register of next M byte otherwise idx；
5. scheduler module judges data storage, will all meet the full data packet portions of M byte and is given to forwarding module successively；
6. first packet is issued transmitter by current storage data by forwarding module in sequence；Record has currently sent
Packet, after being successfully transmitted a packet, idx subtracts 1 certainly, and subsequently completely M byte packet first address is moved forward into head；
7. timer sends instructions to send a packet in the 2nd transmitter transmitter register per 200ms, if during timer
Between it is unfilled to first M byte packet, still send；If timer has been arrived, register has been filled with multiple packets, only sends out
Send one；
2. 3. 4. 5. 6. 8. 1. the 2nd receiver carries out the 1st receiver identical step operation simultaneously, and 8. middle timer is every for step
200ms sends instruction to corresponding 1st transmitter, and doing same steps operation can carry out the data transfer of opposite direction.
The present invention has following advantages and good effect：
1. highly versatile：MCU or DSP driving interfaces are varied, according to the selection of the different demands such as transceiving data size, speed not
Same mode, the maskable bottom layer driving of the method, with different devices when need to only be modified slightly.
2. message efficiency high is forwarded：Usual MCU or DSP messagings also have many message in addition to business datum, various
Size of data differs, and some control information may only have several bit, and high-frequency opens driving interface on the contrary than transmission data repeatedly
Transmission time itself is longer.Different pieces of information is stored in register by the method by appropriate coding and decoding, and timing sends, and improves effect
Rate.
In a word, the present invention is capable of achieving a kind of highly versatile, the information communication mechanism of transmitting-receiving efficiency high, and the system is a kind of double
To communication system, can be good with portable strong, practical, robustness as arbitrary network node for data forwarding in equipment
Etc. advantage.
Brief description of the drawings
Fig. 1 is the block diagram of the system；
In figure：
A-message communication system, B-left message communication system, C-right message communication system；
00-timer；
10-the 1 transmitter；
20-the 1 receiver；
30-data processor；
31-forwarding module, 32-scheduler module, 33-recombination module, 34-decoder module；
40-the 2 transmitter；
50-the 2 receiver.
English to Chinese
1、DSP：Digital Signal Processing, Digital Signal Processing；
2、SPI：Serial Peripheral Interface, Serial Peripheral Interface (SPI)；
3、GPIO：General Purpose Input/Output, universal input output control line；
4、I2C：Inter-integrated Circuit, internal integrated circuit.
Specific embodiment
Described in detail below in conjunction with drawings and Examples.
First, system
1st, it is overall
Such as Fig. 1, the system includes message communication system A and other mutually isostructural systems（Such as left and right message communication system B,
C）, it is interconnected each other；
Message communication system A includes timer 00, the 1st transmitter 10, the 1st receiver 20, data processor 30, the 2nd transmitter
40 and the 2nd receiver 50；
Its annexation is：
Timer 00 is connected with the 1st transmitter 10 and the 2nd transmitter 40 respectively, and the 1st transmitter 10, the 1st receiver the 20, the 2nd are sent out
The receiver 50 of emitter 40 and the 2nd is connected with data processor 30 respectively.
Working mechanism：
The system is an intercommunication system, after the 1st receiver 20 receives message（Such as other dsp or dsp cores）Pass through
Data processor 30 is again gone out the data transfer after treatment by the 2nd transmitter 40；In the same manner, transmitted from another direction
Data by the 2nd receiver 50 receive message, passed by the 1st transmitter 10 again by data processor 30.
2nd, functional part
0）Timer 50
Its hardware configuration：Dsp chip TMS320C6416.
Its software design patterns：Transmitter is sent instructions to per 200ms, a packet is sent in transmitter register.
1）1st transmitter 10
Its hardware configuration：Dsp chip TMS320C6416.
Its software design patterns：Receive the data sent of forwarding module 31 and timing is transmitted to other DSP.
2）1st receiver 20
Its hardware configuration：Dsp chip TMS320C6416.
Its software design patterns：Receive data that other messaging systems send and be given to data processor 30.
3）Data processor 30
Its hardware configuration：Dsp chip TMS320C6416.
Its software design patterns：Embedded module includes the forwarding module 31, scheduler module 32, the and of recombination module 33 that interact
Coding module 34.
（1）Forwarding module 31：First packet is issued transmitter by current storage data in sequence, and record is current
Packet is sent；
（2）Scheduler module 32：The data that 256 bytes will have been met are given to forwarding module 31 successively；
（3）Recombination module 33：The data-message of transmission will be needed to be sequentially placed into register；Judgement is currently received size of data, such as
Data storage is more than 256 bytes to fruit with register, then from increasing 1, current data is put into next 256 byte to idx；
（4）Decoder module 34：Decoder module 34 judges whether it is that other dsp or other cores are sent to the data of oneself, if
Then start decoding, if not then issuing recombination module 33.
4）2nd transmitter 40
With the 1st transmitter 10.
5）2nd receiver 50
With the 1st receiver 20.
2nd, method
1st, described decoder module（34）Idiographic flow be：
Judgement receives whether message is destined to the data of oneself, if it is starts decoding, if not then issuing restructuring mould
Block（33）.
2nd, described recombination module（33）Idiographic flow be：
Repeat step 1. 2. 3., recombination module（33）The data that will be received are inserted in register successively in order, and recombination module
Reading is currently received size of data, if judging that current data amount adds register data storage amount no more than M byte, will
Data are placed on behind canned data, and from increasing 1, current data is stored in the register of next M byte otherwise idx
The idiographic flow of the 3rd, described timing forwarding packet is：
Forwarding module（31）1st packet is issued into transmitter, timer by current storage data in sequence（00）Often
200ms sends instructions to send a packet in transmitter transmitter register, if timer time is to first packet
It is unfilled, still send；If timer（00）It has been arrived that, register has been filled with multiple packets, only sent one.
Claims (6)
1. a kind of Universal efficient message communication system, it is characterised in that：
Including message communication system（A）With other mutually isostructural systems, it is interconnected each other；
Message communication system（A）Including timer（00）, the 1st transmitter（10）, the 1st receiver（20）, data processor（30）、
2nd transmitter（40）With the 2nd receiver（50）；
Its annexation is：
Timer（00）Respectively with the 1st transmitter（10）With the 2nd transmitter（40）It is connected, the 1st transmitter（10）, the 1st receiver
（20）, the 2nd transmitter（40）With the 2nd receiver（50）Respectively with data processor（30）It is connected.
2. the Universal efficient message communication system as described in claim 1, it is characterised in that：
Described data processor（30）Embedded module includes the forwarding module for interacting（31）, scheduler module（32）、
Recombination module（33）And coding module（34）；
Forwarding module（31）：First packet is issued transmitter by current storage data in sequence, and record has currently been sent out
Send packet；
Scheduler module（32）：The data that 256 bytes will have been met are given to forwarding module 31 successively；
Recombination module（33）：The data-message of transmission will be needed to be sequentially placed into register；Judgement is currently received size of data, if
Data storage is more than 256 bytes with register, then from increasing 1, current data is put into next 256 byte to idx；
Decoder module（34）：Decoder module 34 judges whether it is that other dsp or other cores are sent to the data of oneself, if it is
Start decoding, if not then issuing recombination module 33.
3. the communication means of Universal efficient message communication system described in claim 1-2 is based on, it is characterised in that：
1. the 1st receiver receives message to data processor；
2. decoder module judges whether to be destined to the data of oneself, if it is starts decoding, if not then issuing restructuring
Module；
3. recombination module will need the data-message of transmission to be sequentially placed into register, and register is N number of M byte size, M, N root
Depending on demand；
1. 2. 3. 4. repeat step, insert in register successively in order, and recombination module is read by the data that recombination module will be received
Take and be currently received size of data, if judging that current data amount adds register data storage amount no more than M byte, by number
According to being placed on behind canned data, from increasing 1, current data is stored in the register of next M byte otherwise idx；
5. scheduler module judges data storage, will all meet the full data packet portions of M byte and is given to forwarding module successively；
6. first packet is issued transmitter by current storage data by forwarding module in sequence；Record has currently sent
Packet, after being successfully transmitted a packet, idx subtracts 1 certainly, and subsequently completely M byte packet first address is moved forward into head；
7. timer sends instructions to send a packet in the 2nd transmitter transmitter register per 200ms, if during timer
Between it is unfilled to first M byte packet, still send；If timer has been arrived, register has been filled with multiple packets, only sends out
Send one；
2. 3. 4. 5. 6. 8. 1. the 2nd receiver carries out the 1st receiver identical step operation simultaneously, and 8. middle timer is every for step
200ms sends instruction to corresponding 1st transmitter, and doing same steps operation can carry out the data transfer of opposite direction.
4. the communication means as described in claim 3, it is characterised in that：
Described decoder module（34）Idiographic flow be：
Judgement receives whether message is destined to the data of oneself, if it is starts decoding, if not then issuing restructuring mould
Block（33）.
5. the communication means as described in claim 3, it is characterised in that：
Described recombination module（33）Idiographic flow be：
Repeat step 1. 2. 3., recombination module（33）The data that will be received are inserted in register successively in order, and recombination module
Reading is currently received size of data, if judging that current data amount adds register data storage amount no more than M byte, will
Data are placed on behind canned data, and from increasing 1, current data is stored in the register of next M byte otherwise idx.
6. the communication means as described in claim 3, it is characterised in that：
The idiographic flow of described timing forwarding packet is：
Forwarding module（31）1st packet is issued into transmitter, timer by current storage data in sequence（00）Often
200ms sends instructions to send a packet in transmitter transmitter register, if timer time is to first packet
It is unfilled, still send；If timer（00）It has been arrived that, register has been filled with multiple packets, only sent one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710093816.7A CN106888173B (en) | 2017-02-21 | 2017-02-21 | Universal efficient message communication system and its method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710093816.7A CN106888173B (en) | 2017-02-21 | 2017-02-21 | Universal efficient message communication system and its method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106888173A true CN106888173A (en) | 2017-06-23 |
| CN106888173B CN106888173B (en) | 2019-11-29 |
Family
ID=59179253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710093816.7A Active CN106888173B (en) | 2017-02-21 | 2017-02-21 | Universal efficient message communication system and its method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106888173B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1770730A (en) * | 2004-11-01 | 2006-05-10 | 华为技术有限公司 | High-speed message transmitting method with high reliability |
| CN1917478A (en) * | 2006-09-14 | 2007-02-21 | 杭州华为三康技术有限公司 | Method for processing forwarding message, and process module |
| CN1925453A (en) * | 2006-10-12 | 2007-03-07 | 杭州华为三康技术有限公司 | Message transferring method and device |
| CN102823207A (en) * | 2012-05-18 | 2012-12-12 | 华为技术有限公司 | Method and device for forwarding data packet |
| US20140258367A1 (en) * | 2013-03-05 | 2014-09-11 | Qualcomm Incorporated | Renewing registrations for a plurality of client applications that are associated with the same host server via an implicit piggybacking scheme |
| CN105933139A (en) * | 2016-03-30 | 2016-09-07 | 广东凯通软件开发有限公司 | Data processing method and device |
-
2017
- 2017-02-21 CN CN201710093816.7A patent/CN106888173B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1770730A (en) * | 2004-11-01 | 2006-05-10 | 华为技术有限公司 | High-speed message transmitting method with high reliability |
| CN1917478A (en) * | 2006-09-14 | 2007-02-21 | 杭州华为三康技术有限公司 | Method for processing forwarding message, and process module |
| CN1925453A (en) * | 2006-10-12 | 2007-03-07 | 杭州华为三康技术有限公司 | Message transferring method and device |
| CN102823207A (en) * | 2012-05-18 | 2012-12-12 | 华为技术有限公司 | Method and device for forwarding data packet |
| US20140258367A1 (en) * | 2013-03-05 | 2014-09-11 | Qualcomm Incorporated | Renewing registrations for a plurality of client applications that are associated with the same host server via an implicit piggybacking scheme |
| CN105933139A (en) * | 2016-03-30 | 2016-09-07 | 广东凯通软件开发有限公司 | Data processing method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106888173B (en) | 2019-11-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2124452C (en) | Method and apparatus for processing data within stations of a communication network | |
| US6526446B1 (en) | Hardware only transmission control protocol segmentation for a high performance network interface card | |
| US4631666A (en) | Data transfer network for variable protocol management | |
| EP0459753A2 (en) | Network access controller having logical FIFO buffer | |
| CN110086571A (en) | A kind of data transmission and received method, apparatus and data processing system | |
| US10579581B2 (en) | Multilane heterogeneous serial bus | |
| JPH0795767B2 (en) | Optimized method of data communication and system using the method | |
| CN106598889A (en) | SATA (Serial Advanced Technology Attachment) master controller based on FPGA (Field Programmable Gate Array) sandwich plate | |
| CN110380992A (en) | Message processing method, device and network flow acquire equipment | |
| CN101122894A (en) | Asynchronous serial communication control device | |
| US6496487B2 (en) | Efficient full duplex simultaneous message transfer | |
| CN106533976A (en) | Data packet processing method and device | |
| CN110838892B (en) | High-reliability merging and forwarding method for multi-path full-duplex serial port | |
| CN101212480B (en) | Method and apparatus for communication between universal serial bus (USB) host and USB device | |
| CN106888173A (en) | Universal efficient message communication system and its method | |
| CN107846709B (en) | Wireless communication device and wireless communication method based on LoRa | |
| CN111045817A (en) | PCIe transmission management method, system and device | |
| US7010579B1 (en) | Direct data routing system | |
| US7353448B1 (en) | Methods, architectures, circuits and systems for transmission error determination | |
| CN113051212B (en) | Graphics processor, data transmission method, data transmission device, electronic equipment and storage medium | |
| EP1525722B1 (en) | Packet signal processing architecture | |
| CN1347062A (en) | Gigabit IP network card | |
| Iliopoulos et al. | Reconfigurable network processors based on field programmable system level integrated circuits | |
| CN1950810A (en) | Backward-compatible parallel DDR bus for use in host-daughtercard interface | |
| CN110865955B (en) | High-reliability merging and forwarding system of multi-path full-duplex serial port |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |