CN106865484A - Array base palte and preparation method thereof, display device - Google Patents
Array base palte and preparation method thereof, display device Download PDFInfo
- Publication number
- CN106865484A CN106865484A CN201710065876.8A CN201710065876A CN106865484A CN 106865484 A CN106865484 A CN 106865484A CN 201710065876 A CN201710065876 A CN 201710065876A CN 106865484 A CN106865484 A CN 106865484A
- Authority
- CN
- China
- Prior art keywords
- source electrode
- electrode
- grid
- substrate
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
- B81B3/0018—Structures acting upon the moving or flexible element for transforming energy into mechanical movement or vice versa, i.e. actuators, sensors, generators
- B81B3/0021—Transducers for transforming electrical into mechanical energy or vice versa
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
- B81C1/0015—Cantilevers
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/01—Switches
- B81B2201/012—Switches characterised by the shape
- B81B2201/014—Switches characterised by the shape having a cantilever fixed on one side connected to one or more dimples
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention provides a kind of array base palte, including：Substrate, insulating barrier, micro electromechanical system switch and pixel electrode；The micro electromechanical system switch includes：Grid, source electrode and drain electrode；The grid is arranged on the first surface of the substrate；The insulating barrier is arranged on the first surface of the substrate, and covers the grid；The source electrode, the drain electrode and the pixel electrode are arranged on the first surface of the insulating barrier；The drain electrode and pixel electrode connection；Wherein, in the state of the non-on-load voltage of the grid, there is gap between the source electrode and the drain electrode；In the state of the grid on-load voltage, the source electrode and the drain contact.The present invention also provides the preparation method and display device of a kind of array base palte.Array base palte of the invention has gap in the state of the non-on-load voltage of grid between source electrode and drain electrode, will not produce leakage current.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of array base palte and preparation method thereof, display device.
Background technology
Existing mobile product, in order to realize reducing the purpose of power consumption, leads to power consumption and the requirement more and more higher of display effect
Crossing low frequency driving can effectively reduce power consumption；In order to realize being lifted the purpose of display effect, can effectively be solved by high-frequency drive
The certainly smear problem of picture.If taking into account low-power consumption and high image quality on mobile product, display device is needed while supporting low frequency
Drive and high-frequency drive.
At present, TFT (thin film transistor (TFT), Thin Film Transistor) display device uses TFT switch, its source electrode and
Drain electrode is connected by channel layer, and (Low Temperature Poly-silicon, low temperature is more using a-Si, LTPS for the channel layer
Crystal silicon technology) and three kinds of materials of Oxide (oxide), opening for a-Si, LTPS and Oxide backplane technology control pixel is respectively adopted
Close.Wherein a-Si technologies can not support high-frequency drive；LTPS can meet the charge requirement of high-frequency drive, but 100cm/m2Move
Shifting rate can not meet the charge requirement of higher frequency, simultaneously as source electrode and drain electrode are connected by channel layer, leakage current is serious, no
Can low frequency driving be carried out to reduce power consumption；Oxide can support high-frequency drive, while low frequency driving can be supported, but because source electrode
Connected by channel layer with drain electrode, it is impossible to be fully solved current leakage, the frequency of low frequency driving can not be reduced further.Cause
This, the pixel switch of the display device of prior art cannot preferably solve the problems, such as leakage current.
The content of the invention
The embodiment of the present invention provides a kind of array base palte and preparation method thereof, display device, to solve the aobvious of prior art
There is leakage current in the array base palte of showing device.
In a first aspect, technical scheme provides a kind of array base palte, including：Substrate, insulating barrier, microelectron-mechanical
System switching and pixel electrode；The micro electromechanical system switch includes：Grid, source electrode and drain electrode；The grid is arranged on
On the first surface of the substrate；The insulating barrier is arranged on the first surface of the substrate, and covers the grid；It is described
Source electrode, the drain electrode and the pixel electrode are arranged on the first surface of the insulating barrier；The drain electrode and the pixel
Electrode contact；Wherein, in the state of the non-on-load voltage of the grid, there is gap between the source electrode and the drain electrode；
In the state of the grid on-load voltage, the source electrode and the drain contact.
Further：The source electrode includes the hanging Part I source electrode and Part II source electrode for setting；The Part I
There is overlapping region in the orthographic projection of the substrate in source electrode and the grid；The Part II source electrode is vacantly located at the drain electrode
First surface on, the Part II source electrode and the drain electrode is there is overlapping region in the orthographic projection of the substrate.
Further：The source electrode is spaced in orthographic projection and the pixel electrode of the substrate in the orthographic projection of the substrate
First distance.
Further：The source electrode and the material of the drain electrode are conductive metal material or semiconductor conductive material.
Second aspect, technical scheme provides a kind of preparation method of array base palte, including：The first of substrate
Grid is made on surface；Insulating barrier is formed on the first surface of the substrate, the insulating barrier is covered the grid；Institute
State and drain electrode and pixel electrode are made on the first surface of insulating barrier, contact the drain electrode and the pixel electrode；Described exhausted
Sacrifice layer is made on the first surface of edge layer and the first surface of the drain electrode；In the first surface of the insulating barrier and described sacrificial
Source electrode is made on the first surface of domestic animal layer, the grid, the source electrode and the drain electrode is formed micro electromechanical system switch；
The sacrifice layer is removed, the array base palte is obtained；Wherein, in the state of the non-on-load voltage of the grid, the source electrode and
There is gap between the drain electrode；In the state of the grid on-load voltage, the source electrode and the drain contact.
Further, it is described on the first surface of the insulating barrier make source electrode the step of, including：In the first sacrifice layer
Part I source electrode is made on first surface, the Part I source electrode and the grid is existed in the orthographic projection of the substrate
Overlapping region；Wherein, first sacrifice layer is located on the first surface of the insulating barrier；In the first surface of the second sacrifice layer
Upper making Part II source electrode, makes the Part II source electrode and the drain electrode there is overlay region in the orthographic projection of the substrate
Domain, wherein, second sacrifice layer is located on the first surface of the drain electrode；Wherein, the source electrode includes the Part I
Source electrode and the Part II source electrode.
Further, it is described on the first surface of the insulating barrier make source electrode the step of, including：By the source electrode and institute
State pixel electrode interval setting, make the source electrode the substrate orthographic projection and the pixel electrode the substrate positive throwing
Shadow is spaced the first distance.
Further：The source electrode and the material of the drain electrode are conductive metal material or semiconductor conductive material.
Further, the sacrificial layer material includes：Phosphoric acid glass, silica, polysilicon or porous silicon.
The third aspect, technical scheme provides a kind of display device, including above-mentioned array base palte.
So, in the embodiment of the present invention, by setting micro electromechanical system switch so that in the non-on-load voltage of grid
Under state, there is gap between source electrode and drain electrode, thus leakage current will not be produced；And in the state of grid on-load voltage, grid
Pole can attract the source electrode to make source electrode and drain contact so that circuit turn-on, the display device for being provided with the array base palte can show
Image.
Brief description of the drawings
Technical scheme in order to illustrate more clearly the embodiments of the present invention, below by institute in the description to the embodiment of the present invention
The accompanying drawing for needing to use is briefly described, it should be apparent that, drawings in the following description are only some implementations of the invention
Example, for those of ordinary skill in the art, without having to pay creative labor, can also be according to these accompanying drawings
Obtain other accompanying drawings.
Fig. 1 is the structural representation of the array base palte of the embodiment of the present invention；
Fig. 2 is the flow chart of the preparation method of the array base palte of the embodiment of the present invention；
Fig. 3 is the structural representation of the array base palte after the covering insulating barrier of the embodiment of the present invention；
Fig. 4 is the structural representation for making the array base palte after drain electrode and pixel electrode of the embodiment of the present invention；
Fig. 5 is the structural representation for making the array base palte after sacrifice layer of the embodiment of the present invention；
Fig. 6 is the structural representation for making the array base palte after source electrode of the embodiment of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is a part of embodiment of the invention, rather than whole embodiments.Based on this hair
Embodiment in bright, the acquired every other implementation under the premise of creative work is not made of those of ordinary skill in the art
Example, belongs to the scope of protection of the invention.
The embodiment of the invention discloses a kind of array base palte.As shown in figure 1, the array base palte includes：Substrate 101, insulation
Layer 102, micro electromechanical system switch and pixel electrode 103.
Wherein, micro electromechanical system switch includes：Grid 104, source electrode 105 and drain electrode 106.Grid 104 is arranged on base
On the first surface at bottom 101.Preferably, substrate 101 can be substrate of glass, or polymeric transparent substrate, such as PI,
PET etc..The material of the grid 104 can be conductive metal material or semiconductor conductive material.Insulating barrier 102 is arranged on substrate
On 101 first surface, and grid 104 is covered, so as to grid 104 and source electrode 105 can be isolated, it is to avoid both short circuits cause danger
Danger.Source electrode 105, drain electrode 106 and pixel electrode 103 are arranged on the first surface of insulating barrier 102.Drain electrode 106 and pixel electricity
Pole 103 contacts, so that can be when circuit turn-on for pixel is powered.Preferably, the pixel electrode 103 can use ITO, metal
Deng material.
In the state of the non-on-load voltage of grid 104, there is gap between source electrode 105 and drain electrode 106.Should in the present embodiment
Both channel layer connections without prior art between source electrode 105 and drain electrode 106, therefore, will not be produced when ultralow frequency drives
Raw leakage current.In the state of the on-load voltage of grid 104, source electrode 105 can be attracted to be moved to grid 104, so that the He of source electrode 105
Drain electrode 106 is contacted, and makes circuit turn-on.
Therefore, by setting micro electromechanical system switch, the array base palte can be made when ultralow frequency drives, source electrode 105
Leakage current will not be produced and drain electrode 106 between, it is to avoid damage array base palte.
In a preferred embodiment, source electrode 105 includes the hanging Part I source electrode 1051 for setting and Part II source
Pole 1052.Hanging setting in the present invention refers to Part I source electrode 1051 and is separated with interval, and second with insulating barrier 102
Source electrode 1052 and drain electrode 106 is divided to be separated with interval.Therefore, the Part I source electrode 105 and Part II source electrode of the hanging setting
1052 ensure that between source electrode 105 and drain electrode 106 be in structure with gap.Part I source electrode 1051 and grid 104 exist
There is overlapping region in the orthographic projection of substrate 101, so that in the state of the on-load voltage of grid 104, grid 104 can attract
A part of source electrode 1051 is moved to the direction of grid 104.Part II source electrode 1052 is vacantly located on the first surface of drain electrode 106,
Part II source electrode 1052 and drain electrode 106 is set to there is overlapping region in the orthographic projection of substrate 101, so as in Part I source electrode
1051 to the direction of grid 104 when being moved, and Part II source electrode 1052 can be driven to be moved to drain electrode 106, makes Part II source electrode
1052 contact with drain electrode 106, turning circuit.
In a preferred embodiment, source electrode 105 substrate 101 orthographic projection and pixel electrode 103 in substrate 101 just
The distance of projection interval first.First distance can be set according to the actual requirements, as long as ensureing that source electrode 105 will not be with pixel electrode
103 contacts.Therefore, above-mentioned structure design, it can be ensured that source electrode 105 is contacted under the attraction of grid 104 with drain electrode 106
When, will not be contacted with pixel electrode 103, cause danger.
In a preferred embodiment, source electrode 105 is conductive metal material with the material of drain electrode 106 or semiconductor is led
Electric material.Either conductive metal material or semiconductor conductive material, are all conductance conductive material higher, electron transfer
Rate is high.This material can meet the power demands of hyperfrequency driving.It is furthermore preferred that the conductive metal material can be aluminium, copper or
Person's gold etc..The semiconductor conductive material can be silicon.Therefore, by selecting source electrode 105 and the drain electrode 106 of above-mentioned material, the battle array
Row substrate can simultaneously meet the requirement that ultralow frequency drives and hyperfrequency drives.
To sum up, the array base palte of the embodiment of the present invention, due to being provided with micro electromechanical system switch, can make the array base
Plate will not produce leakage current when ultralow frequency drives between source electrode 105 and drain electrode 106, it is to avoid damage array base palte；Additionally, by
Conductance material high is employed in source electrode 105 and drain electrode 106, the array base palte can also simultaneously meet wanting for hyperfrequency driving
Ask.
The embodiment of the present invention additionally provides a kind of preparation method of array base palte.As shown in Fig. 2 the method is including following
Step：
Step S201：Grid is made on the first surface of substrate.
Specifically, the step can make grid by photoetching process on the first surface of substrate.The photoetching process is specific
For：Light shield layer is made on the figure needed for grid, the photoresist of non-lightproof area is inactivated by exposure, then by etching liquid
Unprotected material etch is fallen, the grid needed for being formed.In the step, the material of substrate may be selected glass or transparent polymeric
Thing, the material of grid may be selected conductive metal material or semiconductor conductive material.Thus, can select acidity etching liquid.Specifically
, the acid etching liquid can be phosphoric acid, nitric acid, acetic acid etc..
Step S202：Insulating barrier is formed on the first surface of substrate, insulating barrier is covered grid.
By the step, insulating barrier can be made to cover grid, so as to grid and source electrode can be isolated, it is to avoid both cause in short circuit
It is dangerous.
As shown in figure 3, being the structural representation of the array base palte after covering insulating barrier.Grid 104 is located at the of substrate 101
On one surface, insulating barrier 102 is completely covered grid 104.
Step S203：Drain electrode and pixel electrode are made on the first surface of insulating barrier, drain electrode and pixel electrode is contacted.
Specifically, the step can make drain electrode and pixel electrode by photoetching process on the first surface of substrate.The light
The detailed process of carving technology is identical with step S201, will not be repeated here.In the step, the material of drain electrode may be selected metallic conduction
Material or semiconductor conductive material, thus, can be using the acid etching liquid such as phosphoric acid, nitric acid, acetic acid.The material of the drain electrode can expire
The power demands that sufficient hyperfrequency drives, so that the array base palte that can obtain making drives and hyperfrequency drive while meeting ultralow frequency
Dynamic requirement.The material of pixel electrode, may be selected the materials such as ITO, metal, thus, can be using the acid etching such as hydrochloric acid, nitric acid
Liquid.
As shown in figure 4, the structural representation to make the array base palte after drain electrode and pixel electrode.The drain electrode 106 and picture
Plain electrode 103 is located on the first surface of insulating barrier 102.
Step S204：Sacrifice layer is made on the first surface of insulating barrier and the first surface of drain electrode.
Specifically, sacrificial layer material first can be deposited on the step first surface of insulating barrier and the first surface of drain electrode
On, required sacrifice layer is then obtained by photoetching process.The detailed process of the photoetching process is identical with step S201, herein not
Repeat again.The sacrificial layer material can be phosphoric acid glass, silica, polysilicon, porous silicon etc..By using the sacrifice layer material
Material, when source electrode is made, will not destroy sacrificial layer material, so as to can be isolated source electrode and drain electrode by sacrifice layer.In the step,
For different sacrificial layer materials, different etching liquids need to be used, it is specific as follows：If sacrificial layer material is phosphoric acid glass or two
Silica, then etching liquid is hydrofluoric acid；If sacrificial layer material is polysilicon or porous silicon, etching liquid is KOH solution.
Preferably, in order to avoid being contacted with pixel electrode with latter made source electrode, can also be in the first surface of pixel electrode
Upper making sacrifice layer.
As shown in figure 5, the structural representation to make the array base palte after sacrifice layer.The sacrifice layer 107 is located at insulating barrier
On the first surface of 102 first surface, the first surface of drain electrode 104 and pixel electrode 103.
Step S205：Make source electrode on the first surface of insulating barrier and the first surface of sacrifice layer, make grid, source electrode and
Drain electrode forms micro electromechanical system switch.
Specifically, the step can be made by photoetching process on the first surface of insulating barrier and the first surface of sacrifice layer
Source electrode.The detailed process of the photoetching process is identical with step S201, will not be repeated here.In the step, source electrode material may be selected
Conductive metal material or semiconductor conductive material, thus, can be using the acid etching liquid such as phosphoric acid, nitric acid, acetic acid.The source electrode material
Material can meet the power demands of hyperfrequency driving, so that the array base palte that can obtain making drives and super while meeting ultralow frequency
The requirement of high-frequency drive.By above-mentioned step, after subsequent step removal sacrifice layer, can make to be located at the first surface of sacrifice layer
On source electrode vacantly set.
As shown in fig. 6, the structural representation to make the array base palte after source electrode.The source electrode 105 is located at insulating barrier 102
On the first surface of first surface and sacrifice layer 107.
Step S206：Removal sacrifice layer, obtains array base palte.
The step specifically can remove sacrifice layer by the method corroded, and obtain array base palte as shown in Figure 1.
The array base palte made by the above method, in the state of the non-on-load voltage of grid, is had between source electrode and drain electrode
There is gap, both channel layer connections without prior art between the source electrode and drain electrode, therefore, will not when ultralow frequency drives
Produce leakage current；In the state of grid on-load voltage, source electrode can be attracted, make source electrode and drain contact, so as to can lead circuit
It is logical.
Preferably, the micro electromechanical system switch of the array base palte is obtained to make, step S205 specifically may include
The steps：
The first step：Part I source electrode is made on the first surface of the first sacrifice layer.
As shown in fig. 6, making Part I source electrode 1051 and grid 104 exist in the orthographic projection of substrate 101 by the step
Overlapping region.Wherein, the first sacrifice layer is located on the first surface of insulating barrier 101.
Second step, makes Part II source electrode on the first surface of the second sacrifice layer.
As shown in fig. 6, making Part II source electrode 1052 and drain electrode 106 exist in the orthographic projection of substrate 101 by the step
Overlapping region.Wherein, the second sacrifice layer is located on the first surface of drain electrode 106.
As shown in fig. 6, source electrode 105 includes above-mentioned Part I source electrode 1051 and Part II source electrode 1052.
The structure obtained by above-mentioned specific steps, may be such that in the state of grid on-load voltage, grid can attract
Part I source electrode to grid direction move so that can drive Part II source electrode to drain electrode move, make Part II source electrode with
Drain contact, turning circuit.
Preferably, step S205 also includes：
By source electrode and pixel electrode interval setting.
As shown in fig. 6, by the specific step, making source electrode 105 exist with pixel electrode 103 in the orthographic projection of substrate 101
The orthographic projection of substrate 101 is spaced the first distance, it can be ensured that when source electrode 105 is contacted under the attraction of grid 104 with drain electrode 106, no
Can be contacted with pixel electrode 103, cause danger.
To sum up, the preparation method of the array base palte of the embodiment of the present invention is simple, and the battle array for obtaining is made by the preparation method
Row substrate, due to being provided with micro electromechanical system switch, can make the array base palte when ultralow frequency drives, source electrode and drain electrode
Between will not produce leakage current, it is to avoid damage array base palte；Further, since source electrode and drain electrode employ conductance material high, should
Array base palte can also simultaneously meet the requirement of hyperfrequency driving.
The embodiment of the present invention additionally provides a kind of display device.The display device includes above-mentioned array base palte.The array
The structure of substrate will not be repeated here.
The display device due to above-mentioned array base palte, therefore, it can when ultralow frequency drives, source electrode and drain electrode
Between will not produce leakage current, it is to avoid damage display device；Further, since source electrode and drain electrode employ conductance material high, also
The requirement of hyperfrequency driving can simultaneously be met.
The above, specific embodiment only of the invention, but protection scope of the present invention is not limited thereto, and it is any
Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, should all contain
Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be defined by scope of the claims.
Claims (10)
1. a kind of array base palte, it is characterised in that including：Substrate, insulating barrier, micro electromechanical system switch and pixel electrode；
The micro electromechanical system switch includes：Grid, source electrode and drain electrode；The grid is arranged on the first surface of the substrate
On；The insulating barrier is arranged on the first surface of the substrate, and covers the grid；The source electrode, the drain electrode and institute
Pixel electrode is stated to be arranged on the first surface of the insulating barrier；The drain electrode and pixel electrode contact；
Wherein, in the state of the non-on-load voltage of the grid, there is gap between the source electrode and the drain electrode；In the grid
In the state of the on-load voltage of pole, the source electrode and the drain contact.
2. array base palte according to claim 1, it is characterised in that：The source electrode includes the hanging Part I source for setting
Pole and Part II source electrode；
There is overlapping region in the orthographic projection of the substrate in the Part I source electrode and the grid；
The Part II source electrode vacantly on the first surface of the drain electrode, makes the Part II source electrode and the drain electrode
There is overlapping region in the orthographic projection of the substrate.
3. array base palte according to claim 1, it is characterised in that：The source electrode the substrate orthographic projection with it is described
Pixel electrode is spaced the first distance in the orthographic projection of the substrate.
4. array base palte according to claim 1, it is characterised in that：The source electrode and the material of the drain electrode are metal
Conductive material or semiconductor conductive material.
5. a kind of preparation method of array base palte, including：
Grid is made on the first surface of substrate；
Insulating barrier is formed on the first surface of the substrate, the insulating barrier is covered the grid；
Drain electrode and pixel electrode are made on the first surface of the insulating barrier, the drain electrode and the pixel electrode is contacted；
Sacrifice layer is made on the first surface of the insulating barrier and the first surface of the drain electrode；
Source electrode is made on the first surface of the insulating barrier and the first surface of the sacrifice layer, makes the grid, the source
Pole and the drain electrode form micro electromechanical system switch；
The sacrifice layer is removed, the array base palte is obtained；
Wherein, in the state of the non-on-load voltage of the grid, there is gap between the source electrode and the drain electrode；In the grid
In the state of the on-load voltage of pole, the source electrode and the drain contact.
6. preparation method according to claim 5, it is characterised in that described to be made on the first surface of the insulating barrier
The step of source electrode, including：
Part I source electrode is made on the first surface of the first sacrifice layer, makes the Part I source electrode and the grid in institute
There is overlapping region in the orthographic projection for stating substrate；Wherein, first sacrifice layer is located on the first surface of the insulating barrier；
Part II source electrode is made on the first surface of the second sacrifice layer, makes the Part II source electrode and the drain electrode in institute
There is overlapping region in the orthographic projection for stating substrate, wherein, second sacrifice layer is located on the first surface of the drain electrode；
Wherein, the source electrode includes the Part I source electrode and the Part II source electrode.
7. preparation method according to claim 5, it is characterised in that described to be made on the first surface of the insulating barrier
The step of source electrode, including：
By the source electrode and the pixel electrode interval setting, make orthographic projection and pixel electricity of the source electrode in the substrate
Pole is spaced the first distance in the orthographic projection of the substrate.
8. preparation method according to claim 5, it is characterised in that：The source electrode and the material of the drain electrode are metal
Conductive material or semiconductor conductive material.
9. preparation method according to claim 5, it is characterised in that the sacrificial layer material includes：Phosphoric acid glass, dioxy
SiClx, polysilicon or porous silicon.
10. a kind of display device, including the array base palte as described in any one of Claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710065876.8A CN106865484A (en) | 2017-02-06 | 2017-02-06 | Array base palte and preparation method thereof, display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710065876.8A CN106865484A (en) | 2017-02-06 | 2017-02-06 | Array base palte and preparation method thereof, display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106865484A true CN106865484A (en) | 2017-06-20 |
Family
ID=59166626
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710065876.8A Pending CN106865484A (en) | 2017-02-06 | 2017-02-06 | Array base palte and preparation method thereof, display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106865484A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6091125A (en) * | 1998-12-02 | 2000-07-18 | Northeastern University | Micromechanical electronic device |
| CN1905198A (en) * | 2005-07-29 | 2007-01-31 | 三星电子株式会社 | Array substrate, method of manufacturing the same and method of crystallizing silicon |
| CN1975929A (en) * | 2005-11-29 | 2007-06-06 | 韩国科学技术院 | A memory array and a display apparatus using mechanical switch, method for controlling the same |
| CN103700671A (en) * | 2013-12-24 | 2014-04-02 | 华映视讯（吴江）有限公司 | Pixel array substrate and display panel |
| US20140115873A1 (en) * | 2008-12-18 | 2014-05-01 | Analog Devices, Inc. | Micro-electro-mechanical switch beam construction with minimized beam distortion and method for constructing |
| US20150001539A1 (en) * | 2012-02-22 | 2015-01-01 | Massachusetts Institute Of Technology | Flexible high-voltage thin film transistors |
| CN105047484A (en) * | 2014-04-25 | 2015-11-11 | 亚德诺半导体集团 | Mems switch |
-
2017
- 2017-02-06 CN CN201710065876.8A patent/CN106865484A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6091125A (en) * | 1998-12-02 | 2000-07-18 | Northeastern University | Micromechanical electronic device |
| CN1905198A (en) * | 2005-07-29 | 2007-01-31 | 三星电子株式会社 | Array substrate, method of manufacturing the same and method of crystallizing silicon |
| CN1975929A (en) * | 2005-11-29 | 2007-06-06 | 韩国科学技术院 | A memory array and a display apparatus using mechanical switch, method for controlling the same |
| US20140115873A1 (en) * | 2008-12-18 | 2014-05-01 | Analog Devices, Inc. | Micro-electro-mechanical switch beam construction with minimized beam distortion and method for constructing |
| US20150001539A1 (en) * | 2012-02-22 | 2015-01-01 | Massachusetts Institute Of Technology | Flexible high-voltage thin film transistors |
| CN103700671A (en) * | 2013-12-24 | 2014-04-02 | 华映视讯（吴江）有限公司 | Pixel array substrate and display panel |
| CN105047484A (en) * | 2014-04-25 | 2015-11-11 | 亚德诺半导体集团 | Mems switch |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104716144B (en) | Array base palte and preparation method thereof, display device | |
| TWI400510B (en) | Mems array substrate and display device using the same | |
| CN103247531B (en) | Thin-film transistor and preparation method thereof and display | |
| CN106098699A (en) | A kind of array base palte, its manufacture method, display floater and preparation method thereof | |
| CN104576658A (en) | Array substrate, method for manufacturing array substrate and displayer | |
| CN105655359A (en) | Method for manufacturing TFT (thin-film transistor) substrates | |
| CN104779171A (en) | Low-temperature polycrystalline silicon thin film transistor, manufacturing method thereof, array substrate and display device | |
| CN103700629A (en) | Array base plate and preparation method thereof as well as display device | |
| CN106783889B (en) | Display substrate, preparation method thereof and display device | |
| CN100583458C (en) | Pixel structure, thin-film transistor and production method thereof | |
| CN103928343A (en) | Method for manufacturing thin film transistor and organic light-emitting diode display | |
| CN104090401A (en) | Array substrate, preparation method thereof and display device | |
| CN103474439B (en) | A kind of display device, array base palte and preparation method thereof | |
| CN105633136B (en) | A kind of thin film transistor (TFT), its driving method, array substrate and display device | |
| CN105118777A (en) | Manufacturing method for TFT back board and structure | |
| CN104392991A (en) | Array substrate and preparation method thereof, display device | |
| CN102629589B (en) | Array substrate and manufacturing method thereof, and display apparatus | |
| CN103383924A (en) | Array substrate and method of fabricating the same | |
| CN109545836A (en) | A kind of OLED display and preparation method thereof | |
| CN206619596U (en) | Array base palte and display panel | |
| CN103094353A (en) | Thin film transistor structure, liquid crystal display device and manufacturing method | |
| CN105206619B (en) | A kind of array base palte and preparation method thereof, display panel | |
| CN104810375A (en) | Array substrate, manufacture method thereof and display device | |
| CN106865484A (en) | Array base palte and preparation method thereof, display device | |
| CN104485420A (en) | Organic thin film transistor and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170620 |