CN106856171A - The forming method of fin formula field effect transistor - Google Patents
The forming method of fin formula field effect transistor Download PDFInfo
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- CN106856171A CN106856171A CN201510906912.XA CN201510906912A CN106856171A CN 106856171 A CN106856171 A CN 106856171A CN 201510906912 A CN201510906912 A CN 201510906912A CN 106856171 A CN106856171 A CN 106856171A
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- dielectric layer
- deuterium
- fin
- field effect
- formula field
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 230000005669 field effect Effects 0.000 title claims abstract description 49
- 229910052805 deuterium Inorganic materials 0.000 claims abstract description 145
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 claims abstract description 98
- 239000004065 semiconductor Substances 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 238000000137 annealing Methods 0.000 claims abstract description 12
- 238000011049 filling Methods 0.000 claims abstract description 6
- 239000007789 gas Substances 0.000 claims description 60
- 239000000463 material Substances 0.000 claims description 35
- 238000000151 deposition Methods 0.000 claims description 26
- 230000008021 deposition Effects 0.000 claims description 21
- 229910052735 hafnium Inorganic materials 0.000 claims description 20
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 20
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 18
- 239000001301 oxygen Substances 0.000 claims description 18
- 229910052760 oxygen Inorganic materials 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 239000011435 rock Substances 0.000 claims description 10
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 8
- 238000005137 deposition process Methods 0.000 claims description 8
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 7
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 5
- 229910052593 corundum Inorganic materials 0.000 claims description 5
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910015801 BaSrTiO Inorganic materials 0.000 claims description 3
- 229910003865 HfCl4 Inorganic materials 0.000 claims description 3
- 229910002370 SrTiO3 Inorganic materials 0.000 claims description 3
- PDPJQWYGJJBYLF-UHFFFAOYSA-J hafnium tetrachloride Chemical compound Cl[Hf](Cl)(Cl)Cl PDPJQWYGJJBYLF-UHFFFAOYSA-J 0.000 claims description 3
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- -1 deuterium ion Chemical class 0.000 abstract description 48
- 230000000694 effects Effects 0.000 abstract description 16
- DYCJFJRCWPVDHY-LSCFUAHRSA-N NBMPR Chemical compound O[C@@H]1[C@H](O)[C@@H](CO)O[C@H]1N1C2=NC=NC(SCC=3C=CC(=CC=3)[N+]([O-])=O)=C2N=C1 DYCJFJRCWPVDHY-LSCFUAHRSA-N 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 147
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 239000010408 film Substances 0.000 description 14
- 150000002500 ions Chemical class 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000005530 etching Methods 0.000 description 10
- 238000000926 separation method Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 7
- 125000004429 atom Chemical group 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- YZCKVEUIGOORGS-IGMARMGPSA-N Protium Chemical compound [1H] YZCKVEUIGOORGS-IGMARMGPSA-N 0.000 description 5
- 241000720974 Protium Species 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 230000006641 stabilisation Effects 0.000 description 5
- 238000011105 stabilization Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 239000000725 suspension Substances 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 229910001439 antimony ion Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000002353 field-effect transistor method Methods 0.000 description 1
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910001449 indium ion Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
A kind of forming method of fin formula field effect transistor, including：Semiconductor substrate is provided, fin is formed with the Semiconductor substrate；It is developed across the pseudo- grid of part fin side wall and top surface；The dielectric layer of the covering Semiconductor substrate, fin and pseudo- grid is formed, the surface of the dielectric layer flushes with the top surface of pseudo- grid；The pseudo- grid are removed, groove is formed；The high-K dielectric layer containing deuterium is formed in the side wall and lower surface of the groove；The high-K dielectric layer containing deuterium is annealed so that the deuterium ion in the high-K dielectric layer containing deuterium is diffused in the fin of bottom portion of groove, remaining oxide layer is used as boundary layer；After annealing, the metal gates of filling groove are formed in the high-K dielectric layer.The method of the present invention causes that deuterium ion is uniformly diffused into the fin of bottom portion of groove, improves the HCI effects of N-type fin formula field effect transistor and the NBTI effects of p-type fin formula field effect transistor.
Description
Technical field
The present invention relates to field of semiconductor fabrication, more particularly to a kind of formation side of fin formula field effect transistor
Method.
Background technology
Continuing to develop with semiconductor process technique of the invention, process node is gradually reduced, rear grid
(gate-last) technique is widely applied, and to obtain preferable threshold voltage, improves device performance.
But when the characteristic size (CD, Critical Dimension) of device further declines, even if using
Grid technique afterwards, the structure of conventional metal-oxide-semiconductor field effect transistor also cannot meet the demand to device performance,
Fin formula field effect transistor (Fin FET) has obtained extensive concern as the replacement of conventional device.
A kind of fin formula field effect transistor of prior art includes：Semiconductor substrate, the Semiconductor substrate
On be formed with the fin of protrusion, fin after semiconductor substrate etching generally by obtaining；Separation layer,
Cover a part for the surface of the Semiconductor substrate and the side wall of fin；Grid structure, across in institute
State on fin, cover top and the side wall of the fin, grid structure includes gate dielectric layer and is situated between positioned at grid
Gate electrode on matter layer.
The material of the gate dielectric layer is silica, and the material of gate electrode is polysilicon.As fin is imitated
Answer the characteristic size of transistor also less and less, in order to reduce the parasitic capacitance of fin formula field effect transistor with
And the leakage current of reduction device, device speed is improved, high-K gate dielectric layer is folded with the grid of metal gate electrode
Rotating fields are introduced in fin formula field effect transistor.In order to avoid the metal material of metal gates is to crystal
The influence of pipe other structures, the metal gates are generally used with the gate stack structure of high-K gate dielectric layer
" grid (gate last) afterwards " technique makes.
The forming process of the metal gates of existing fin formula field effect transistor is：Semiconductor substrate, institute are provided
State and be formed with Semiconductor substrate some fins；Pseudo- grid are formed on the side wall of the fin and surface；Shape
Into the dielectric layer for covering the pseudo- grid, fin and semiconductor substrate surface, the surface of the dielectric layer is higher than
The top surface of pseudo- grid；The dielectric layer is planarized using chemical mechanical milling tech, until exposing puppet
The top surface of grid；The pseudo- grid are removed, groove is formed, the groove exposes the partial sidewall of fin
And top surface；In the middle formation high-K gate dielectric layer and metal gate electrode of the groove.
The fin formula field effect transistor performance of existing formation still has to be hoisted.
The content of the invention
The problem that the present invention is solved is the HCI effects and P for how improving N-type fin formula field effect transistor
The NBTI effects of type fin formula field effect transistor.
To solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, including：
Semiconductor substrate is provided, fin is formed with the Semiconductor substrate；It is developed across part fin side
The pseudo- grid of wall and top surface；Form the dielectric layer of the covering Semiconductor substrate, fin and pseudo- grid, institute
The surface for stating dielectric layer flushes with the top surface of pseudo- grid；The pseudo- grid are removed, groove is formed；Described
The side wall and lower surface of groove form the high-K dielectric layer containing deuterium；The high-K dielectric layer containing deuterium is entered
Row annealing so that the deuterium ion in the high-K dielectric layer containing deuterium is diffused in the fin of bottom portion of groove；Annealing
Afterwards, the metal gates of filling groove are formed in the high-K dielectric layer.
Optionally, the high-K dielectric layer containing deuterium is formed using auto-dope depositing operation.
Optionally, the formation process of the high-K dielectric layer containing deuterium is the atom layer deposition process of auto-dope.
Optionally, the material of the high-K dielectric layer is HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、
ZrO2、ZrSiO2、Al2O3、SrTiO3Or BaSrTiO.
Optionally, the high-K dielectric layer material HfO2, the atom layer deposition process formation of auto-dope is containing deuterium
The process of high-K dielectric layer include：The step of to hafnium source gas is passed through in deposition chambers；To deposition chambers
The step of being passed through oxygen source gas；The step of to deuterium source gas is passed through in chamber；Apply radio-frequency power, by hafnium
The step of source gas, oxygen source gas and deuterium source gas are dissociated into plasma；Plasma-deposited formation contains
The step of high K dielectric film layer of deuterium；Repeat abovementioned steps, some high K dielectric films containing deuterium
Layer constitutes the high-K dielectric layer containing deuterium.
Optionally, hafnium source gas is HfCl4, the flow of hafnium source gas is 60sccm to 500sccm,
Oxygen source gas are O2Or O3, the flow of oxygen source gas is 20~300sccm, and deuterium source gas is DO2, deuterium
The flow of source gas is 30~200sccm, and deposition chambers pressure is 0.1 support to 8 supports, deposition chambers radio frequency
Power is 300 watts to 3000 watts, and deposition chambers temperature is 250~400 degrees Celsius.
Optionally, the concentration of deuterium ion is in the high-K dielectric layer containing deuterium
1E12atom/cm3~1E16atom/cm3, the thickness of the high-K dielectric layer containing deuterium is 5~30 angstroms.
Optionally, 600~1200 degrees Celsius when being annealed, annealing time is 30 seconds~60 minutes, is moved back
Fiery atmosphere is atmosphere of inert gases.
Optionally, source region and drain region are also formed with the fin of the pseudo- grid both sides.
Optionally, also include：Before the anneal, cap rock is formed on the high-K dielectric layer surface containing deuterium.
Optionally, the cap rock is metal nitride.
Optionally, the metal nitride is TiN or TaN.
Optionally, the thickness of the cap rock is 10~50 angstroms.
Compared with prior art, technical scheme has advantages below：
The method of the present invention, the high-K dielectric layer containing deuterium of formation is film layer, can use auto-dope technique
Uniform doping deuterium ion, can cause containing deuterium when subsequently being annealed in the high-K dielectric layer for being formed
Deuterium ion in high-K dielectric layer is uniformly diffused into the fin of bottom portion of groove, deuterium ion and fin portion surface
Silicon suspension bond close or substitute si-h bond in protium be stabilization silicon deuterium key, so as to improve N
The HCI effects of type fin formula field effect transistor and the NBTI effects of p-type fin formula field effect transistor；
And the side wall table of the lower surface of groove but also covering groove is not only covered due to the high-K dielectric layer containing deuterium
Face, the deuterium ion so that fin of bottom portion of groove edge and middle can uniformly adulterate.
Further, when forming the high-K dielectric layer containing deuterium using the atom layer deposition process of auto-dope, formed
One layer of corresponding auto-dope deuterium ion of high K dielectric film layer containing deuterium, deuterium ion is in height of each layer containing deuterium
Can be uniformly distributed in K dielectric thin film layers, if high K dielectric film layer of the dried layer containing deuterium stacks to be formed containing deuterium
High-K dielectric layer, thus high-K dielectric layer thickness evenness containing deuterium is higher, and the K high containing deuterium is situated between
Deuterium ion is uniformly distributed in matter layer.
Brief description of the drawings
Fig. 1~Fig. 5 is the structural representation of the forming process of one embodiment of the invention fin formula field effect transistor
Figure.
Specific embodiment
As background technology is sayed, the fin formula field effect transistor performance of existing formation still has to be hoisted, such as
There is hot carrier in jection (Hot Carrier in the N-type fin formula field effect transistor that prior art is formed
Injection, HCI) problem, there is Negative Bias Temperature Instability in p-type fin formula field effect transistor
The problem of (Negative Bias Temperature Instability, NBTI).
Research finds that in the manufacturing process of fin formula field effect transistor, semiconductor substrate surface can be formed
The dangling bonds or trap of a large amount of silicon so that between the gate dielectric layer and Semiconductor substrate of the transistor of formation
Interfacial state changes so that the threshold voltage of fin formula field effect transistor shifts, and silicon is outstanding
Hang key or trap holds generation snowslide ionization by collision and causes hot carrier injection effect under strong electric field；And
The dangling bonds of silicon are easily combined during technique with hydrogen, form unstable Si -- H bond.
To solve the above problems, a kind of shape of fin formula field effect transistor is provided in one embodiment of the invention
Into method, including：Semiconductor substrate is provided, fin is formed with the Semiconductor substrate；It is developed across
The pseudo- grid of part fin side wall and top surface；Form the covering Semiconductor substrate, fin and pseudo- grid
Dielectric layer, the surface of the dielectric layer flushes with the top surface of pseudo- grid；The pseudo- grid are removed, is formed recessed
Groove；Deuterium ion is injected in Semiconductor substrate using from ion implantation technology to bottom portion of groove；Injection deuterium ion
Afterwards, high-K dielectric layer is formed on the side wall and lower surface of the groove；In the high-K dielectric layer
Form the metal gates of filling groove.By the way that to deuterium ion is injected in Semiconductor substrate, deuterium ion hangs with silicon
Protium forms stability Si-D keys higher in hanging key or substituting Si -- H bond, improves high K dielectric
The interfacial state of the semiconductor substrate surface under layer, improves the HCI effects of N-type fin formula field effect transistor
Should and p-type fin formula field effect transistor NBTI effects.
Further study show that, the above method carries out deuterium ion using ion implantation technology to Semiconductor substrate
Injection, but because the structure of fin formula field effect transistor is more special, when ion implanting is carried out, fin
(shadow effect, when being injected, subregion cannot for the shadow effect that formula field-effect transistor is produced
It is injected into) can cause the deuterium ion skewness that is injected in the Semiconductor substrate of bottom portion of groove, and from
Son injection easily carrys out implant damage to semiconductor backing tape.
Therefore, the invention provides a kind of forming method of fin formula field effect transistor, deuterium is contained this is formed
High-K dielectric layer when, can using auto-dope technique in the high-K dielectric layer for being formed uniform doping deuterium
Ion, can subsequently cause that the deuterium ion in the high-K dielectric layer containing deuterium is uniformly diffused into bottom portion of groove
In fin, deuterium ion closes or substitutes the protium shape in si-h bond with the suspension bond of the silicon of fin portion surface
Into the fluosilicic key of stabilization, so as to improve the HCI effects and p-type fin of N-type fin formula field effect transistor
The NBTI effects of formula field-effect transistor.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
Specific embodiment of the invention is described in detail.When the embodiment of the present invention is described in detail, for purposes of illustration only,
Schematic diagram can disobey general ratio and make partial enlargement, and the schematic diagram is example, and it should not herein
Limit the scope of the invention.Additionally, the three of length, width and depth should be included in actual fabrication
Dimension space size.
The structural representation of the forming process of Fig. 1~Fig. 5 one embodiment of the invention fin formula field effect transistors.
With reference to Fig. 1, there is provided Semiconductor substrate 200, fin 201 is formed with the Semiconductor substrate 200；
It is developed across the pseudo- grid 204 of the side wall of part fin 201 and top surface；The formation covering Semiconductor substrate,
The dielectric layer 203 of fin and pseudo- grid, the surface of the dielectric layer 203 flushes with the top surface of pseudo- grid 204.
The Semiconductor substrate 200 can be silicon or silicon-on-insulator (SOI), the Semiconductor substrate
200 can also be germanium, germanium silicon, GaAs or germanium on insulator or other suitable materials, in this implementation
The material of the Semiconductor substrate 200 is silicon.
The surface of the Semiconductor substrate 200 is formed with the fin 201 of some projections, described in the present embodiment
Fin 201 is formed by etch semiconductor substrates 200, in other embodiments of the invention, the fin
Portion 201 is formed by epitaxy technique.Can be according to the fin field effect crystal for being formed in the fin 201
The type of pipe is different doped with different types of foreign ion, in the present embodiment, when fin to be formed
When effect transistor is p-type fin formula field effect transistor, can be with doped N-type foreign ion in fin 201；
When fin formula field effect transistor to be formed is N-type fin formula field effect transistor, can be with fin 201
Doped p-type foreign ion.
The material of the pseudo- grid 204 is polysilicon, amorphous carbon.The pseudo- grid 204 are subsequently removed to be formed
Groove, forms metal gates in a groove.
In one embodiment, the forming process of the pseudo- grid 204 is：Form the covering Semiconductor substrate
200 and the pseudo- gate material layer of fin 201, the top surface of the surface higher than fin 201 of pseudo- gate material layer；
Planarize the surface of the pseudo- gate material layer；The part surface of pseudo- gate material layer after planarization is formed and covered
Film layer；Pseudo- gate material layer after being planarized described in the mask layer as mask etching, is developed across fin
Partial sidewall and top surface pseudo- grid 204.
In other embodiments, the pseudo- grid 204 and fin 201 can also form boundary layer.The boundary
The material of surface layer can be silica.
In one embodiment, separation layer 202, the separation layer are also formed with the Semiconductor substrate 200
Less than the top surface of fin 201, the separation layer 202 is for the adjacent fin of electric isolation on 202 surface
Portion 201 and adjacent grid structure, the material of the separation layer 202 is silica, silicon nitride or nitrogen oxygen
SiClx, the material of separation layer 202 described in the present embodiment is silica.It is specific that separation layer 202 is formed
Process is：It is initially formed the spacer material layer of the covering Semiconductor substrate 200 and fin 201；Then
The spacer material layer is planarized using chemical mechanical milling tech, the top surface with fin 201 is to stop
Only layer；Then it is etched back to remove the part spacer material layer, forms separation layer 202, the separation layer
Top surface of 202 surface less than fin 201.
In one embodiment, it is also formed with side wall 205 in the both sides sidewall surfaces of the pseudo- grid 204.It is described
Side wall 205 can be single or multiple lift (>=2 layers) stacked structure.The material of the side wall 205 can be oxygen
SiClx, silicon nitride or silicon oxynitride.
After side wall 205 is formed, can also distinguish in the fin 201 of pseudo- grid 204 and the both sides of side wall 205
Form source region and drain region 206.
In the present embodiment, the source region and drain region 206 are stress source-drain area, the shape of the stress source-drain area
It is into process：With the fin that the pseudo- grid 204 and side wall 205 are mask etching puppet grid 204 both sides, shape
Into etching groove；Stress material layer is filled in etching groove, stress source-drain area is formed.
In one embodiment, the etching groove can be the etching groove of sigma shapes, be filled in etching groove
Stress material is SiGe.In another embodiment, the etching groove can be rectangular channel, be filled out in etching groove
The stress material for filling is carborundum.
In other embodiments of the invention, the source region and drain region 206 can be by ion implantation technologies
Formed, its forming process is：With the pseudo- grid 204 and side wall 205 as mask, using ion implanting work
Skill to pseudo- grid 204 and the fin impurity ion of the both sides of side wall 205, in pseudo- grid 204 and side wall 205
Source region and drain region 206 are formed in the fin 201 of both sides.
The foreign ion of the ion implanting injection is p type impurity ion or N-type impurity ion, the P
Type foreign ion is one or more in boron ion, gallium ion or indium ion；The N-type impurity ion
It is one or more in phosphonium ion, arsenic ion or antimony ion.
The material of the dielectric layer 203 is silica, silicon nitride or low-K dielectric material.
With reference to Fig. 2, the pseudo- grid 204 (with reference to figure) are removed, form groove 211；In the groove 211
Side wall and lower surface formed containing deuterium high-K dielectric layer 210.
The deuterium ion that the high-K dielectric layer 210 containing deuterium spreads for the follow-up fin to the bottom of groove 211
Deuterium source is provided.The high-K dielectric layer 210 containing deuterium that this implementation is formed is film layer, is using depositing operation shape
During into the high-K dielectric layer 210 for containing deuterium, can be equal in the high-K dielectric layer for being formed using auto-dope technique
Even doping deuterium ion, can subsequently cause that the deuterium ion in the high-K dielectric layer 210 containing deuterium uniformly expands
It is scattered in the fin 201 of the bottom of groove 211, compared to ion implantation technology, prevents shadow effect (shadow
Effect) the uniformity of the deuterium ion to being adulterated in the fin 201 of the bottom of groove 211, and due to containing deuterium
High-K dielectric layer 210 not only cover groove 211 lower surface and also covering groove 211 side wall table
Face so that the fin 211 of bottom portion of groove edge and middle all can uniformly adulterate deuterium ion.
The high-K dielectric layer 210 containing deuterium is formed using auto-dope depositing operation.The high-K dielectric layer
210 material is HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、
SrTiO3Or BaSrTiO.In the present embodiment, the material of the high-K dielectric layer 210 is HfO2。
In the present embodiment, the formation process of the high-K dielectric layer 210 containing deuterium is the atomic layer of auto-dope
Depositing operation, the atom layer deposition process of auto-dope formed the high-K dielectric layer containing deuterium process include (with
Form the HfO containing deuterium2As a example by high-K dielectric layer 210)：The step of to hafnium source gas is passed through in deposition chambers；
The step of oxygen source gas being passed through to deposition chambers；The step of to deuterium source gas is passed through in chamber；Apply radio frequency
Power, the step of hafnium source gas, oxygen source gas and deuterium source gas are dissociated into plasma；Plasma
The step of deposition forms the high K dielectric film layer containing deuterium；Repeat abovementioned steps, some height containing deuterium
K dielectric thin film layers constitute the high-K dielectric layer 210 containing deuterium.
It should be noted that when the high-K dielectric layer of other materials is formed, auto-dope ald work
The process of skill and formation HfO2High-K dielectric layer process is similar to, such as form Al2O3It is, in said process
Hafnium source gas replace with aluminum source gas accordingly, other step all sames.In brief, can be by K high
Other elements in dielectric layer material outside oxygen element are defined as the first element, carry out auto-dope atomic layer deposition
During product technique, above-mentioned hafnium source gas is replaced with into the source gas with the first element, such as high K dielectric
Layer material is Al2O3When, the first element be aluminium element, by above-mentioned hafnium source gas replace with aluminium unit
The source gas of element；For another example, high-K dielectric layer material is TiO2, the first element is titanium elements, will be above-mentioned
Hafnium source gas replace with the source gas with titanium elements；Such as, high-K dielectric layer material is HfZrO,
First element is hafnium element and zr element, and above-mentioned hafnium source gas is replaced with hafnium element and zr element
Source gas.Detailed process is：The step of to the source gas with the first element is passed through in deposition chambers；
The step of oxygen source gas being passed through to deposition chambers；The step of to deuterium source gas is passed through in chamber；Apply radio frequency
Power, the source gas with the first element, oxygen source gas and deuterium source gas are dissociated into the step of plasma
Suddenly；The step of plasma-deposited formation contains the high K dielectric film layer of deuterium；Repeat abovementioned steps,
Some high K dielectric film layers containing deuterium constitute the high-K dielectric layer 210 containing deuterium.
In one embodiment, the atom layer deposition process of the auto-dope forms the HfO containing deuterium2High K dielectric
During layer 210, hafnium source gas is HfCl4, the flow of hafnium source gas is 60sccm to 500sccm,
Oxygen source gas are O2Or O3, the flow of oxygen source gas is 20~300sccm, and deuterium source gas is DO2, deuterium
The flow of source gas is 30~200sccm, and deposition chambers pressure is 0.1 support to 8 supports, deposition chambers radio frequency
Power is 300 watts to 3000 watts, and deposition chambers temperature is 250~400 degrees Celsius, improves and is formed containing deuterium
The thickness evenness of high-K dielectric layer 210 and the uniformity of deuterium ion distribution.
It should be noted that formed other materials the high-K dielectric layer 210 containing deuterium when, technological parameter with
Form the HfO containing deuterium2The technological parameter of high-K dielectric layer 210 is similar to, only need to be by the hafnium source in said process
Gas replaces with the source gas with the first element.Specially：The source gas with the first element
Flow is 60sccm to 500sccm, and oxygen source gas are O2Or O3, the flow of oxygen source gas is 20~300
Sccm, deuterium source gas is DO2, the flow of deuterium source gas is 30~200sccm, and deposition chambers pressure is
0.1 support to 8 supports, deposition chambers radio-frequency power is 300 watts to 3000 watts, and deposition chambers temperature is 250~400
Degree Celsius.
When forming the high-K dielectric layer 210 containing deuterium using the atom layer deposition process of auto-dope, one layer is formed
The corresponding auto-dope deuterium ion of high K dielectric film layer containing deuterium, deuterium ion is situated between in K high of each layer containing deuterium
It is uniformly distributed in matter film layer, and deuterium ion is in free state in high K dielectric film layer, if dried layer contains
The high K dielectric film layer of deuterium stacks the high-K dielectric layer 210 to be formed containing deuterium, thus the high K dielectric containing deuterium
210 thickness evenness of layer are higher, and deuterium ion is uniformly distributed in the high-K dielectric layer 210 containing deuterium, makes
The deuterium ion uniform concentration distribution of diverse location in the high-K dielectric layer 210 of deuterium must be contained, when thickness is annealed,
Allow that the deuterium ion in the high-K dielectric layer 210 containing deuterium uniformly diffuses to the fin 201 of bottom portion of groove
In.
The thickness of high-K dielectric layer 210 containing deuterium that the above method is formed is 5~30 angstroms, and the K high containing deuterium is situated between
The concentration of deuterium ion is 1E12atom/cm in matter layer 2103~1E16atom/cm3。
Removing the pseudo- grid can be using wet-etching technology, in embodiment, the quarter that wet etching is used
Erosion solution is TMAH (TMAH), ammoniacal liquor or KOH.
In other embodiments, when interfacial TCO layer is formed, after the pseudo- grid of removal, corresponding removal border face
Layer.
With reference to Fig. 3, cap rock 207 is formed on the surface of high-K dielectric layer 210 containing deuterium.
The material of the cap rock 207 is metal nitride.In one embodiment, the metal nitride
It is TiN or TaN.The one side of the cap rock 207 can be as a part for the metal gates being subsequently formed；
Another convenience, when being annealed, the TiN can also prevent in high-K dielectric layer 210 oxonium ion to
The direction diffusion on the surface of high-K dielectric layer 210.
The thickness of the cap rock 207 is 10~50 angstroms
In other examples, it is also possible to do not form cap rock 207, the high-K dielectric layer containing deuterium is being formed
Follow-up annealing steps are directly carried out after 210.
With reference to Fig. 4, the high-K dielectric layer 210 containing deuterium is annealed so that the K high containing deuterium is situated between
Deuterium ion in matter layer 210 is diffused in the fin of bottom portion of groove.
When being annealed, the deuterium ion in the high-K dielectric layer 210 containing deuterium can spread and carry out bottom portion of groove
Fin 201 in, and partly or entirely the suspension bond of the silicon on deuterium ion and the surface of fin 201 close or
The protium that person substitutes in si-h bond is the fluosilicic key of stabilization, due to the deuterium of the high-K dielectric layer 210 containing deuterium
Ion is to be uniformly distributed, thus deuterium ion in the high-K dielectric layer 210 containing deuterium is uniform from each position
It is diffused into the fin of the bottom of groove 211, thus the silicon of diverse location in the fin of bottom portion of groove is outstanding
Protium is formed during floating key can be combined into the silicon deuterium key of stabilization or deuterium ion replacement si-h bond with deuterium ion
The silicon deuterium key more more stable than si-h bond.
In one embodiment, the temperature of the annealing process is 600~1200 degrees Celsius, can be taken the photograph for 600
Family name's degree, 700 degrees Celsius, 800 degrees Celsius, 900 degrees Celsius, 1000 degrees Celsius, 1100 degrees Celsius, 1200
Degree Celsius, annealing time is 30 seconds~60 minutes, and annealing atmosphere is atmosphere of inert gases, can be 30
Second, 1 minute, 5 minutes, 10 minutes, 20 minutes, 30 minutes, 40 minutes, 50 minutes, 55 points
Clock, 60 minutes, with deuterium ion in causing the high-K dielectric layer 210 containing deuterium from high-K dielectric layer 210 and fin
The contact surface in portion 201 is uniformly diffused in the fin of bottom portion of groove, and causes deuterium ion and fin 201
Protium in the suspension bond conjunction of the silicon on surface or the si-h bond on replacement fin 201 surface forms stabilization
Silicon deuterium key；And cause that the deuterium ion of high-K dielectric layer 210 containing deuterium is wholly or largely diffused into fin
In 201, the residual of deuterium ion in high-K dielectric layer 210 is reduced so that the performance of high-K dielectric layer 210 is protected
Hold constant.
Deuterium ion in high-K dielectric layer 210 containing deuterium is diffused into after fin 201, and remaining K high is situated between
Matter layer 210 is still as the gate dielectric layer of metal gates.
With reference to Fig. 5, after annealing, the metal gates 208 of filling groove are formed on the cap rock 207.
The material of the metal gates 208 is W, Al or Cu.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore guarantor of the invention
Shield scope should be defined by claim limited range.
Claims (13)
1. a kind of forming method of fin formula field effect transistor, it is characterised in that including：
Semiconductor substrate is provided, fin is formed with the Semiconductor substrate；
It is developed across the pseudo- grid of part fin side wall and top surface；
Form the dielectric layer of the covering Semiconductor substrate, fin and pseudo- grid, surface and the puppet of the dielectric layer
The top surface of grid is flushed；
The pseudo- grid are removed, groove is formed；
The high-K dielectric layer containing deuterium is formed in the side wall and lower surface of the groove；
The high-K dielectric layer containing deuterium is annealed so that the deuterium ion in the high-K dielectric layer containing deuterium expands
It is dissipated in the fin of bottom portion of groove；
After annealing, the metal gates of filling groove are formed in the high-K dielectric layer.
2. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that using from
Doping depositing operation forms the high-K dielectric layer containing deuterium.
3. the forming method of fin formula field effect transistor as claimed in claim 2, it is characterised in that described to contain
The formation process of the high-K dielectric layer of deuterium is the atom layer deposition process of auto-dope.
4. the forming method of fin formula field effect transistor as claimed in claim 3, it is characterised in that the height
The material of K dielectric layer is HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、
Al2O3、SrTiO3Or BaSrTiO.
5. the forming method of fin formula field effect transistor as claimed in claim 3, it is characterised in that the height
K dielectric layer material HfO2, the mistake of the atom layer deposition process high-K dielectric layer of the formation containing deuterium of auto-dope
Journey includes：The step of to hafnium source gas is passed through in deposition chambers；Oxygen source gas are passed through to deposition chambers
Step；The step of to deuterium source gas is passed through in chamber；Apply radio-frequency power, by hafnium source gas, oxygen source
The step of gas and deuterium source gas are dissociated into plasma；Plasma-deposited K high Jie formed containing deuterium
The step of matter film layer；Repeat abovementioned steps, some high K dielectric film layers containing deuterium are constituted and contained
The high-K dielectric layer of deuterium.
6. the forming method of fin formula field effect transistor as claimed in claim 5, it is characterised in that the hafnium
Source gas is HfCl4, the flow of hafnium source gas is 60sccm to 500sccm, and oxygen source gas are O2、
O3Or H2O, the flow of oxygen source gas is 20~300sccm, and deuterium source gas is DO2, deuterium source gas
Flow be 30~200sccm, deposition chambers pressure be 0.1 support to 8 supports, deposition chambers radio-frequency power
It it is 300 watts to 3000 watts, deposition chambers temperature is 250~400 degrees Celsius.
7. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that described to contain
The concentration of deuterium ion is 1E12atom/cm in the high-K dielectric layer of deuterium3~1E16atom/cm3, containing deuterium
The thickness of high-K dielectric layer is 5~30 angstroms.
8. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that moved back
600~1200 degrees Celsius when fiery, annealing time is 30 seconds~60 minutes, and annealing atmosphere is indifferent gas
Body atmosphere.
9. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the puppet
Source region and drain region are also formed with the fin of grid both sides.
10. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that also include：
Before the anneal, cap rock is formed on the high-K dielectric layer surface containing deuterium.
The forming method of 11. fin formula field effect transistors as claimed in claim 10, it is characterised in that the lid
Layer is metal nitride.
The forming method of 12. fin formula field effect transistors as claimed in claim 11, it is characterised in that the gold
Category nitride is TiN or TaN.
The forming method of 13. fin formula field effect transistors as claimed in claim 11, it is characterised in that the lid
The thickness of layer is 10~50 angstroms.
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| CN1531032A (en) * | 2003-03-11 | 2004-09-22 | ���ǵ�����ʽ���� | Manufacturing method for high dielectric constant oxidation film, capacitor therewith and manufacturing method thereof |
| TW200629420A (en) * | 2004-08-27 | 2006-08-16 | Renesas Tech Corp | High dielectric film, field-effect transistor, semiconductor integrated circuit device and method of producing of high dielectric film |
| CN103378156A (en) * | 2012-04-26 | 2013-10-30 | 台湾积体电路制造股份有限公司 | Multi-gate devices with replaced-channels and methods for forming the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1531032A (en) * | 2003-03-11 | 2004-09-22 | ���ǵ�����ʽ���� | Manufacturing method for high dielectric constant oxidation film, capacitor therewith and manufacturing method thereof |
| TW200629420A (en) * | 2004-08-27 | 2006-08-16 | Renesas Tech Corp | High dielectric film, field-effect transistor, semiconductor integrated circuit device and method of producing of high dielectric film |
| CN103378156A (en) * | 2012-04-26 | 2013-10-30 | 台湾积体电路制造股份有限公司 | Multi-gate devices with replaced-channels and methods for forming the same |
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Application publication date: 20170616 |