CN106847928B - Thin film transistor, array substrate and display device - Google Patents
Thin film transistor, array substrate and display device Download PDFInfo
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- CN106847928B CN106847928B CN201710065525.7A CN201710065525A CN106847928B CN 106847928 B CN106847928 B CN 106847928B CN 201710065525 A CN201710065525 A CN 201710065525A CN 106847928 B CN106847928 B CN 106847928B
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- 239000010409 thin film Substances 0.000 title claims abstract description 74
- 239000000758 substrate Substances 0.000 title claims abstract description 31
- 229910001092 metal group alloy Inorganic materials 0.000 claims abstract description 90
- 229910052751 metal Inorganic materials 0.000 claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 68
- 239000010408 film Substances 0.000 claims abstract description 65
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 24
- 239000003292 glue Substances 0.000 abstract description 13
- 238000001259 photo etching Methods 0.000 abstract description 6
- 239000000853 adhesive Substances 0.000 abstract description 5
- 230000001070 adhesive effect Effects 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 26
- 229910045601 alloy Inorganic materials 0.000 description 18
- 239000000956 alloy Substances 0.000 description 18
- 238000010586 diagram Methods 0.000 description 13
- 238000005530 etching Methods 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000003670 easy-to-clean Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- DTSBBUTWIOVIBV-UHFFFAOYSA-N molybdenum niobium Chemical compound [Nb].[Mo] DTSBBUTWIOVIBV-UHFFFAOYSA-N 0.000 description 1
- MGRWKWACZDFZJT-UHFFFAOYSA-N molybdenum tungsten Chemical compound [Mo].[W] MGRWKWACZDFZJT-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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Abstract
The invention provides a thin film transistor, an array substrate and a display device, wherein the thin film transistor comprises a conductive electrode, the conductive electrode is of a multilayer film structure, and the multilayer film at least comprises: the metal wire comprises a top metal layer, a metal alloy layer and a Cu wire layer, wherein the top metal layer is positioned on the top layer, the metal alloy layer is positioned between the top metal layer and the Cu wire layer, and the thickness of the top metal layer is smaller than a preset threshold value. In the invention, the top metal layer is added above the metal alloy layer, and the adhesive force between the metal and the PR glue is larger than that between the metal alloy and the PR glue, so that the PR glue is not easy to peel off in the photoetching process, thereby improving the yield of the thin film transistor.
Description
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor, an array substrate and a display device.
Background
With the development of large-scale display technology, Cu wires are increasingly widely used in thin film transistors. However, the Cu wire is easily oxidized and easily diffused, which greatly limits its application. In order to overcome the characteristic that the Cu wire is easily oxidized and easily diffused, in the prior art, a metal alloy layer (for example, a molybdenum metal alloy) is disposed on one side or both sides of the Cu wire to form a multi-layer film structured wire. However, when the mo metal alloy is located on the top layer of the multi-layer film structure, the adhesion between the mo metal alloy and the Photoresist (PR) is low during the photolithography process, and PR peeling is likely to occur during the photolithography process (e.g., after photo exposure or during etching), thereby reducing the yield of the tft.
Disclosure of Invention
In view of the above, the present invention provides a thin film transistor, an array substrate and a display device, so as to solve the problem that the yield of the thin film transistor is reduced due to the low adhesion between the metal alloy layer on the top layer of the conductive wire and the photoresist and the easy occurrence of PR peeling during the photolithography process in the conventional thin film transistor having the conductive wire with the multi-layer film structure.
To solve the above technical problem, the present invention provides a thin film transistor, including: including the conductive electrode, the conductive electrode is multilayer rete structure, multilayer rete includes at least: the metal wire comprises a top metal layer, a metal alloy layer and a Cu wire layer, wherein the top metal layer is positioned on the top layer, the metal alloy layer is positioned between the top metal layer and the Cu wire layer, and the thickness of the top metal layer is smaller than a preset threshold value.
Preferably, the thickness of the top metal layer is less than 500A.
Preferably, the thickness of the top metal layer is in the range of 200-500A.
Preferably, the top metal layer is made of Cu.
Preferably, the multilayer film layer structure further comprises: and the metal alloy layer is positioned below the Cu wire layer.
Preferably, the thickness range of the metal alloy layer located between the top metal layer and the Cu wiring layer is 100-.
Preferably, the conductive electrode includes a source electrode and a drain electrode.
Preferably, the thin film transistor further comprises a gate electrode having a multi-layer film structure including at least a Cu wiring layer and a metal alloy layer under the Cu wiring layer.
Preferably, the metal alloy is a molybdenum metal alloy.
The invention also provides an array substrate comprising the thin film transistor.
Preferably, the conductive electrode includes a source electrode and a drain electrode, and the array substrate further includes a data line, and the data line is disposed in the same layer as the source electrode and the drain electrode and has the same film structure.
The invention also provides a display device comprising the array substrate.
The technical scheme of the invention has the following beneficial effects:
the top metal layer is added above the metal alloy layer of the thin film transistor conductive electrode, and the adhesive force between the metal and the PR glue is larger than that between the metal alloy and the PR glue, so that the PR glue is not easy to peel off in the photoetching process, and the yield of the thin film transistor can be improved.
Drawings
FIG. 1 is a schematic diagram of a TFT in the prior art;
FIG. 2 is a schematic diagram of another prior art TFT;
FIG. 3 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention;
FIG. 4 is a schematic diagram showing EPM comparison of a thin film transistor when the source electrode and the drain electrode of the thin film transistor are respectively of a two-layer film structure, a three-layer film structure and a four-layer film structure;
fig. 5 is a schematic diagram of EPM characteristics of a thin film transistor obtained by etching at different times when forming the source electrode and the drain electrode having the four-layer film structure in fig. 4 according to an embodiment of the present invention;
fig. 6 is a schematic performance diagram of a thin film transistor obtained by etching at different times when forming the source electrode and the drain electrode having the four-layer film structure in fig. 4 according to an embodiment of the present invention;
fig. 7-13 are schematic views illustrating a method for manufacturing an array substrate according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention, are within the scope of the invention.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the description and claims of the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships are changed accordingly.
In order to solve the problem that in the existing thin film transistor with a multilayer film structure lead, the adhesion between a metal alloy layer on the top layer of the lead and a photoresist is low, and the PR peeling phenomenon is easy to occur in the photoetching process, so that the yield of the thin film transistor is reduced, the embodiment of the invention provides a thin film transistor, which comprises a conductive electrode, wherein the conductive electrode is in a multilayer film structure, and the multilayer film at least comprises: the top metal layer is positioned on the top layer, the metal alloy layer is positioned between the top metal layer and the Cu lead layer, and the thickness of the top metal layer is smaller than a preset threshold value, namely the top metal layer is a thin metal layer with a smaller thickness.
In the embodiment of the invention, the metal alloy layer above the Cu wire layer has the functions of preventing the Cu wire layer from being oxidized and preventing Cu in the Cu wire layer from diffusing to the upper layer film layer of the conductive electrode.
In the embodiment of the invention, the top metal layer is added above the metal alloy layer, and the adhesive force between the metal and the PR glue is larger than that between the metal alloy and the PR glue, so that the PR glue is not easy to peel off in the photoetching process, and the yield of the thin film transistor can be improved.
In the embodiment of the present invention, preferably, the thickness of the top metal layer is less than 500A (angstrom), that is, the predetermined threshold is 500A. Further preferably, the thickness of the top metal layer is in the range of 200-500A.
The top metal layer can be made of Cu, namely the top metal layer and the Cu wire layer are made of the same material, so that the top metal layer can be made of Cu directly used for making the Cu wire layer, equipment materials do not need to be replaced, and the process flow is saved.
The top metal layer is thin, so that the influence on the whole thickness of the conductive electrode is small, and when the top metal layer is made of Cu, the top metal layer is not easy to oxidize due to the thin thickness, and an oxidation layer is thin even if the top metal layer is oxidized, so that the top metal layer is easy to clean in a subsequent process.
In the embodiment of the present invention, the metal alloy may be a molybdenum metal alloy, such as a MoNb (molybdenum niobium) alloy, a MoW (molybdenum tungsten) alloy, or the like. Molybdenum metal alloys in particular suffer from a low adhesion to PR pastes. Of course, other types of metal alloys are not excluded from the metal alloys of the embodiments of the present invention.
The conductive electrode in the embodiment of the invention has a structure with at least three film layers, wherein the three film layers are respectively a top metal layer, a metal alloy layer and a Cu conductor layer. In a preferred embodiment of the present invention, the multi-layer film structure may further include: and the metal alloy layer is positioned below the Cu wire layer. The metal alloy layer under the Cu wire layer has the function of preventing the Cu wire layer from being oxidized and preventing Cu in the Cu wire layer from diffusing to the lower film layer of the conductive electrode. That is, in a preferred embodiment of the present invention, the conductive electrode has a minimum four-layer structure, which is a top metal layer, a metal alloy layer located above the Cu wiring layer, and a metal alloy layer located below the Cu wiring layer.
The metal alloy layer located above the Cu wiring layer and the metal alloy layer located below the Cu wiring layer may be the same metal alloy layer or may be different metal alloy layers. Preferably, the metal alloy layer located above the Cu wire layer and the metal alloy layer located below the Cu wire layer are the same metal alloy layer, so that when the two film layers are manufactured, equipment materials do not need to be replaced, and the process flow is saved.
Preferably, the thickness of the metal alloy layer between the top metal layer and the Cu wiring layer is in the range of 100-600A. The thickness of the Cu wire layer is in the range of 2000-6000A. The thickness of the metal alloy layer under the Cu wiring layer is in the range of 100-600A. The thickness of all the film layers is thin, so that the whole thickness of the whole thin film transistor is not influenced.
In the embodiment of the present invention, the conductive electrode may include a source electrode and a drain electrode, may further include a gate electrode, or may include a gate electrode, a source electrode, and a drain electrode.
In the embodiment of the present invention, it is preferable that the conductive electrode includes a source electrode and a drain electrode, because when the array substrate including the thin film transistor according to the embodiment of the present invention is manufactured, a PVX (passivation) layer needs to be manufactured above the source electrode and the drain electrode, and the PVX layer has an oxygen atmosphere during a deposition process, so that the Cu wiring layer is relatively easily oxidized, a metal alloy layer needs to be added on the Cu wiring layer to prevent the Cu wiring layer from being oxidized, and the metal alloy layer is located on a top layer and has a low adhesion with a photoresist, so that PR peeling is easily generated during a photolithography process, so that the source electrode and the drain electrode may adopt a multi-layer film structure including the top metal layer in the embodiment of the present invention to overcome the above problem.
Since the gate electrode does not have the above-described problem, the multilayer film structure including the top metal layer in the embodiment of the present invention may not be employed.
Of course, in order to improve the wire performance of the gate electrode, it is preferable that the gate electrode also includes a Cu wire layer, and in order to prevent the Cu wire layer from diffusing into the lower film layer, in an embodiment of the present invention, a metal alloy layer may be disposed below the Cu wire layer of the gate electrode, that is, the gate electrode in an embodiment of the present invention also has a multilayer film layer structure, and at least includes the Cu wire layer and the metal alloy layer located below the Cu wire layer.
The thin film transistor in the embodiment of the invention further comprises an active layer, and the active layer can be made of Oxide (Oxide), a-Si, polysilicon, hydrogenated amorphous silicon and the like.
The thin film transistor in the embodiment of the present invention may be a thin film transistor of a BCE (back channel) structure, and may also be a thin film transistor of an ESL (etch stop layer) structure.
An embodiment of the present invention further provides an array substrate, including the thin film transistor in any of the above embodiments.
Preferably, the conductive electrode includes a source electrode and a drain electrode, and the array substrate further includes a data line, and the data line is disposed on the same layer as the source electrode and the drain electrode and has the same film structure.
Because the data line, the source electrode and the drain electrode need to be manufactured with PVX (passivation) layers, and the PVX layers have oxygen atmosphere in the deposition process, the Cu conducting wire layer is easy to be oxidized, a metal alloy layer needs to be added on the Cu conducting wire layer to prevent the Cu conducting wire layer from being oxidized, the metal alloy layer is positioned on the top layer and has low adhesive force with photoresist, and the PR peeling phenomenon is easy to occur in the photoetching process, so that the data line, the source electrode and the drain electrode can adopt the multilayer film structure comprising the top metal layer in the embodiment of the invention to overcome the problems.
The array substrate in the embodiment of the invention can be a liquid crystal array substrate and can also be an OLED array substrate.
The embodiment of the invention also provides a display device which comprises the array substrate.
The embodiment of the invention also provides a manufacturing method of the thin film transistor, which is used for manufacturing the thin film transistor in any embodiment.
The embodiment of the invention also provides a manufacturing method of the array substrate, which is used for manufacturing the array substrate in any embodiment.
The following detailed description of embodiments of the present invention will be made with reference to the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a thin film transistor in the prior art, and the thin film transistor shown in fig. 1 includes: a substrate 11, a gate electrode 12, a gate insulating layer 13, an active layer 14, a source electrode 15, and a drain electrode 15'.
The source electrode 15 and the drain electrode 15' adopt a two-layer film structure, including: and a metal alloy layer 151 and a Cu wiring layer 152, wherein the metal alloy layer 151 is located below the Cu wiring layer 152, and is used for preventing the Cu wiring layer 152 from being oxidized and preventing Cu in the Cu wiring layer 152 from diffusing to the active layer 14. The metal alloy layer 151 is made of a MoNb alloy, that is, the film structures of the source electrode 15 and the drain electrode 15' are MoNb/Cu. The thickness of the metal alloy layer 151 was 300A, and the thickness of the Cu wiring layer was 3000A.
The gate electrode 12 also adopts a two-layer film structure including: a metal alloy layer 121 and a Cu wire layer 122, wherein the metal alloy layer 122 is located below the Cu wire layer 122, and is used for preventing the Cu wire layer 122 from being oxidized and preventing Cu in the Cu wire layer 122 from diffusing to the substrate 11. The metal alloy layer 122 is made of a MoNb alloy, that is, the film structure of the gate electrode 12 is MoNb/Cu.
In the thin film transistor with the structure, the source electrode 15 and the drain electrode 15' adopt a two-layer film structure, and the metal alloy layer is not protected above the Cu lead layer 152 and is easy to be oxidized.
Referring to fig. 2, fig. 2 is a schematic structural diagram of another thin film transistor in the prior art, and the thin film transistor shown in fig. 2 includes: a substrate base plate 21, a gate electrode 22, a gate insulating layer 23, an active layer 24, a source electrode 25, and a drain electrode 25'.
The source electrode 25 and the drain electrode 25' adopt a three-layer film structure, including: the metal alloy layer 251 is located below the Cu wire layer 252 and used for preventing the Cu wire layer 252 from being oxidized and preventing Cu in the Cu wire layer 252 from diffusing to the active layer 24, and the metal alloy layer 253 is located above the Cu wire layer 252 and used for preventing the Cu wire layer 252 from being oxidized. The metal alloy layer 251 and the metal alloy layer 253 are made of MoNb alloy, that is, the film structures of the source electrode 25 and the drain electrode 25' are MoNb/Cu/MoNb. The thickness of the metal alloy layer 251 is 300A, the thickness of the Cu wiring layer is 3000A, and the thickness of the metal alloy layer 253 is 200A.
The gate electrode 22 has a two-layer structure including: a metal alloy layer 221 and a Cu wiring layer 222, wherein the metal alloy layer 222 is located below the Cu wiring layer 222 for preventing the Cu wiring layer 222 from being oxidized and preventing Cu in the Cu wiring layer 222 from diffusing to the base substrate 21. The metal alloy layer 222 is made of a MoNb alloy, that is, the film structure of the gate electrode 22 is MoNb/Cu.
In the thin film transistor with the structure, the source electrode 25 and the drain electrode 25 ' adopt a three-layer film structure, in the process of performing a photolithography process, the adhesion between the metal alloy layer 253 on the top layer and the PR glue is low, and PR peeling is easy to occur, so that the metal alloy layer 253 on the top layer is lost, so that the Cu wire layer 252 becomes thin or the Profile (side) is too poor to conduct normally, and after the source electrode 25 and the drain electrode 25 ' are formed, the Cu wire layer is exposed in the air and is easy to be oxidized, in addition, when the thin film transistor with the structure is applied to an array substrate, a CVD (chemical vapor deposition) process is also needed to form the PVX layer after the source electrode 25 and the drain electrode 25 ' are formed, and in the CVD process, oxidizing gases such as O2 or N2O also cause oxidation corrosion to the Cu wire layer.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a thin film transistor according to an embodiment of the invention, and the thin film transistor shown in fig. 3 includes: a substrate 31, a gate electrode 32, a gate insulating layer 33, an active layer 34, a source electrode 35, and a drain electrode 35'.
The source electrode 35 and the drain electrode 35' adopt a four-layer film structure including: the metal wiring structure comprises a metal alloy layer 351, a Cu wiring layer 352, a metal alloy layer 353 and a top metal layer 354, wherein the metal alloy layer 351 is located below the Cu wiring layer 352 and used for preventing the Cu wiring layer 352 from being oxidized and preventing Cu in the Cu wiring layer 352 from diffusing to an active layer 34, the metal alloy layer 353 is located above the Cu wiring layer 352 and used for preventing the Cu wiring layer 352 from being oxidized, and the top metal layer 354 is located above the metal alloy layer 353. The metal alloy layer 351 and the metal alloy layer 353 are both made of MoNb alloy, and the top metal layer 354 is made of Cu, that is, the film structures of the source electrode 35 and the drain electrode 35' are MoNb/Cu/MoNb/Cu.
In the embodiment of the present invention, the thickness of the metal alloy layer 351 is 300A, the thickness of the Cu wiring layer 352 is 3000A, the thickness of the metal alloy layer 353 is 200A, and the thickness of the top metal layer 354 is 200A, which is thinner.
The gate electrode 32 has a two-layer structure including: a metal alloy layer 321 and a Cu wire layer 322, wherein the metal alloy layer 322 is located below the Cu wire layer 322 and is used for preventing the Cu wire layer 322 from being oxidized and preventing Cu in the Cu wire layer 322 from diffusing to the substrate 31. The metal alloy layer 322 is made of a MoNb alloy, that is, the film structure of the gate electrode 32 is MoNb/Cu.
In the thin film transistor in the embodiment of the invention, the source electrode 35 and the drain electrode 35' adopt a four-layer film structure, the top metal layer 354 is added above the metal alloy layer 353, and because the adhesive force between metal and PR glue is greater than that between metal alloy and PR glue, the PR glue is not easy to peel off in the photoetching process, thereby improving the yield of the thin film transistor.
When the thin film transistor in this embodiment is applied to an array substrate, a PVX layer needs to be formed over the source electrode 35 and the drain electrode 35', and since the thickness of the top metal layer 354 is relatively thin, the top metal layer 354 is not easily oxidized and corroded by an oxidizing gas such as O2 or N2O when the PVX layer is deposited by a CVD process, and even if oxidation occurs, the PVX layer is easily removed by plasma cleaning at dry etching because the oxide layer is relatively thin.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating an EPM (electrical property) comparison of a thin film transistor when a source electrode and a drain electrode of the thin film transistor respectively have a two-layer film structure, a three-layer film structure and a four-layer film structure. In fig. 4, the abscissa represents the gate voltage vg (v) and the ordinate represents the Drain Current (a). From the viewpoint of EPM, EPM of the thin film transistor having the source electrode and the drain electrode of the three-layer film structure and the four-layer film structure is good and almost overlapped, and Vth (threshold voltage) of the thin film transistor of the two-layer film structure is shifted and ss (sub-threshold amplitude) is not good.
Referring to fig. 5, fig. 5 is a schematic diagram of the EPM characteristics of the thin film transistor obtained by etching at different times when the source electrode and the drain electrode having the four-layer film structure in fig. 4 are formed according to the embodiment of the present invention, and it can be seen from fig. 5 that the EPM characteristics of the thin film transistor obtained after etching 72S and etching 85S are both good.
Referring to fig. 6, fig. 6 is a schematic diagram illustrating the performance of the thin film transistor obtained by etching at different times when the source electrode and the drain electrode having the four-layer film structure in fig. 4 are formed according to the embodiment of the present invention, in fig. 6, the abscissa is the etching time, the ordinate is the threshold voltage, Vth is the threshold voltage, and ss is the subthreshold amplitude, and it can be seen from fig. 6 that the performance of the thin film transistor obtained by etching at different times is substantially unchanged and is relatively stable.
Referring to fig. 7 to 13, fig. 7 to 13 are schematic diagrams illustrating a manufacturing method of an array substrate according to an embodiment of the invention, the manufacturing method includes:
step S11: referring to fig. 7, a gate electrode 102, a gate line (not shown), and a common electrode line wiring pattern 102' are formed on a substrate 101.
The forming process of the gate electrode 102 specifically includes:
and depositing a MoNb alloy film and a Cu metal film on the cleaned substrate 101 by using a magnetron sputtering process in sequence, wherein the thickness of the MoNb alloy film is 300A, and the thickness of the Cu metal film is 3000A.
Coating a layer of photoresist on the Cu metal film, exposing and developing the photoresist by using a mask plate to obtain a photoresist pattern, and wet-etching the MoNb alloy film and the Cu metal film to form a gate electrode 102, a gate line (not shown) and a common electrode line connection pattern 102 ', wherein the gate electrode 102 and the common electrode line connection pattern 102' both include: a metal alloy layer 1021 made of a MoNb alloy thin film, and a Cu wiring layer 1022 made of a Cu metal thin film.
Step S12: referring to fig. 8, a PECVD process is used to deposit the gate insulating layer 103, the gate insulating layer 103 may be a SiNx/SiON/SiO three-layer film structure with a thickness of 3100A, and the active layer 104 may be an oxide such as IGZO with a thickness of 700A.
Step S13: referring to fig. 9, a bottom MoNb alloy thin film, a Cu metal thin film, an intermediate MoNb alloy thin film, and a top Cu metal thin film are sequentially deposited by magnetron sputtering, where the top Cu metal thin film has a thickness of 400A, the intermediate MoNb alloy thin film has a thickness of 200A, the Cu metal thin film has a thickness of 3000A, and the bottom MoNb alloy thin film has a thickness of 300A, and then a source electrode 105, a drain electrode 105', a data line (not shown) and a common electrode line connection pattern 105 ″ having a four-layer film structure are formed by a patterning process. The source electrode 105, the drain electrode 105', the data line and the common electrode line connection pattern 105 ″ each include: metal alloy layer 1051 made of a bottom MoNb alloy thin film, Cu wire layer 1052 made of a Cu metal thin film, metal alloy layer 1053 made of an intermediate MoNb alloy thin film, and top metal layer 1054 made of a top Cu metal thin film.
Step S14: referring to fig. 10, a PECVD process is used to prepare the first passivation layer (PVX1)106 of 200n-400nm and form a via.
Step S15: referring to fig. 11, a first ITO film is deposited and patterned to form a common electrode 107;
step S16: referring to fig. 12, a second passivation layer (PVX2)108 is formed.
Step S17: referring to fig. 13, a second ITO film is deposited and patterned to form a pixel electrode 109.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. A thin film transistor comprising a conductive electrode, wherein the conductive electrode is a multilayer film structure, the multilayer film comprising at least: the metal wire layer is positioned between the top metal layer and the Cu wire layer, and the thickness of the top metal layer is smaller than a preset threshold value; the top metal layer is made of Cu; the thickness of the top metal layer is less than 500A.
2. The thin film transistor of claim 1, wherein the multilayer film structure further comprises: and the metal alloy layer is positioned below the Cu wire layer.
3. The thin film transistor of claim 2, wherein the thickness of the metal alloy layer between the top metal layer and the Cu wiring layer is in the range of 100-600A, the thickness of the Cu wiring layer is in the range of 2000-6000A, and the thickness of the metal alloy layer under the Cu wiring layer is in the range of 100-600A.
4. The thin film transistor of claim 1, wherein the conductive electrode comprises a source electrode and a drain electrode.
5. The thin film transistor according to claim 4, further comprising a gate electrode having a multi-layer film structure including at least a Cu wiring layer and a metal alloy layer under the Cu wiring layer.
6. The thin film transistor according to any one of claims 1 to 5, wherein the metal alloy is a molybdenum metal alloy.
7. An array substrate comprising the thin film transistor according to any one of claims 1 to 6.
8. A display device comprising the array substrate according to claim 7.
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| CN102664193A (en) * | 2012-04-01 | 2012-09-12 | 京东方科技集团股份有限公司 | Conductive structure, manufacturing method thereof, thin film transistor, array substrate, and display device |
| CN103531594A (en) * | 2013-10-30 | 2014-01-22 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN105789218A (en) * | 2016-03-10 | 2016-07-20 | 京东方科技集团股份有限公司 | Base plate and manufacturing method thereof and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102664193A (en) * | 2012-04-01 | 2012-09-12 | 京东方科技集团股份有限公司 | Conductive structure, manufacturing method thereof, thin film transistor, array substrate, and display device |
| CN103531594A (en) * | 2013-10-30 | 2014-01-22 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN105789218A (en) * | 2016-03-10 | 2016-07-20 | 京东方科技集团股份有限公司 | Base plate and manufacturing method thereof and display device |
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