CN106847670A - The manufacture method of semiconductor devices - Google Patents
The manufacture method of semiconductor devices Download PDFInfo
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- CN106847670A CN106847670A CN201710078922.8A CN201710078922A CN106847670A CN 106847670 A CN106847670 A CN 106847670A CN 201710078922 A CN201710078922 A CN 201710078922A CN 106847670 A CN106847670 A CN 106847670A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Chemical Kinetics & Catalysis (AREA)
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- Optics & Photonics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of manufacture method of semiconductor devices, including step：Semiconductor substrate is provided, thereon with raised semiconductor structure；The contact hole blocking layer of the covering semiconductor structure is formed on a semiconductor substrate；The first inter-level dielectric is formed on the contact hole blocking layer；Planarize first inter-level dielectric；The second inter-level dielectric is deposited on first inter-level dielectric, its composition is boron-phosphorosilicate glass or phosphorosilicate glass；Medium between third layer is deposited on second inter-level dielectric, so that it is flat to form dielectric layer surface, and without depression.
Description
Technical field
The present invention relates to semiconductor applications, more particularly to a kind of manufacture method of semiconductor devices.
Background technology
In inter-level dielectric, the effect of boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG) generally has two：One, is utilized
The mobility of BPSG and PSG, is filled out by Reflow Soldering (reflow) as the gap of preceding layer process (such as poly-silicon gap)
Fill.Two, using boron ion or phosphonium ion to the adsorptivity of impurity, prevent mobile ion (such as Na+, K+) in last part technology or
Influence of the high energy particle to leading portion device.
With the lasting micro (scaling down) of deep submicron process because in the gap of leading portion device often have compared with
Depth-to-width ratio high, the clearance filling capability of BPSG/PSG becomes not enough, the technique or with special insertion below 0.13 micron
In the technique of formula structure (such as embedded flash memory, disposable programmable memory or electric capacity etc.), high-density plasma is commonly used
The dielectric for learning vapor deposition (HDP CVD) is filled as gap.However, in embedded flash memory (embedded flash) or
In the technique platforms such as secondary property programmable storage (OTP), damascene structures have larger difference in height, and inter-level dielectric is carrying out chemistry
When mechanical polishing (CMP) is thinning, BPSG/PSG films may expose at the larger structure of difference in height, and due to BPSG/PSG
Grinding rate be much larger than silica, a big depression can be formed, so as to the device existing defects for resulting in.
The content of the invention
In order to solve the above technical problems, the invention provides a kind of manufacture method of semiconductor devices, solving interlayer Jie
The problem of matter depression.
The manufacture method of semiconductor devices of the invention includes step：
S21, there is provided semiconductor substrate, thereon with raised semiconductor structure；
S22, forms the contact hole blocking layer of the covering semiconductor structure on a semiconductor substrate；
S23, forms the first inter-level dielectric on the contact hole blocking layer；
S24, planarizes first inter-level dielectric；
S25, the second inter-level dielectric is deposited on first inter-level dielectric, and its composition is boron-phosphorosilicate glass or phosphorus silicon glass
Glass；
S26, the medium between deposit third layer on second inter-level dielectric.
Optionally, first inter-level dielectric is to utilize high-density plasma chemical vapor deposition.
Optionally, it is using chemically mechanical polishing to planarize first inter-level dielectric.
Optionally, also include after the second inter-level dielectric is formed and carry out the flow back boron-phosphorosilicate glass or phosphorosilicate glass.
Optionally, medium is the oxygen of the SiH4 or TEOS formation deposited in the method for chemical vapor deposition between deposit third layer
SiClx film.
Optionally, the deposition thickness of medium measures thickness dynamically adjustment with front layer between the third layer.
Optionally, the semiconductor devices is flush memory device or disposable programmable read only memory device.
Compared with prior art, advantage is the present invention：
The present invention is initially formed contact hole blocking layer the step of form inter-level dielectric by adjustment, is then formed on the
One inter-level dielectric, then planarizes the first inter-level dielectric, and boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG) material are re-formed afterwards
Second inter-level dielectric of material, medium between third layer is then formed on the second inter-level dielectric, so that it is flat to form dielectric layer surface,
And without depression.
Brief description of the drawings
Drawings below of the invention is in this as a part of the invention for understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining principle of the invention.
Fig. 1 is the manufacture method flow chart of semiconductor devices；
Fig. 2~Fig. 7 is the manufacture method schematic diagram of semiconductor devices of the invention.
Specific embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From start to finish
Same reference numerals represent identical element.
In inter-level dielectric, the effect of boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG) generally has two：One, is utilized
The mobility of BPSG and PSG, is filled by Reflow Soldering (reflow) as the gap of preceding layer process (such as poly gap).Two, profits
With Boron or Phosphorus to the adsorptivity of impurity, mobile ion (such as Na+, K+) or the high energy in last part technology are prevented
Influence of the particle to leading portion device.
With the lasting micro (scaling down) of deep submicron process, the clearance filling capability of BPSG/PSG becomes not
Foot, below 0.13 micron in technique or the technique with special damascene structures (such as embed flash, OTP etc.),
The dielectric of conventional high-density plasma chemical vapor deposition (HDP CVD) is filled as gap.However, in flash memory or once
In the technique platforms such as programmable read only memory, damascene structures have larger difference in height, and inter-level dielectric is carrying out chemical machinery
When polishing (CMP) is thinning, BPSG/PSG films may expose at the larger structure of difference in height, and grinding due to BPSG/PSG
Mill speed is much larger than silica, a big depression can be formed, so as to the contact for causing many technological problemses to be for example subsequently formed
Defect of hole and metal level etc..
The invention provides inter-level dielectric (ILD) manufacturing process of one kind without depression (dishing free).
The manufacture method to semiconductor devices of the invention is described in detail below in conjunction with the accompanying drawings.
With reference to Fig. 1, the manufacture method of semiconductor devices of the invention includes step：
The manufacture method of semiconductor devices of the invention includes step：
S21, there is provided semiconductor substrate, thereon with raised semiconductor structure；
S22, forms the contact hole blocking layer of the covering semiconductor structure on a semiconductor substrate；
S23, forms the first inter-level dielectric on the contact hole blocking layer；
S24, planarizes first inter-level dielectric；
S25, the second inter-level dielectric is deposited on first inter-level dielectric, and its composition is boron-phosphorosilicate glass or phosphorus silicon glass
Glass；
S26, the medium between deposit third layer on second inter-level dielectric.
Optionally, first inter-level dielectric is to utilize high-density plasma chemical vapor deposition.
Optionally, it is using chemically mechanical polishing to planarize first inter-level dielectric.
Optionally, also include after the second inter-level dielectric is formed and carry out the flow back boron-phosphorosilicate glass or phosphorosilicate glass.
Optionally, medium is the oxygen of the SiH4 or TEOS formation deposited in the method for chemical vapor deposition between deposit third layer
SiClx film.
Optionally, the deposition thickness of medium measures thickness dynamically adjustment with front layer between the third layer.
Optionally, the semiconductor devices is flush memory device or disposable programmable read only memory device or electric capacity etc..
With reference to Fig. 2, step S21 is performed, there is provided semiconductor substrate, the semiconductor base includes Semiconductor substrate 100,
The material of the Semiconductor substrate 100 can be monocrystalline silicon, polysilicon or silicon compound, or GaAs or gallium nitride
Deng compound, in the present embodiment, preferred Semiconductor substrate 100 is monocrystalline silicon.There is semiconductor on a semiconductor substrate 100
Structure 101, the semiconductor structure 101 can be to be formed using semiconductor technology method known in the art.In this implementation
In example, the semiconductor structure 101 can be memory cell.The memory cell protrudes the semiconductor substrate surface.
In the present embodiment, the preferred semiconductor structure is memory device, and such as flush memory device or flash memory are once
Programmable read only memory part.
With reference to Fig. 3, step S22 is performed, covering Semiconductor substrate 100 and semiconductor junction are formed on the semiconductor base
The contact hole blocking layer 102 of structure 101, specifically, it is possible to use the method for chemical vapor deposition is formed.Connect in semiconductor fabrication
Contact hole technique is a very important ring, and contact hole technique is mainly divided into three steps, and forms contact on a semiconductor substrate first
Hole opening, forms barrier layer afterwards, eventually forms metal level.For semiconductor devices, the contact resistance of contact hole is one
The important electrical characteristic parameter of item.It is well known that semiconductor devices will have good electrical characteristic, the contact resistance of contact hole will
Ask small, and the barrier layer in contact hole has a great impact to the contact resistance of contact hole.In the present embodiment, the contact hole
In intercept layer process in using Ti/TiN as the barrier layer in contact hole, the barrier layer in contact hole is divided into two-layer, first
Layer Ti is adhesive layer, and second layer TiN is barrier layer, and Ti and TiN is formed using the mode of physical vapour deposition (PVD) (PVD).Wherein,
The adhesion of Ti and Si is good, and Ti and Si reaction generation TiSi2, and contact resistance is small, and barrier layer TiN is prevented from Ti rear
Reacted with other materials in continuous technical process.
With reference to Fig. 4, perform step S23 and the first inter-level dielectric 103 is formed on the contact hole blocking layer 102.In this reality
Apply in example, be that silica, the two of the formation are formed using high-density plasma chemical vapor deposition (HDP-CVD) technique
Silicon oxide layer has projection in the position of the semiconductor structure.HDP-CVD techniques are normal during semiconductor integrated circuit is manufactured
With one of technique, the characteristics of with that can also be performed etching while deposit, therefore, existing HDP-CVD techniques are generally used for filling out
The gap with depth-to-width ratio high is filled, such as intermetallic dielectric layer can be filled with the silicon dioxide layer of HDP-CVD techniques formation
(PMD), before-metal medium layer (IMD), the gap of shallow trench isolation (STI).In the present embodiment, it is using HDP-CVD techniques
Deposit forms pad silicon dioxide layer (Liner Oxide), during deposit under lower pressure, is passed through process gas, and addition is penetrated
Frequently (RF) source and growth is just proceeded by after producing high-density plasma；The flow of wherein process gas is to use mass flowmenter
(Mass Flow Controller, MFC) is controlled, and process gas includes silicon source such as silane, oxygen source such as oxygen and lazy
Property gas such as argon gas；Radio frequency can include top source radio frequency, side source radio frequency and bias radio frequency, wherein top source radio frequency, side source radio frequency
One uniform electromagnetic field can be provided so that produce high-density plasma be uniformly distributed, bias radio frequency can make high density
Surface transport from the material of plasma to silicon chip and can deposit when realize sputtering.Under 2 millitorr~10 millitorr lower pressures,
The ion concentration of produced high-density plasma can reach 1011CM-3~1012CM-3.Wherein, described high density etc.
Gas ions can make cavity (Chamber) and silicon chip (wafer) heat up, and the initial temperature setting of the cavity of HDP-CVD is all compared
It is low, it is set as 100 DEG C~200 DEG C；After the heating of the high-density plasma, the temperature of silicon chip can reach 600 during deposit
More than DEG C, such as 640 DEG C~720 DEG C.So as to realize good covering semiconductor structure and filling groove by HDP-CVD techniques
Ability.
With reference to Fig. 5, step S24 is performed, planarize first inter-level dielectric 103.In the present embodiment, planarization is to adopt
With the method for chemically mechanical polishing, specifically, including step：Chemical mechanical polishing pads are provided, it is included：Polyurethanes is thrown
Photosphere；Wherein described polyurethanes polishing layer is chosen with composition, basal surface and polished surface；Wherein described poly- ammonia
Carbamate polishing layer composition represents >=0.5mg (KOH)/g, and such as 0.5 arrives 25mg (KOH)/g；Wherein described polished surface
It is adapted for polishing substrate；Abrasive slurry is provided, wherein the abrasive slurry includes water and ceria abrasive；Will
The substrate and the chemical mechanical polishing pads are arranged in the polishing machine；In the chemical mechanical polishing pads and the substrate
Between interface formed dynamic Contact；And the abrasive slurry is assigned to the throwing of the chemical mechanical polishing pads
The interface between the chemical mechanical polishing pads and the substrate is located near or on the polished surface of photosphere；Until described
The projection of semiconductor structure position is smoothed so that the surface of semiconductor base is in a plane 201.
With reference to Fig. 6, step S25 is continued executing with, the second inter-level dielectric 104 is deposited on first inter-level dielectric 103, its
Composition is boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).
In the present embodiment, it is method using high density plasma CVD, one layer 1000 of deposit~
The PSG films of 2000 Ethylmercurichlorendimides, deposition conditionses：Air pressure is 3~15 millitorrs, and power is 2000~3000 watts, and reacting gas is O2 (oxygen
Gas), the mixed gas of SiH4 (silane) and PH3 (phosphine), bombarding gas be Ar (argon gas) or He (helium), reaction temperature is general
Control is at 400~600 degrees Celsius.
In another embodiment, it is also possible to use sub-atmospheric pressure chemical gaseous phase depositing process, by TEOS, TEPO (tricresyl phosphate second
Ester), after the gasification of TEB (triethyl borate) these three reaction liquids, enter to be passed through in board and reacted with He is airborne, deposit one layer
Thickness is the BPSG films of 1000~2000 Ethylmercurichlorendimides.Deposition conditionses are：The support of air pressure 200~600, reaction temperature control 400~
500 degrees centigrades.In addition can also, using the laminated construction of PSG and BPSG.
In the present embodiment, specifically, second inter-level dielectric is formed in the plane 201 of semiconductor base.
Preferably, also include being flowed back (reflow) to strengthen filling effect after second inter-level dielectric is formed.
With reference to Fig. 7, step S26 is continued executing with, medium 105 between depositing third layer on second inter-level dielectric 104,
In the present embodiment, medium 105 is the silica of the SiH4 or TEOS formation deposited in PECVD methods between preferred deposit third layer
Film.
Optionally, the deposition thickness of medium 105 can measure thickness dynamically adjustment with front layer between the deposit third layer, with
It is worth after obtaining the ILD thickness of stabilization, for example, its thickness is measured after the first inter-level dielectric 103 is formed, and forms the
It is measured after two inter-level dielectrics 104, the thickness adjustment of thickness and the second inter-level dielectric according to the first inter-level dielectric
The thickness of medium between third layer, keep the first inter-level dielectric, between the second inter-level dielectric and third layer medium gross thickness sum protect
Hold constant.
Specifically, being selected from 300~400W, SiH4 gas flows (SiH 4) heretofore described radio-frequency power (RF)
With 60~70sccm, substrate is 280mil fixed values, reaction to the distance between gas spray (Spacing) in reaction cavity
Cavity internal pressure (Pressure) is 3.8Torr fixed values, and depositing temperature is 400 DEG C.
Reacting gas in technical scheme of the present invention can select SiH4, the i.e. program and be applied to SiH4based dioxies
The deposition of SiClx film；Reacting gas can also select the TEOS (tetraethyl silica) through vaporizing, i.e., the program is also applied for
The deposition of TEOS based silica membranes.
In the present embodiment, it is preferred that follow-up also to include step：Using the first inter-level dielectric is formed with, the second interlayer is situated between
The semiconductor base of medium forms semiconductor storage unit between matter and third layer.Those skilled in the art institute can specifically be used
Familiar semiconductor fabrication process, repeats no more.
Obviously, those skilled in the art can carry out various changes and modification without deviating from spirit of the invention to invention
And scope.So, if these modifications of the invention and modification belong to the claims in the present invention and its equivalent technologies scope it
Interior, then the present invention is also intended to comprising these changes and modification.
Claims (10)
1. a kind of manufacture method of semiconductor devices, it is characterised in that including step：
Semiconductor substrate is provided, thereon with raised semiconductor structure；
The contact hole blocking layer of the covering semiconductor structure is formed on a semiconductor substrate；
The first inter-level dielectric is formed on the contact hole blocking layer；
Planarize first inter-level dielectric；
The second inter-level dielectric is deposited on first inter-level dielectric, its composition is boron-phosphorosilicate glass or phosphorosilicate glass；
Medium between depositing third layer on second inter-level dielectric.
2. the manufacture method of semiconductor devices according to claim 1, it is characterised in that first inter-level dielectric is profit
Use high-density plasma chemical vapor deposition.
3. the manufacture method of semiconductor devices according to claim 1, it is characterised in that planarization first interlayer is situated between
Matter is using chemically mechanical polishing.
4. the manufacture method of semiconductor devices according to claim 1, it is characterised in that after the second inter-level dielectric is formed
Also include and carry out the flow back boron-phosphorosilicate glass or phosphorosilicate glass.
5. the manufacture method of semiconductor devices according to claim 1, it is characterised in that between deposit third layer medium be with
The silicon oxide film that the SiH4 or TEOS of the method deposit of chemical vapor deposition are formed.
6. the manufacture method of semiconductor devices according to claim 1, it is characterised in that the shallow lake of medium between the third layer
Product thickness measures thickness and dynamically adjusts with front layer.
7. the manufacture method of semiconductor devices according to claim 1, it is characterised in that the semiconductor structure is insertion
Formula memory device or electric capacity etc..
8. the manufacture method of semiconductor devices according to claim 7, it is characterised in that the memory device is embedded
Flush memory device.
9. the manufacture method of semiconductor devices according to claim 7, it is characterised in that the memory device is once may be used
Program read-only memory part.
10. the manufacture method of semiconductor devices according to claim 1, it is characterised in that also including step：Using formation
There is the first inter-level dielectric, the semiconductor base of medium forms semiconductor storage unit between the second inter-level dielectric and third layer.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113675327A (en) * | 2021-07-23 | 2021-11-19 | 无锡莱斯能特科技有限公司 | Manufacturing method of thermopile sensor |
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| CN101521159A (en) * | 2008-02-29 | 2009-09-02 | 中芯国际集成电路制造(上海)有限公司 | Method for improving the uniformity of disc and interlayer medium |
| CN101740377A (en) * | 2009-11-26 | 2010-06-16 | 上海宏力半导体制造有限公司 | Filling method of doped interlayer medium with high depth-to-width ratio gap |
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| CN1181628A (en) * | 1996-10-30 | 1998-05-13 | 三星电子株式会社 | Method for manufacturing semiconductor memory device having self-aligned contact |
| US20050282395A1 (en) * | 2004-06-16 | 2005-12-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming an improved low power SRAM contact |
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| CN113675327A (en) * | 2021-07-23 | 2021-11-19 | 无锡莱斯能特科技有限公司 | Manufacturing method of thermopile sensor |
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Application publication date: 20170613 |