CN106847181A - Data wire to pel array enters the device and method of line precharge - Google Patents
Data wire to pel array enters the device and method of line precharge Download PDFInfo
- Publication number
- CN106847181A CN106847181A CN201510895945.9A CN201510895945A CN106847181A CN 106847181 A CN106847181 A CN 106847181A CN 201510895945 A CN201510895945 A CN 201510895945A CN 106847181 A CN106847181 A CN 106847181A
- Authority
- CN
- China
- Prior art keywords
- data wire
- precharge
- pel array
- switch
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present invention relates to the device and method that the data wire to pel array enters line precharge, including first, second, and third test cabling, pel array includes multiple data wires and the multiple sub-pixel circuits positioned at same row in pel array share same data line, wherein any one data line is connected to described first, second, and third one tested in cabling this three by a first switch.
Description
Technical field
Present invention is primarily about field of display, more precisely, being to propose one kind to picture
The data wire of pixel array enters the device and method of line precharge.
Background technology
In the prior art, with consumer and the actual thriving demand in market, for example, can wear
Wear on the product of equipment and the relatively low small size panel display of resolution requirement, in order to
The overall dimensions and cost of electronic equipment are reduced, often by a data lines of driving chip
Output is connected to a plurality of data lines of display pannel simultaneously, such that it is able to substantially reduce for carrying
For total output port quantity and the bar number of data line of the driving chip of data voltage signal, finally
Realize reducing the cost of driving chip.In the AMOLED pixel compensations electricity of this application of arranging in pairs or groups
Lu Zhong, must do a precharge to data wire and move before every a line sub-pixel formally charges
Make, otherwise can have influence on the normal of picture in last moment remaining voltage because of data wire
Display.It is currently that precharge is realized to arrange in pairs or groups data voltage by the switch configured on data wire
Function, opens all switches in pre-charging stage, while data line voltage needs to reduce in the lump
Current potential performs pre-charge operation with to data wire, but the method makes the control sequential of switch and data
The signal intensity of line becomes complicated, the true charging interval of electric capacity in influence image element circuit, and
And can also increase the extra power consumption of driving chip.
The content of the invention
In one alternate embodiment, the present invention provides a kind of data wire to pel array and carries out
The device of precharge, including first, second, and third test being arranged on around pel array is walked
Line and one precharge control line, the pel array include a plurality of data wire, and
Multiple sub-pixel circuits in the pel array positioned at same row share data described in same
Line, wherein any one data wire be connected to described first by a first switch,
Second and the 3rd tests one of cabling three, and the first switch is all connected to the precharge
Control line.
Used as a preferred embodiment, above-mentioned device also includes a driving chip, described
The each data wire in pel array is connected to the drive by a second switch
Dynamic chip, makes the data wire according to the connection of the second switch or off-state to select to be
It is no from the driving chip acquisition data voltage signal.
Above-mentioned device, in a pre-charging stage of the data wire, described first,
Input has the first reference potential on two and the 3rd test cabling, and the second switch breaks
Open, the first logic level being applied on the precharge control line connects the first switch
It is logical, so as to perform precharge to the data wire and be clamped down in the first reference potential.
Above-mentioned device, the first, second, and third test cabling is all connected to the driving
Chip, and the first reference potential of precharge is provided by the driving chip for the data wire.
Above-mentioned device, the precharge control line is connected to the driving chip, and by described
The driving chip control precharge control line switches between first, second logic level, its
Described in precharge control line only overturn to first logic level in the pre-charging stage,
Overturn to second logic level in other time periods.
Above-mentioned device a, end of the first, second, and third test cabling connects respectively
A pad is connected to, test signal is applied to the data wire by the pad, for testing
Corresponding sub-pixel circuits.
Above-mentioned device a, end of the precharge control line is connected with a pad.
As a preferred embodiment, panel test circuit is utilized present invention also provides one kind
The method that precharge is performed to the data wire of pel array, the panel test circuit includes the
First, second and the 3rd test cabling, the pel array include multiple data wires and
Multiple sub-pixels in the pel array positioned at same row share data wire described in same, appoint
One data wire of meaning is connected to described first, second, and third by a first switch
One of test cabling three；
The described method comprises the following steps：
Arbitrarily selected one group of sub-pixel circuits in the pel array, one group of sub-pixel electricity
Before being lighted successively in the Lu Yi frame periods, a precharge step is first carried out, by described one group
The data wire of each sub-pixel circuits is using described first, second and the in sub-pixel circuits
Three test one of cabling threes to clamp down in first reference potential.
Above-mentioned method a, there is provided driving chip, by each institute in the pel array
State data wire and the driving chip is connected to by a second switch；And
By controlling the connection or disconnection of the second switch, so as to choose whether to make the data
Line is according to from the driving chip acquisition data voltage signal.
Above-mentioned method, in the precharge step, first described first, second, and third
First reference potential is input on test cabling；And
The second switch is disconnected, while applying the first logic electricity on the precharge control line
It is flat, so as to all of first switch all be connected, perform to data wire precharge simultaneously
Its potential is clamped down in first reference potential.
Above-mentioned method, the drive is all connected to by described first, second, and third test cabling
Dynamic chip, and provide institute from the driving chip to described first, second, and third test cabling
State the first reference potential.
Above-mentioned method, is connected to the driving chip, using institute by the precharge control line
The driving chip control precharge control line is stated to switch between first, second logic level；
In precharge step, the current potential of the precharge control line is controlled to switch to described first
Logic level, the other times section beyond the precharge step then controls the preliminary filling automatically controlled
The current potential of line processed switches to second logic level.
Brief description of the drawings
Read after described further below and reference the following drawings, feature and advantage of the invention will
Obviously：
Fig. 1 is the sequential that prior art is pre-charged using multiple switch to data wire.
Fig. 2 is the circuit diagram that driving chip provides voltage to data wire.
Fig. 3 is the circuit diagram that the present invention enters line precharge using panel test circuit to data.
Fig. 4 is the timing diagram that the present invention is pre-charged using panel test circuit to data wire.
Specific embodiment
Below in conjunction with each embodiment, clearly complete explaining is carried out to technical scheme
State, but described embodiment is only the present invention embodiment being described herein used by explanation rather than complete
The embodiment in portion, based on the embodiment such as this, those skilled in the art is not making creativeness
The scheme obtained on the premise of work belongs to protection scope of the present invention.
Referring to Fig. 1 and Fig. 2, the application temporarily with provide six timing control signal S1 extremely
S6 illustrate logarithm in the prior art as a example by control six switch SW1 to SW6 to correspond to
Enter the device of line precharge according to line, it is notable that timing control signal or switch here
Particular number is as just example but not constitutes restrictive condition of the invention.Generally, for
The data wire of pel array is provided in the scheme of drive signal, and industry can utilize a driving chip
A piece passage IC channel data wire of IC promotes many of pel array in display panel
Data wire panel data line, because, if we are only setting driving chip IC
Channel data line and pel array the data wire data one-to-one connections of line if, this is undoubtedly
May require that driving chip IC has numerous output ports to correspond to numerous numbers of display panel
According to line, cause the size of driving chip IC relatively excessive, and then be difficult to be set in portable electronic
Version is realized on the panel of such requirement small size display screen curtain such as standby or wearable device
The minimum optimization layout of figure, so in general, industry is advocated to make on small size electronic product
Three single datas of pel array are connected to the channel data line correspondence of driving chip IC
Line or correspondence are connected to the six roots of sensation data wire of pel array, or even correspondence is connected to pixel battle array
Nine data lines of row, the output port for thereby reducing driving chip IC carrys out size reduction.Just
As shown in Fig. 2, do not illustrate of driving chip 110 IC channel data line
Six roots of sensation data wire D1~D6, the driving in the pel array of display panel can be simultaneously coupled to
Chip 110 provides them data voltage signal Data voltage, because every in pel array
The stabling current of the light-emitting component of individual sub-pixel circuits depends on the size of the data voltage signal.
Referring to Fig. 2, it is both provided with each data lines in volume of data line D1~D6
One electronic switch, note here so-called switch in general have first end, one
Second end and a control end, control end can be controlled between the first end of the switch and the second end
Turn on and off.For example we are opened with one be correspondingly arranged on a data wire D1 now
Close as a example by SW1, the first end of switch SW1 is used to receive the number of the transmission of driving chip 110
According to voltage signal, and second end of switch SW1 then corresponds to and is connected to certain sub-pixel circuits
The input Data input of the data voltage signal of PX1, once switch SW1 is switched on, drive
The data voltage signal of the dynamic transmission of chip 110 smoothly can be just transferred to by data wire D1
The sub-pixel circuits PX1 of data wire D1 is connected in, vice versa, switch SW1 is closed
Then data wire D1 cannot be from the acquisition data voltage signal of driving chip 110 when disconnected.In order to keep away
Exempt from the understanding difference caused because term or wording are different, generally so-called sub-pixel is electric here
Road PX1 is sometimes referred to as pixel compensation circuit.We referring still to shown in Fig. 2, with number
It is similar according to line D1, if also corresponded on other some data wire D2~D6 being respectively arranged with
Dry electronic switch SW2~SW6, and grade data wire D2~D6 and multiple sub-pixel circuits
PX2~PX6 also it is man-to-man correspondence connection, in view of switch SW2~SW6 working mechanism with
Switch SW1 on data wire D1 is essentially identical, therefore it will not go into details here.
In Fig. 1, the data voltage signal DLIN for being provided by driving chip IC can be by number
The data voltage signal input of sub-pixel circuits is transferred to according to line, and in AMOLED pixels
In compensation circuit, the concrete scheme for performing the precharging procedure of data wire is embodied in, in frame week
Before phase formally lights the light-emitting component of each sub-pixel circuits, data voltage signal DLIN
From high potential Pre-charge time periods T can be pre-charged at onePRELow potential is turned to, for example
Ground connection GND.In order to explain this point, we are clear from still by taking Fig. 2 as an example now,
Every a line sub-pixel circuits of pel array must be entered to data wire in advance before carrying out formal charging
Line precharge, for example for the one group of sub-pixel circuits PX1~PX6 selected in certain a line
Speech, before preparing formally to light sub-pixel circuits PX1~respective light-emitting components of PX6 successively,
An action for precharge must be implemented to data wire D1~D6 in advance, in time period TPREBy number
Be pulled down to low potential according to line D1~D6, just formally light light-emitting component successively thereafter, this be because
For parasitic capacitance of coupling etc. induces remaining at the previous frame moment on data wire D1~D6 to be avoided
Magnitude of voltage have influence on the normal display of the picture when former frame.
In order to realize the pre-charge operation for referring to, at least it is required to meet at 2 points, first, in preliminary filling
The time period T of electricityPRE, switch SW1~SW6 and synchronously connected.Second, the grade switch
While SW1~SW6 is switched on, driving chip 110 is conveyed to the number of data wire D1~D6
According to voltage signal DLIN in time period TPRELow potential must be reduced to.Consequently, it is possible to number
Low potential just can be reduced to according to line D1~D6, so that implement expected preliminary filling electroresponse, quite
Current potential in refreshing or initialization data line D1~D6.We are with the PMOS of use herein
As a example by thin film transistor switch SW1~SW6, in time period TPREIt is not only driving chip 110
Being conveyed to the data voltage signal DLIN of data wire D1~D6 needs to be turned to low potential, also
Six timing control signals for making correspondence be applied in the control end of each switch SW1~SW6
S1~S6 also must synchronously be turned to logic low potential, so as in time period TPREWill switch
SW1~SW6 is connected, and makes the data voltage signal DLIN that driving chip 110 is provided in this stage
Smoothly can be delivered on each data wire D1~D6 via each switch SW1~SW6.
In a frame period, time period TPREAfter end, just continuous time on a timeline
Section T1~T6 lights sub-pixel circuits PX1~respective light-emitting components of PX6 respectively successively.When
Between section T1, timing control signal S1 is turned to low level and carrys out ON switch SW1 by high level,
And be connected with data wire D1 is lighted by the data voltage signal on data wire D1
Light-emitting component (such as color is red R) in individual image element circuit PX1, the time period, T1 terminated it
Timing control signal S1 is back to high level afterwards.By this rule, the rest may be inferred, behind when
Between section T2, timing control signal S2 is turned to the switch SW2 that low level is connected on data wire D2,
Light in the image element circuit PX2 being connected with data wire D2 light-emitting component (such as color for green
G), timing control signal S2 is back to high level after time period T2 terminates.Equally, at it
Time period T3 afterwards, timing control signal S3 are turned to low level and connect opening on data wire D3
SW3 is closed, light-emitting component (such as face in the image element circuit PX3 being connected with data wire D3 is lighted
Color is blueness B), timing control signal S3 is back to high level after time period T3 terminates.Cause
In time period T1~T3, we realize the lighting timings control of RGB for this.In order to be unlikely to repeat
Repeat with T1~T3 identical light emitting control modes, the SECO mode of time period T4~T6 compared with
It is being presented as omitting, time period T4 timing control signal S4 lights what is be connected with data wire D4
Light-emitting component (such as color is red R) in image element circuit PX4, the SECO of time period T5
Signal S5 lights light-emitting component (such as color in the image element circuit PX5 being connected with data wire D5
It is green G), time period T6, timing control signal S6 lighted the pixel being connected with data wire D6
Light-emitting component (such as color be blueness B) in circuit PX6, thus time period T4~T6 I
Again repeat realize RGB lighting timings control.
But very unfortunately, it is desirable in the time period T of prechargePREEach switch SW1~SW6
Synchronously connected, and required that driving chip 110 is conveyed to the data electricity of data wire D1~D6
Pressure signal DLIN synchronously jumps to low potential, and this is for driving chip 110 or pin
For driving the timing control signal S1~S6 of each switch SW1~SW6, can undoubtedly make driving
Big and timing control signal S1~S6 the operational control of the operation power consumption of chip 110 is complicated, condition
And the mode of operation of this precharge in itself can be since it is desired that expending many times and postponing a little
The smooth degree of brighten the hair optical element.So we will face these it is urgently to be resolved hurrily the drawbacks of,
How on the premise of the power consumption of driving chip 110 is not increased, strongly simplify number in pel array
According to the precharging procedure of line, and ensuing disclosure will in detail explain present invention spirit, carry
Technical scheme for solving technical problem present in prior art.
Referring to Fig. 3, for the facility for understanding, with the picture of full HD display FHD panel constructions
Illustrated as a example by the layout of pixel array, usual pel array 120 and panel test circuit Panel
Test can be typically arranged on a substrate, additionally explained here, panel test circuit
Be in order to measure the functional stabilization of the sub-pixel circuits of pure color/or monochrome, such as it is pure red or pure
Green or ethereal blue monochrome, so that for monochrome sub-pixels circuit provides corresponding test signal.In picture
In pixel array 120, each data wire DL1, DL2, DL3 ... of driving chip 110 are connected to
The sub-pixel circuits that DLm is respectively different lines provide data voltage signal.Can arbitrarily choose
Sub-pixel circuits P11, P21 of the first row in pel array 120, P31 ... Pn1 (n
It is greater than the natural number equal to 1) as research object, the sub-pixel circuits P11 of first row,
P21, P31 ... the public same data line DL1 of Pn1, driving chip 110 utilize this
The sub-pixel circuits that data wire DL1 is respectively this row provide data voltage signal.
Panel test circuit includes that layout tests cabling the first of the periphery of pel array 120
101st, the second test test cabling 103 of cabling 102 and the 3rd, additionally, also additionally with the addition of
One precharge control line 104.In the present invention, in order to farthest reduce the size and not
The general domain of influence standard, first, we test the He of cabling 101 by substantially parallel first
The 3rd test respective Part I cabling of cabling 103 is arranged in the left side week of pel array 120
Border area domain is simultaneously parallel with left side edge, and the first test cabling 101 and the 3rd is tested into cabling
103 respective Part II cablings be arranged in the front periphery region of pel array 120 and with it is preceding
Edge is parallel.Furthermore, also by substantially parallel the second test cabling 102 and precharge control line
104 respective Part I cablings be arranged in the right periphery region of pel array 120 and with the right side
Lateral edges are parallel, and by the second test cabling 102 and are pre-charged control line 104 respective second
Part cabling is arranged in the front periphery region of pel array 120 and parallel with leading edge.Usual
In the case of driving chip 110 can be arranged in the rear side of pel array 120.In addition, as panel
The conventional design of test circuit a, end of the first test cabling 101 is electrically connected to substrate
On one be located in the test pads (Test pad) 111 of the rear side of pel array 120, the 3rd
An end for testing cabling 103 is electrically connected to one on substrate and is located at pel array 120
In the test pads 113 of rear side, an end of the second test cabling 102 is electrically connected to base
One on plate is located in the test pads 112 of the rear side of pel array 120.As option
Optionally item, is pre-charged an end of control line 104 can be electrically connected on substrate one
On the individual added with padding 114 on rear side of pel array 120.
Inform above, original effect of panel test circuit is to test the sub- picture of each monochrome
Plain circuit, it is substantial that we can apply test signal in these test pads 111~113,
Such as first test cabling 101 is mainly used in the sub-pixel for the first color (such as Red)
Data wire provides the sub-pixel circuits that test signal lights corresponding color to test, and second tests
Cabling 102 is mainly used in being provided for the data wire of second sub-pixel of color (such as Green)
Test signal lights the sub-pixel circuits of corresponding color to test, and the 3rd test cabling 103 is main
Data wire for the sub-pixel for the third color (such as Blue) provides test signal to test
Light the sub-pixel circuits of corresponding color.But the present invention is not limited by panel test circuit
These original test functions, are on the contrary on the premise of not influenceing panel test circuit basic function
The program of extra precharge is also performed by panel test circuit.
Referring to Fig. 3, the present invention also use one group of switch SWP1, SWP2 ... SWPm
(m is greater than the natural number equal to 1) etc., alternatively these switches are disposed in
The front periphery region of pel array 120, and these switch can also be with first end,
Second end and the PMOS thin film transistor (TFT)s of control end, first is controlled by the signal of control end
Shut-off or connection between end (such as source electrode) and the second end (as drained).Data wire (DL1,
DL2, DL3 ... DLm) in any one data line be required to be opened by as one
Connection is connected to the first test cabling 101, second and tests the test cabling 103 of cabling 102 and the 3rd
One of this three, so as to the action of precharge can benefit it is each in pel array 120
Data line.Specifically, the public data line of the sub-pixel circuits of such as first row
DL1 is connected to second end of switch SWP1, and the first end for switching SWP1 is then connected to
Second test cabling 102 is parallel on the Part II of forward edge.The sub-pixel electricity of secondary series
The public data line DL2 in road is connected to second end of switch SWP2, and switchs SWP2
First end be connected to the 3rd test cabling 103 parallel on the Part II of forward edge.Again
As the public data line DL3 of tertial sub-pixel circuits is connected to switch SWP3's
Second end, and the first end for switching SWP3 is connected to the first test cabling 101 parallel to front side
On the Part II at edge.The sub-pixel circuits of the rest may be inferred ... ... m row it is public one
The first end that data line DLm is connected to the second end for switching SWPm and switchs SWPm
It is connected to first test cabling 101 ... ... etc..The group switch SWP1, SWP2 ...
The control end of SWPm is all connected to precharge control line 104 parallel to the second of forward edge
On part.
It is automatically controlled by preliminary filling in Fig. 3 in order to avoid causing to understand deviation because of term or obscuring of exhaling
On line processed 104 apply control signal control one group of switch SWP1, SWP2 ...
The type of SWPm is defined as first switch, by timing control signal S1~S6 controls in Fig. 2
The type of the switch SW1~SW6 of system is defined as second switch.
Ingenious part of the invention is that the first test cabling 101, second tests cabling 102
It is all connected to driving chip 110 and provides one by driving chip 110 with the 3rd test cabling 103
Individual first reference potential DREFTo them.As a kind of simplified measure, the first reference potential DREF
Can maintain always in high or low logic state, namely logic state fixed and need not in height
Switch between low level.In actual applications, as data wire (DL1, DL2, DL3 ...
DLm) in the time period T of prechargePREIt is expected to need great voltage, then the first reference potential
DREFJust it is set as corresponding magnitude of voltage, is typically for example set as ground potential GND.In order to more
The operating mechanism of detailed understanding the application, or explained with reference to Fig. 2, at certain
For the one group of sub-pixel circuits PX1~PX6 selected in a line, when preparation is formally lighted successively
Before sub-pixel circuits PX1~respective light-emitting components of PX6, it is necessary in advance to data wire
D1~D6 implements an action for precharge, in this action being pre-charged, SECO
Signal S1~S6 remains high level and logic state overturns, in other words, in Fig. 2
Second switch SW1~SW6 all disconnect, then driving chip 110 provide data voltage signal
DLIN is turned to low level (this and existing skill without because of pre-charge operation from high level
The pre-charging schemes of art Fig. 1 are completely contradicted).At the same time, it is applied to preliminary filling electric control
Control signal S on line 104PREIn time period TPREIt is the first logic level (e.g. low electricity
It is flat), such that it is able to by one group of first switch SWP1, SWP2 in Fig. 3 for PMOS ...
SWPm is turned on, and data wire D1 by SWP1 because be communicated to the second test cabling 102
Above flush to the first reference potential DREF, data wire D2 by SWP2 because be communicated to the
The first reference potential D is flushed on three test cablings 103REF, data wire D3 is because pass through
SWP3 is communicated on the first test cabling 101 and flushes to the first reference potential DREF.With this
Analogize, data wire D4~D6 and all of data wire are all refreshed in the pre-charge operation
To default first reference potential DREFTo remove the electric charge of previous frame residual.
Although control signal S can be applied on added with padding 114PREBut, it is simplest straight
Connect by the driving control signal S of driving chip 110PREThe first logic level (such as low level),
Switch between second logic level (such as high level), namely precharge control line 104 is coupled to
Driving chip 110, realize controlling precharge control line 104 first by driving chip 110,
Switch between second logic level, wherein precharge control line 104 is only in pre-charging stage TPRE
Overturn to the first logic level, and except time period TPREOther times section in addition is all maintained
In the second logic level.In view of the real work of pel array 120 is to control similar to one group
Sub-pixel circuits PX1~PX6 carrys out actual operation, so in a current frame period,
Pre-charging stage TPREAfter end, we still by taking Fig. 2 as an example, on a timeline continuously
Time period T1~T6 lights sub-pixel circuits PX1~respective light-emitting components of PX6 respectively successively.
By the agency of, lights sub-pixel circuits PX1, in time period T2 points in time period T1 above
Transom image element circuit PX2 ... ... lights sub-pixel circuits PX6 in time period T6, realizes
The lighting timings control of RGBRGB.
Mode of the embodiment of Fig. 4 than prior art Fig. 1, can greatly mitigate driving chip
The factor of 110 workloads and saving power consumption is at least embodied at 2 points, in pre-charging stage TPRE,
The data voltage signal DLIN for being first the offer of driving chip 110 need not be because pre-charge operation
And once height logic level state is overturn, furthermore it is that grade switch SW1~SW6 need not be connect
It is logical, namely timing control signal S1~S6 is in pre-charging stage TPREWithout because pre-charge operation
And overturn once height logic level state.It is clear that the present invention is surveyed using existing panel
Try circuit to realize pre-charging functions, shared panel test circuit can both realize pre-charging functions,
The space and mode of operation for saving panel are also easier to realize, it is often more important that switch
SW1~SW6 and data voltage signal DLIN without again for pre-charge operation does corresponding adjustment,
The complexity of driving is substantially reduced, beneficial to improving the display effect of panel and cost-effective.
More than, by explanation and accompanying drawing, give the typical case of the ad hoc structure of specific embodiment
Embodiment, foregoing invention proposes existing preferred embodiment, but these contents are not intended as office
Limit.For a person skilled in the art, after reading described above, various changes and modifications
Undoubtedly it will be evident that.Therefore, appending claims should regard as cover it is of the invention true
Whole variations and modifications of sincere figure and scope.It is any and all etc. in Claims scope
The scope and content of valency, are all considered as still belonging to the intent and scope of the invention.
Claims (12)
1. a kind of data wire to pel array enters the device of line precharge, it is characterised in that
Including first, second, and third test cabling being arranged on around pel array and a precharge
Control line, the pel array includes a plurality of data wire, and in the pel array
Multiple sub-pixel circuits positioned at same row share data wire described in same, wherein any one
The data wire is connected to first, second, and third test and walks by a first switch
One of line three, and the control end of the first switch is all connected to the preliminary filling electric control
Line.
2. the data wire to pel array according to claim 1 enters the dress of line precharge
Put, it is characterised in that also including a driving chip, each institute in the pel array
State data wire and the driving chip is connected to by a second switch, make the data wire root
According to the connection or off-state of the second switch with choose whether from the driving chip capture
Data voltage signal.
3. the data wire to pel array according to claim 2 enters the dress of line precharge
Put, it is characterised in that in a pre-charging stage of the data wire, described first,
Input has the first reference potential on two and the 3rd test cabling, and the second switch breaks
Open, the first logic level being applied on the precharge control line connects the first switch
It is logical, so as to perform precharge to the data wire and be clamped down in the first reference potential.
4. the data wire to pel array according to claim 3 enters the dress of line precharge
Put, it is characterised in that the first, second, and third test cabling is all connected to the driving
Chip, and the first reference potential of precharge is provided by the driving chip for the data wire.
5. the data wire to pel array according to claim 3 enters the dress of line precharge
Put, it is characterised in that the precharge control line is connected to the driving chip, and by described
The driving chip control precharge control line switches between first, second logic level, its
Described in precharge control line only overturn to first logic level in the pre-charging stage,
Overturn to second logic level in other time periods.
6. the data wire to pel array according to claim 1 enters the dress of line precharge
Put, it is characterised in that an end of the first, second, and third test cabling connects respectively
A pad is connected to, test signal is applied to the data wire by the pad, for testing
Corresponding sub-pixel circuits.
7. the data wire to pel array according to claim 1 enters the dress of line precharge
Put, it is characterised in that an end of the precharge control line is connected with a pad.
8. a kind of utilization panel test circuit performs the side of precharge to the data wire of pel array
Method, it is characterised in that the panel test circuit includes first, second, and third test cabling,
The pel array includes multiple data wires and is located in the pel array same
Multiple sub-pixels of row share data wire described in same, and any one data wire passes through
One first switch is connected to one of described first, second, and third test cabling three；
The described method comprises the following steps：
Arbitrarily selected one group of sub-pixel circuits in the pel array, one group of sub-pixel electricity
Before being lighted successively in the Lu Yi frame periods, a precharge step is first carried out, by described one group
The data wire of each sub-pixel circuits is using described first, second and the in sub-pixel circuits
Three test one of cabling threes to clamp down in first reference potential.
9. method according to claim 8, it is characterised in that a driving core is provided
Piece, each the described data wire in the pel array is connected by a second switch
To the driving chip；And
By controlling the connection or disconnection of the second switch, so as to choose whether to make the data
Line is according to from the driving chip acquisition data voltage signal.
10. method according to claim 9, it is characterised in that in the precharge step
In rapid, first first reference potential is input on described first, second, and third test cabling；
And
The second switch is disconnected, while applying the first logic electricity on the precharge control line
It is flat, so as to all of first switch all be connected, perform to data wire precharge simultaneously
Its potential is clamped down in first reference potential.
11. methods according to claim 9, it is characterised in that by described first,
Two and the 3rd test cabling is all connected to the driving chip, and from the driving chip to described
First, second, and third test cabling provides first reference potential.
12. methods according to claim 10, it is characterised in that by the precharge
Control line is connected to the driving chip, and the preliminary filling electric control is controlled using the driving chip
Line switches between first, second logic level；
In precharge step, the current potential of the precharge control line is controlled to switch to described first
Logic level, the other times section beyond the precharge step then controls the preliminary filling automatically controlled
The current potential of line processed switches to second logic level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510895945.9A CN106847181A (en) | 2015-12-07 | 2015-12-07 | Data wire to pel array enters the device and method of line precharge |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510895945.9A CN106847181A (en) | 2015-12-07 | 2015-12-07 | Data wire to pel array enters the device and method of line precharge |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106847181A true CN106847181A (en) | 2017-06-13 |
Family
ID=59151646
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510895945.9A Pending CN106847181A (en) | 2015-12-07 | 2015-12-07 | Data wire to pel array enters the device and method of line precharge |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106847181A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108615504A (en) * | 2018-05-10 | 2018-10-02 | 武汉华星光电半导体显示技术有限公司 | DEMUX display panels and OLED display |
| CN111179807A (en) * | 2019-04-09 | 2020-05-19 | 友达光电股份有限公司 | Display panel and driving method thereof |
| WO2020098053A1 (en) * | 2018-11-12 | 2020-05-22 | 惠科股份有限公司 | Test line structure, test device, and test system |
| CN111798800A (en) * | 2020-07-21 | 2020-10-20 | 合肥维信诺科技有限公司 | Driving circuit, driving method, display panel and display device |
| CN114299865A (en) * | 2021-12-31 | 2022-04-08 | 湖北长江新型显示产业创新中心有限公司 | Display panel and display device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1427385A (en) * | 2001-08-02 | 2003-07-02 | 精工爱普生株式会社 | Driving of data line used in control of unit circuit |
| CN1545691A (en) * | 2002-04-30 | 2004-11-10 | 索尼株式会社 | Liquid crystal display device, drive method thereof, and mobile terminal |
| CN101145318A (en) * | 2006-09-13 | 2008-03-19 | 三星Sdi株式会社 | Organic electro luminescence display device and driving method |
| CN101697269A (en) * | 2009-10-30 | 2010-04-21 | 友达光电股份有限公司 | Pixel circuit and pixel driving method |
| CN103035200A (en) * | 2011-10-04 | 2013-04-10 | 乐金显示有限公司 | Organic light emitting display device and driving method thereof |
| CN103310727A (en) * | 2012-03-09 | 2013-09-18 | 佳能株式会社 | Display apparatus, electronic apparatus using the display apparatus and driving method of the display apparatus |
-
2015
- 2015-12-07 CN CN201510895945.9A patent/CN106847181A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1427385A (en) * | 2001-08-02 | 2003-07-02 | 精工爱普生株式会社 | Driving of data line used in control of unit circuit |
| CN1545691A (en) * | 2002-04-30 | 2004-11-10 | 索尼株式会社 | Liquid crystal display device, drive method thereof, and mobile terminal |
| CN101145318A (en) * | 2006-09-13 | 2008-03-19 | 三星Sdi株式会社 | Organic electro luminescence display device and driving method |
| CN101697269A (en) * | 2009-10-30 | 2010-04-21 | 友达光电股份有限公司 | Pixel circuit and pixel driving method |
| CN103035200A (en) * | 2011-10-04 | 2013-04-10 | 乐金显示有限公司 | Organic light emitting display device and driving method thereof |
| CN103310727A (en) * | 2012-03-09 | 2013-09-18 | 佳能株式会社 | Display apparatus, electronic apparatus using the display apparatus and driving method of the display apparatus |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108615504A (en) * | 2018-05-10 | 2018-10-02 | 武汉华星光电半导体显示技术有限公司 | DEMUX display panels and OLED display |
| US11176893B2 (en) | 2018-05-10 | 2021-11-16 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | DEMUX display panel and OLED display |
| WO2020098053A1 (en) * | 2018-11-12 | 2020-05-22 | 惠科股份有限公司 | Test line structure, test device, and test system |
| US11385485B2 (en) | 2018-11-12 | 2022-07-12 | HKC Corporation Limited | Test wiring structure, test apparatus and test system |
| CN111179807A (en) * | 2019-04-09 | 2020-05-19 | 友达光电股份有限公司 | Display panel and driving method thereof |
| CN111798800A (en) * | 2020-07-21 | 2020-10-20 | 合肥维信诺科技有限公司 | Driving circuit, driving method, display panel and display device |
| CN114299865A (en) * | 2021-12-31 | 2022-04-08 | 湖北长江新型显示产业创新中心有限公司 | Display panel and display device |
| CN114299865B (en) * | 2021-12-31 | 2023-06-16 | 湖北长江新型显示产业创新中心有限公司 | Display panel and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106847181A (en) | Data wire to pel array enters the device and method of line precharge | |
| CN106847200B (en) | Display device and its driving method | |
| CN104992957B (en) | Array substrate, display panel and display device | |
| CN105427781B (en) | Display device | |
| CN103927970B (en) | Panel display apparatus | |
| CN104700796B (en) | Liquid crystal disply device and its preparation method | |
| CN104252835B (en) | Organic light emitting diode display and its driving method | |
| CN106097955B (en) | A kind of driving method of display panel, multiple selector and display panel | |
| CN103366700B (en) | Display device and driving method thereof | |
| CN1989542A (en) | Active matrix type display device and drive control circuit used in the same | |
| TW201306012A (en) | Application of voltage to data lines during Vcom toggling | |
| JP3329009B2 (en) | Active matrix display device | |
| CN107274844A (en) | Display device | |
| CN101404151A (en) | Multi-screen splicing apparatus and method | |
| CN103149759B (en) | Display for generating uniform brightness picture | |
| US20170169771A1 (en) | Liquid Crystal Display And Control Method For The Same | |
| CN110992911B (en) | Display panel driving method and display device | |
| CN105895035A (en) | Over-driving circuit used for display device | |
| CN107507574A (en) | OLED display panel and its compensation method and device, display device | |
| CN106782407A (en) | The driving method and display panel of a kind of display panel | |
| CN102856321A (en) | Thin film transistor array substrate and display device | |
| JP2020502557A (en) | Fault-tolerant display | |
| KR20220035783A (en) | A display device and operating method thereof | |
| CN107195279A (en) | A kind of drive control method of display panel | |
| KR20200041096A (en) | A display comprising a multiplexer and A control method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170613 |
|
| RJ01 | Rejection of invention patent application after publication |