CN106816172B - The whole erasing apparatus of phase transition storage - Google Patents
The whole erasing apparatus of phase transition storage Download PDFInfo
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- CN106816172B CN106816172B CN201710041124.8A CN201710041124A CN106816172B CN 106816172 B CN106816172 B CN 106816172B CN 201710041124 A CN201710041124 A CN 201710041124A CN 106816172 B CN106816172 B CN 106816172B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0097—Erasing, e.g. resetting, circuits or methods
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Abstract
The present invention provides a kind of whole erasing apparatus of phase transition storage, it is mainly individually increased on the basis of existing phase transition storage comprising the enabled switch of erasing, word line voltage generation circuit, erasing voltage generation circuit, bit line wipes the whole erasing apparatus of switching circuit and wordline erasing switch etc., it is limited to avoid by binary system one-hot encoding decoder, and apply the present invention can be when integrally erasing enable signal is effective, all wordline erasing switches are opened, the gate tube of all phase-change memory cells is switched on, switching circuit is wiped by bit line again to be transmitted on bit line erasing voltage, realize the effect that phase transition storage is quickly wiped, and it effectively solves in the prior art, the function of not wiped integrally once due to phase transition storage, all have to take a long time when so that every time wiping entire phase transition storage, it is counted The drawbacks of ten thousand times, up to a million even more multiple erasing operations.
Description
Technical field
The present invention relates to a kind of scrub techniques fields of information-storing device, more particularly to a kind of entirety of phase transition storage
Erasing apparatus.
Background technique
Phase transition storage (Phase change random access memory；It PCRAM) is a kind of non-volatile random
Memory is accessed, and phase-changing memory unit is the basic component units of phase transition storage, is the basis of storage, as shown in Figure 1
1T1R (the 1transistor and 1resistance) phase change memory array being made of n*m phase-changing memory unit 41
4, phase change memory array occupies most of area of phase change memory chip, by the bit line (BL) 42 and word of a large amount of right-angled intersections
The two-dimensional surface matrix composition that line (WL) 43 is formed, and phase-change memory cell 41 is formed in each right-angled intersection point.Wordline and position
Line passes through line decoder respectively and the column selector of column decoder is chosen by external address signal, at this point, selected phase transformation is deposited
Storage unit is connected to programming/reading module, passes through matching for interface and logic control circuit and reference source and clock source module
Closing can realize that reading and writing or erasing to particular memory location etc. operate.Ranks decoder in phase transition storage uses two
The one-hot encoding decoded mode of system, by controlling a small amount of address signal, the wordline and bit line that control needs to activate, this mode
At most there was only one in synchronization storage array wordline to be selected；The bit line of phase change memory array can have one or more quilt
It chooses simultaneously, realizes unit or multi-bit parallel operation, such as the parallel work-flow of single bit operation and 16bits of 1bit.
In conclusion phase transition storage when carrying out erasing operation, can only be directed to (the 1bit output of single phase-change memory cell
Phase transition storage) or n parallel-by-bit operation when to n phase-change memory cell (phase transition storage of n bits parallel output) into
Row erasing operation, specifically, for the phase transition storage of 1bit output, in synchronization phase change memory array bit line at most
Only one is selected, and wordline can only also have one to be selected, then, there can only be one in synchronization phase change memory array
Phase-change memory cell is selected, and by taking the PCRAM chip of 1M memory capacity 1bit output as an example, it has 1024 wordline and 1024
Bit line, according to the principle of the only hot decoding circuit of binary system, once-through operation can only choose a wordline WL and 1 bit line BL, wipe
The operating time of single storage unit is about 500ns, and if desired entire storage array is wiped, then needs to be implemented 1024*1024
=1048576 erasing operations, the time for wiping out entire storage array are up to about 0.5s！And execute million operations significantly
Increase the complexity of operation；For the phase transition storage of n bits parallel output, although synchronization storage array bit line
N item can be chosen simultaneously, but generally there was only 8/16bits, because being applied by pin area, operation complexity and market
Limitation, the quantity of n bits parallel output do not exceed 32 generally, and wordline can only also have one it is selected, then, same
The phase change memory array of one moment n bits parallel output can only have the selected execution erasing operation of n phase-change memory cell, and
And n " 32.By taking the PCRAM chip of 1M memory capacity 16bits output as an example, it has 1024 wordline and 1024 bit lines, according to
The principle of the only hot decoding circuit of binary system, once-through operation can only choose a wordline and 16 bit lines, that is to say, that in same a period of time
Quarter can only at most have 16 phase-change memory cells that can execute erasing operation, and wipe the operating time of single phase-change memory cell
If desired about 500ns wipes entire storage array, then needs to be implemented 1024*1024/16=65536 erasing operation, wipe
The time for removing entire storage array is up to 32ms！And need to be implemented the complexity that tens of thousands of operations increase operation.
Therefore, it is necessary to a kind of whole erasing apparatus of phase transition storage for overcoming prior art disadvantages is proposed, to keep away
From the limitation of binary system one-hot encoding decoder, the problems such as leveraging efficiency of erasing.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of entirety of phase transition storage to wipe
Except device, to effectively reduce the erasing time, and then the efficiency of erasing of phase transition storage is improved.
In order to achieve the above objects and other related objects, the present invention provides a kind of whole erasing apparatus of phase transition storage,
Wherein, the phase transition storage includes at least a column decoder, a connection and is controlled by the column selector of the column decoder, one
Line decoder, be made of multiple phase-change memory cells and this etc. phase-change memory cells arranged by certain line number and columns with linescan method
One phase change memory array of column, and the phase change memory array also includes the columns and each of the corresponding grade phase-change memory cells
Be be separately connected the column selector in the phase change memory array be located at same row all phase-change memory cells it is a plurality of
Bit line and it is corresponding this etc. phase-change memory cells line number and each be to be separately connected the line decoder to deposit with the phase transformation
Store up array in be located at a line all phase-change memory cells a plurality of wordline, and each phase-change memory cell have one with it is described
Gate tube and one that wordline connects are separately connected the phase change resistor of the gate tube Yu the bit line, which is characterized in that the phase
The whole erasing apparatus of transition storage includes: the enabled switch of an erasing, and being provided for an effective or invalid whole erasing makes
It can signal；One word line voltage generation circuit, being includes a word line voltage source and a plurality of erasing wordline (EWL), wherein the word
Line voltage source is provided for a word line voltage opened for the gate tube, this waits the quantity of erasing wordline to be equal to the phase transformation
The line number of the equal phase-change memory cells of this in storage array；One erasing voltage generation circuit comprising an adjustable erasing voltage produces
Raw circuit and a plurality of erasing bit line (EBL), wherein the adjustable erasing voltage generation circuit is provided for the phase transformation
Resistance undergoes phase transition required erasing voltage, and the quantity of grade erasing bit line is equal to the grade phase transformations in the phase change memory array and deposits
The columns of storage unit；One bit line wipes switching circuit comprising and multiple bit line erasing switches and an address increase circuit certainly,
In, equipotential line erasing switch is to connect one to one with grade erasing bit line and be connected in parallel to one by one with the column selector
The equipotential line, the address, which is that connection is described from increasing circuit, wipes enabled switch and equipotential line erasing switch, and to foundation
The erasing enables the effective of whole erasing enable signal provided by switch and controls equipotential line erasing respectively in vain and open
It closes and is successively switched on and off according to a unlatching rule, to be switched on or switched off the company of grade erasing bit line and the equipotential line accordingly
It connects；And multiple wordline erasing switch, be with the enabled switch connection of the erasing and with this etc. erasing wordline connect one to one
And the wordline such as this are connected in parallel to the line decoder one by one, wherein the wordline such as this erasing switch is to receive the wiping
Except integrally wiping enable signal provided by enabled switch, when receiving effective whole erasing enable signal, all wordline
Erasing switch open, with connect accordingly grade wipe wordline and this etc. wordline connection so that the word line voltage source is mentioned
The word line voltage of confession is wiped wordline by the grade and is sent in the wordline such as this one by one, and then correspondingly opens the phase change memory battle array
All gate tubes in column, at the same time, the address is from circuit is increased according to a certain number of bit lines of the unlatching rule control
Erasing switch is successively opened, accordingly to connect the connection that grade wipes bit line and the equipotential line, and then by the adjustable erasing
Erasing voltage caused by voltage generation circuit is transmitted to one by one with the equipotential line by grade erasing bit line and connect the equipotential line
The equal phase change resistors on so that the grade phase change resistors are undergone phase transition, and then complete the erasing behaviour to the equal phase-change memory cells
Make.
In an embodiment of the whole erasing apparatus of phase transition storage of the invention, the enabled switch of the erasing is by soft
What part was realized, but not limited to this, in another embodiment of the whole erasing apparatus of phase transition storage of the invention, the erasing
Enabled switch is by hard-wired.In addition, the adjustable erasing voltage generation circuit may be, for example, stepped erasing electricity
The erasing circuit of road or ramp type.
Specifically, the unlatching rule is according to the maximum current in phase transition storage for the power source loads of erasing operation
Value and single phase-change memory cell are for maximum current value needed for erasing operation, then the layout according to wordline and bit line of arranging in pairs or groups
Rule extrapolates the number for the phase-change memory cell that can be loaded at each moment, then, arranges in pairs or groups according to the phase transition storage
In this etc. wordline quantity, calculate a moment most multipotency open bit line quantity, then the address from increase circuit evidence
Switch is wiped with the bit line that the quantity of bit line calculated opens corresponding number a moment with every secondary control, entire phase transformation is deposited
The bit line for storing up the quantity that array opens corresponding bit line calculated in the address every time under the control for increasing circuit wipes switch,
Until all bit lines erasing switch is all opened, to realize the whole erasing of phase transition storage.In addition, the wordline and bit line
Placement rule is the n times side that the quantity of wordline and bit line is 2, wherein n is natural number.
In addition, the address further comprises from circuit is increased: from circuit is increased, to receive, the erasing is enabled to be opened for the address
Whole erasing enable signal provided by closing turns off all bit line erasings when receiving invalid whole erasing enable signal
Switch, and then the connection of grade erasing bit line and the equipotential line is disconnected, so that the adjustable erasing voltage generation circuit is produced
Raw erasing voltage can not wipe bit line by the grade and is sent in the equipotential line one by one, in order to other behaviour not influenced on bit line
Make.And respectively wordline erasing switch further comprises: the wordline such as this erasing switch is mentioned to receive the enabled switch of the erasing
The whole erasing enable signal of confession, when receiving invalid whole erasing enable signal, all wordline wipe switch OFF, into
And disconnect the grade erasing wordline and this etc. wordline connection so that word line voltage provided by the word line voltage source can not pass through
Grade erasing wordline is sent to one by one in the wordline such as this, in order to other operations not influenced in wordline.
As described above, the present invention proposes a kind of whole erasing apparatus of phase transition storage, mainly in existing phase change memory
It is individually increased on the basis of device comprising wiping enabled switch, word line voltage generation circuit, erasing voltage generation circuit, bit line are wiped
Except the whole erasing apparatus of switching circuit and wordline erasing switch etc., avoid being limited by binary system one-hot encoding decoder, and
It can control all wordline erasing switches when integrally erasing enables effective using the present invention and open, all phase-change memory cells
Gate tube be switched on, then switching circuit is wiped by bit line, erasing voltage is transmitted on bit line, realized and quickly wipe
Effect, and effectively solve in the prior art, it, can only be only by binary system due to the function that phase transition storage is not wiped integrally once
The limitation of hot code encoder can only once wipe one/several (parallel data output interface) phase-change memory cells, so that every time
All have to take a long time when wiping entire phase transition storage, carries out tens of thousands of secondary, up to a million times even more repeatedly
Erasing operation the drawbacks of.
Detailed description of the invention
Fig. 1 is shown as the 1T1R phase change memory array schematic diagram of n*m.
Fig. 2A is shown as simplifying for the phase transition storage after the whole erasing apparatus using phase transition storage of the invention and ties
Structure block diagram.
Fig. 2 B is shown as the circuit diagram of an embodiment of application drawing 2A.
Fig. 3 be shown as using phase transition storage of the invention whole erasing apparatus first embodiment every bit line according to
The bit line of secondary unlatching wipes switching circuit schematic diagram.
4 bit lines that Fig. 4 is shown as the second embodiment of the whole erasing apparatus using phase transition storage of the invention are same
Shi Kaiqi is sequentially completed the bit line erasing switching circuit schematic diagram integrally wiped.
Component label instructions
1 column decoder
2 column selectors
3 line decoders
4 phase change memory arrays
41 phase-change memory cells
411 gate tubes
412 phase change resistors
42 bit lines
43 wordline
The enabled switch of 51 erasings
52 word line voltage generation circuits
521 word line voltage sources
522 erasing wordline
53 erasing voltage generation circuits
531 adjustable erasing voltage generation circuits
532 erasing bit lines
54 bit lines wipe switching circuit
541 bit lines erasing switch
542 addresses increase circuit certainly
55 wordline erasing switch
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.It should be noted that in the absence of conflict, following embodiment and implementation
Feature in example can be combined with each other.
It should be noted that illustrating the basic structure that only the invention is illustrated in a schematic way provided in following embodiment
Think, only shown in schema then with related component in the present invention rather than component count, shape and size when according to actual implementation
Draw, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its assembly layout kenel
It is likely more complexity.
Fig. 2A is please referred to, the phase transition storage after being displayed as the whole erasing apparatus using phase transition storage of the invention
Simplification structural block diagram.As shown in Figure 2 A, which includes at least a column decoder 1, one and connects and be controlled by described
The column selector 2 of column decoder, a line decoder 3 are made of and each phase-change memory cell 41 multiple phase-change memory cells 41
By the phase change memory array 4 that certain line number and columns are arranged in ranks, and the phase change memory array 4 further includes corresponding each
The columns and each of the phase-change memory cell 41 are to be separately connected in the column selector 2 and the phase change memory array 4 to be located at together
The multiple bit lines (BL) 42 of all phase-change memory cells 41 of one column and the corresponding respectively line number of the phase-change memory cell 41 and every
One is to be separately connected all phase-change memory cells 41 being located in the line decoder 3 and the phase change memory array 4 with a line
A plurality of wordline (WL) 43, and each phase-change memory cell 41 has a gate tube 411 connecting with the wordline 43 and a difference
The phase change resistor 412 of the gate tube 411 Yu the bit line 42 is connected, in addition, as shown in Figure 2 B, which is provided for
The selection of sense bit line (RBL) or global bit line (GBL) uses；And the whole erasing apparatus of phase transition storage of the invention then wraps
It includes an erasing and enables switch 51, a word line voltage generation circuit 52, an erasing voltage generation circuit 53, bit line erasing switch electricity
Road 54 and multiple wordline wipe switch 55.Cooperate Fig. 2 B to the whole erasing apparatus of phase transition storage of the invention below
It is described in detail.
As shown in Figure 2 A, which enables switch 51 and is provided for an effective or invalid whole erasing enable signal.
In one embodiment, it is by software realization which, which enables switch 51, and but not limited to this, in other embodiments, the wiping
Except enabled switch is also possible to through hardware realization, such as one is provided in the whole erasing apparatus of phase transition storage of the invention
Toggle switch or button switch generate described effective or invalid whole erasing enable signal.
The word line voltage generation circuit 52 be include a word line voltage source 521 and a plurality of erasing wordline (EWL) 522,
In, which is to provide one for opening the word line voltage of the gate tube 411, respectively the quantity etc. of the erasing wordline 522
The line number of the respectively phase-change memory cell 41 in the phase change memory array 4.Specifically, in the present embodiment, wordline electricity
Potential source 521 is a power supply.
The erasing voltage generation circuit 53 includes an adjustable erasing voltage generation circuit 531 and a plurality of erasing bit line
(EBL) 532, wherein the adjustable erasing voltage generation circuit 531 is to generate a wiping for wiping phase transition storage integrally
Except voltage, phase change resistor is made to be converted into low-resistance, respectively the quantity of the erasing bit line 532 is equal to respectively should in the phase change memory array 4
The columns of phase-change memory cell 41.In one embodiment, the adjustable erasing voltage generation circuit 531 may be, for example, it is stepped or
The erasing circuit of ramp type, specifically, the process of erasing operation is first that phase-change material is all molten under erasing voltage control
Change, obtain consistent amorphous state, then gradually decrease the height of voltage pulse again, not only can improve erasing operation at
Power keeps the phase change resistor after erasing lower, moreover it is possible to make the consistency raising of resistance after erasing operation, therefore can use
Stepped or ramp type erasing voltage carries out erasing operation to phase-change memory cell.
It includes multiple bit lines erasing switch 541 and an address from circuit 542 is increased that the bit line, which wipes switching circuit 54, specifically
For, respectively the bit line erasing switch 541 be with the grade wipe bit line 532 connect one to one and one by one with the column selector 2 simultaneously
Row is connected to the respectively bit line 42, and the address is to enable switch 51 and the respectively position to be separately connected the erasing from circuit 542 is increased
Line wipes switch 541, and the address is that integrally erasing makes to enable provided by switch 51 according to the erasing from circuit 542 is increased
Can signal it is effective with it is invalid and control respectively bit line erasing switch 541 respectively and be successively switched on and off according to a unlatching is regular,
To be switched on or switched off the connection of respectively the erasing bit line 532 and the respectively bit line 42 accordingly.Specifically, the address increases circuit certainly
542 be to enable integrally to wipe enable signal provided by switch 51 to receive the erasing, is wiped when receiving effective entirety
When enable signal, the respectively bit line is successively opened according to above-mentioned unlatching rule and wipes switch 541, and then connects the respectively erasing bit line
532 with the connection of each bit line 42, and then erasing voltage caused by the adjustable erasing voltage generation circuit 531 passed through each
The erasing bit line 532 is sent on the phase change resistor 412 for connecting the respectively bit line 42 one by one with the respectively bit line 42；It is invalid when receiving
Whole erasing enable signal when, turn off all bit lines erasing switches 541, and then disconnect the respectively erasing bit line 532 and the respectively position
The connection of line 42, so that erasing voltage caused by the adjustable erasing voltage generation circuit 531 can not pass through the respectively erasing position
Line 532 is sent to one by one on the respectively bit line 42, in order to other operations not influenced on bit line.
Preferably, which is according to the maximum current value in phase transition storage for the power source loads of erasing operation
And single phase-change memory cell is for maximum current value needed for erasing operation, then arranges in pairs or groups according to wordline and the layout of bit line rule
Then, the quantity for the phase-change memory cell 41 that can be loaded at each moment is extrapolated, then, is arranged in pairs or groups according in the phase transition storage
The respectively quantity of the wordline 43 calculates the quantity for the bit line 42 opened in a moment most multipotency, then the address increases circuit 542 certainly
Every secondary control wipes switch 541 a moment with the bit line that the quantity of bit line calculated opens corresponding number accordingly, entirely
The bit line that phase change memory array successively opens the quantity of corresponding bit line calculated in the address under the control for increasing circuit 542 is wiped
Except switch 541, until all bit lines erasing switch 541 is all opened, to realize the whole erasing of phase transition storage.More in detail and
The placement rule of Yan Zhi, the wordline and bit line is the n times side that the quantity of wordline and bit line is 2, wherein n is natural number.
Multiple wordline erasing switches 55 be with the erasing enable switch 51 connect and with respectively 522 1 a pair of erasing wordline
It should connect and be connected in parallel to the respectively wordline 43 with the line decoder 3 one by one, and respectively wordline erasing switch 55 is to receive
The erasing enables integrally to wipe enable signal provided by switch 51, when receiving effective whole erasing enable signal, institute
There is wordline erasing switch 55 to open, to connect the connection of respectively the erasing wordline 522 and the respectively wordline 43 accordingly, so that the wordline
Word line voltage provided by voltage source 521 is sent in the respectively wordline 43 one by one by the respectively erasing wordline 522, and then correspondingly
It opens with all gate tubes 411 that respectively wordline 43 is connect in the phase change memory array 4, at the same time, which increases circuit certainly
542 successively open according to a certain number of bit line erasing switches 541 of above-mentioned unlatching rule control, and then connect the respectively erasing bit line
532 with the connection of each bit line 42, and then erasing voltage caused by the adjustable erasing voltage generation circuit 531 passed through each
The erasing bit line 532 is sent on the phase change resistor 412 for connecting the respectively bit line 42 one by one with the respectively bit line 42, so that the respectively phase transformation
Resistance 412 is undergone phase transition, and then completes the erasing operation to the respectively phase-change memory cell.In addition, ought respectively wordline erasing switch
55 when receiving invalid whole erasing enable signal, and all wordline erasing switches 522 turn off, and then each erasing wordline of disconnection
522 with the connection of each wordline 43 so that word line voltage provided by the word line voltage source 521 can not pass through the respectively erasing wordline
522 are sent to one by one in the respectively wordline 43, in order to other operations not influenced in wordline 43.
It needs to be explained herein, respectively bit line erasing in the whole erasing apparatus of phase transition storage of the invention is opened
541 are closed to be connected in parallel to one by one on the respectively bit line 42 with column selector 2, meanwhile, respectively the wordline wipes switch 55 and line decoder 3
Also it is connected in parallel to one by one in the respectively wordline 43, to realize reading and writing, the erasing function of phase transition storage, these wordline, position respectively
Line erasing switch and the read-write switching circuit of ranks decoder control are respectively independent, are independent of each other, specific structure is as shown in Figure 2 B.
Application unlatching rule of the invention is understood to be more detailed, below with the maximum electricity of the power source loads for erasing operation
Flow valuve be 1A and single phase-change memory cell for maximum current value needed for erasing operation be 400 μ A for and cooperate Fig. 3
And Fig. 4 is illustrated for two examples respectively.According to the maximum current value as described above for the power source loads of erasing operation
Maximum current value needed for being used for erasing operation for 1A and single phase-change memory cell is 400 μ A, and each moment is calculated
The quantity for the phase-change memory cell that power supply can load simultaneously can only be limited in≤2500, advise in conjunction with wordline and the layout of bit line
Then, i.e. the quantity of wordline and bit line is 2 n (n is natural number) power, further extrapolates each moment and is being wiped
The quantity of phase-change memory cell can only be limited in≤2048, i.e. the quantity of wordline and bit line is all necessarily less than equal to 2048, if
It is too big to will lead to the electric current in whole erasing operation, loaded on power supply more than 2048, will cause power pins be burned out or
Person causes the erasing operation in chip to fail because circuit can not provide so big electric current.
Firstly, as shown in figure 3, showing the first embodiment of the whole erasing apparatus of application phase transition storage of the invention
The bit line that every bit line is successively opened wipes switching circuit schematic diagram: under the conditions of chip capacity is biggish, number of word lines reaches
2048, for the normal erasing operation for guaranteeing circuit, according to above-mentioned unlatching rule, then can calculate moment at most only
Can open bit line quantity be 1, then the address from increase circuit 542 accordingly every secondary control a moment with position calculated
(1) unlatching corresponding number (1) bit line of quantity of line wipes switch 541, and bit line erasing switch 541 can only be opened a moment
One is opened, i.e., should successively be opened one by one by address from the bit line 42 that circuit 542 controls is increased, entire phase change memory array exists
Quantity (1) bit line that the address successively opens corresponding bit line calculated under the control for increasing circuit 542 wipes switch 541,
Until all bit lines erasing switch 541 is all opened, to realize the whole erasing of phase transition storage, in this way, in synchronization
It can guarantee there is 2048*1=2048 phase-change memory cell 41 to execute erasing operation under the premise of chip is normally wiped free of, far
Much larger than can only at most have 32 phase change memory lists in synchronization according to the quantity of parallel data output interface in the prior art
Member executes the limitation of erasing operation, substantially increases efficiency of erasing.
Secondly, as shown in figure 4, showing the second embodiment of the whole erasing apparatus of application phase transition storage of the invention
4 bit lines open the bit line erasing switching circuit schematic diagram for being sequentially completed and integrally wiping simultaneously: in the lesser condition of chip capacity
Under, wordline WL is less than 2048, and for wordline 512, according to above-mentioned unlatching rule, bit line wipes switch 541 at one
4 can only at most be opened quarter, address is opened from 542 every secondary control of circuit, 4 bit line erasing switches 541 are increased, entire phase change memory
Array opens 4 bit lines under the control for increasing circuit 542 in address every time, and successively opens according to 4 every time quantity, finally
Realize the whole erasing of phase transition storage.Therefore, according to above-mentioned unlatching rule, it can control a+1 bit line erasing in synchronization
(a >=0) is switched to open, entire phase change memory array opens a+1 bit line under the control for increasing circuit 542 in address every time, and
Erasing operation successively is completed to entire phase change memory array according to each quantity for opening a+1, realizes whole erasing, in this way,
There is 512*4=2048 phase-change memory cell to execute erasing under the premise of synchronization can guarantee that chip is normally wiped free of
Operation is far longer than in the prior art because being limited in the chip that synchronization list bit is operated by binary system one-hot encoding decoder
Can only at most there be 1 phase-change memory cell to execute erasing operation, even the shadow of managed instep product of the chip of more bits operation etc.
The general limitation that at most can only also there are 32 phase-change memory cells to execute erasing operation is rung, efficiency of erasing is substantially increased.
In conclusion the present invention provides a kind of whole erasing apparatus of phase transition storage, mainly in existing phase change memory
It is individually increased on the basis of device comprising wiping enabled switch, word line voltage generation circuit, erasing voltage generation circuit, bit line are wiped
Except the whole erasing apparatus of switching circuit and wordline erasing switch etc., wherein bit line wipes switching circuit and increases electricity certainly by address
Road controls its bit line and wipes switch, and when the whole erasing enable signal that erasing enables switch generation is effective, address increases circuit certainly
It opens, bit line erasing switch is also successively opened, and erasing voltage generation circuit is connected on the bit line of phase change memory array and is wiped
Except operation；When integrally erasing enable signal is invalid, address is from circuit shutdown is increased, and bit line erasing switch is all off, erasing electricity
Pressure generation circuit does not have an impact the operation on bit line with the value on the connecting line (i.e. erasing bit line) of bit line erasing switch；And
Wordline erasing switch is addition in wordline, the whole erasing enable signal control generated by wiping enabled switch, in whole wiping
When effective except enable signal, all wordline erasing switches are opened, and word line voltage is transmitted in the wordline of phase change memory array, is owned
The gate tube of storage unit is switched on；When integrally erasing enable signal is invalid, all wordline wipe switch OFF, word line voltage
Other operations in wordline are not had an impact with the value on the connecting line (i.e. erasing wordline) of wordline erasing switch, by this hair
The whole erasing apparatus of bright phase transition storage neither influences the normal read-write operation of existing phase transition storage, but also can
To realize the function quickly wiped entirety of phase transition storage, with can only once wipe one/it is several that (parallel data is exported and is connect
Mouthful) conventional phase change memory of phase-change memory cell compares, effectively reduce the erasing time, improve erasing speed.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (9)
1. a kind of whole erasing apparatus of phase transition storage, wherein the phase transition storage includes at least a column decoder, a company
The column selector of the column decoder, a line decoder are connect and be controlled by, is made of multiple phase-change memory cells and multiple phase
Become the phase change memory array that storage unit is arranged in ranks by certain line number and columns, and the phase change memory array is also
Comprising multiple bit lines and a plurality of wordline, and each phase-change memory cell has a gate tube connecting with the wordline and one
It is separately connected the phase change resistor of the gate tube Yu the bit line, which is characterized in that the whole erasing dress of the phase transition storage
It sets and includes:
The enabled switch of one erasing is provided for an effective or invalid whole erasing enable signal；
One word line voltage generation circuit, being includes a word line voltage source and a plurality of erasing wordline, wherein the word line voltage source
It is provided for a word line voltage opened for the gate tube, the quantity of a plurality of erasing wordline is equal to the phase change memory battle array
The line number of multiple phase-change memory cell in column；
One erasing voltage generation circuit comprising an adjustable erasing voltage generation circuit and a plurality of erasing bit line, wherein institute
It states adjustable erasing voltage generation circuit and is provided for the phase change resistor and undergo phase transition required erasing voltage, a plurality of wiping
Except the quantity of bit line is equal to the columns of multiple phase-change memory cell in the phase change memory array；
One bit line wipes switching circuit comprising multiple bit line erasing switches and an address increase circuit certainly, wherein multiple position
Line erasing switch be connect one to one with a plurality of erasing bit line and --- it is a plurality of to be connected in parallel to this with the column selector
Bit line, the address, which is that connection is described from increasing circuit, wipes enabled switch and multiple bit line erasing switch, and to according to institute
Erasing is stated to enable the effective of whole erasing enable signal provided by switch and control multiple bit line erasing respectively in vain and open
It closes and is successively switched on and off according to a unlatching rule, to be switched on or switched off a plurality of erasing bit line and the multiple bit lines accordingly
Connection；And
Multiple wordline erasing switches are to connect with the enabled switch of the erasing and connect one to one with a plurality of erasing wordline
And a plurality of wordline is connected in parallel to the line decoder one by one, wherein multiple wordline erasing switch is to receive
Whole erasing enable signal provided by the enabled switch of erasing is stated to own when receiving effective whole erasing enable signal
Wordline erasing switch is opened, to connect the connection of a plurality of the erasing wordline and a plurality of wordline accordingly, so that the wordline is electric
Word line voltage provided by potential source is sent in a plurality of wordline one by one by a plurality of erasing wordline, and then correspondingly opens institute
Gate tube all in phase change memory array is stated, at the same time, the address is from circuit is increased according to the unlatching rule control one
The bit line erasing switch of fixed number amount is successively opened, accordingly to connect the connection of a plurality of the erasing bit line and the multiple bit lines, in turn
Erasing voltage caused by the adjustable erasing voltage generation circuit is passed through into a plurality of erasing bit line and the multiple bit lines one
One is sent on the multiple phase change resistors for connecting the multiple bit lines, so that multiple phase change resistor is undergone phase transition, and then completes
To the erasing operation of multiple phase-change memory cell；
Wherein, it is described open rule for according in phase transition storage for the maximum current value of the power source loads of erasing operation and
Single phase-change memory cell is for maximum current value needed for erasing operation, then the placement rule according to wordline and bit line of arranging in pairs or groups,
The number for the phase-change memory cell that can be loaded at each moment is extrapolated, then, collocation was according to should in the phase transition storage
The quantity of a plurality of wordline calculates the quantity for the bit line opened in a moment most multipotency, then the address increases circuit accordingly certainly
Every secondary control wipes switch, entire phase change memory a moment with the bit line that the quantity of bit line calculated opens corresponding number
The bit line that array opens the quantity of corresponding bit line calculated in the address every time under the control for increasing circuit wipes switch, directly
It is all opened to all bit lines erasing switch, to realize the whole erasing of phase transition storage.
2. the whole erasing apparatus of phase transition storage according to claim 1, it is characterised in that: the enabled switch of erasing
It is to pass through software realization.
3. the whole erasing apparatus of phase transition storage according to claim 1, it is characterised in that: the enabled switch of erasing
It is to pass through hardware realization.
4. the whole erasing apparatus of phase transition storage according to claim 1, it is characterised in that: the adjustable erasing electricity
Pressing generation circuit is the one of them of the erasing circuit of stepped erasing circuit and ramp type.
5. the whole erasing apparatus of phase transition storage according to claim 1, it is characterised in that: the wordline and bit line
Placement rule is the n times side that the quantity of wordline and bit line is 2, wherein n is natural number.
6. the whole erasing apparatus of phase transition storage according to claim 1, it is characterised in that: the address increases circuit certainly
Further comprise: the address enables entirety erasing enable signal provided by switch to receive the erasing from increasing circuit,
When receiving invalid whole erasing enable signal, all bit line erasing switches are turned off, and then disconnect a plurality of erasing bit line
With the connection of the multiple bit lines so that erasing voltage caused by the adjustable erasing voltage generation circuit can not be more by this
Item erasing bit line is sent to one by one on the multiple bit lines, does not influence other operations on bit line.
7. the whole erasing apparatus of phase transition storage according to claim 1, it is characterised in that: multiple wordline erasing is opened
Pass further includes: multiple wordline erasing switch to receive the whole enabled letter of erasing provided by the enabled switch of the erasing
Number, when receiving invalid whole erasing enable signal, all wordline wipe switch OFF, and then disconnect a plurality of erasing word
The connection of line and a plurality of wordline, so that word line voltage provided by the word line voltage source can not pass through a plurality of erasing wordline
It is sent in a plurality of wordline one by one, does not influence other operations in wordline.
8. the whole erasing apparatus of phase transition storage according to claim 1, it is characterised in that: the quantity of the multiple bit lines
Equal to the columns of multiple phase-change memory cell, and each bit line is to be separately connected the column selector and the phase change memory
Positioned at all phase-change memory cells of same row in array.
9. the whole erasing apparatus of phase transition storage according to claim 1, it is characterised in that: the quantity of a plurality of wordline
Equal to the line number of multiple phase-change memory cell, and each wordline is to be separately connected the line decoder and the phase change memory
It is located at all phase-change memory cells with a line in array.
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| CN201710041124.8A CN106816172B (en) | 2017-01-17 | 2017-01-17 | The whole erasing apparatus of phase transition storage |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040114438A1 (en) * | 2002-12-05 | 2004-06-17 | Sharp Kabushiki Kaisha | Semiconductor memory device and erase method for memory array |
| CN1744232A (en) * | 2004-09-03 | 2006-03-08 | 海力士半导体有限公司 | Flash memory device and method of erasing flash memory cell thereof |
| CN103839587A (en) * | 2014-03-17 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Electric erasable programmable read-only memory and operating method |
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2017
- 2017-01-17 CN CN201710041124.8A patent/CN106816172B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040114438A1 (en) * | 2002-12-05 | 2004-06-17 | Sharp Kabushiki Kaisha | Semiconductor memory device and erase method for memory array |
| CN1744232A (en) * | 2004-09-03 | 2006-03-08 | 海力士半导体有限公司 | Flash memory device and method of erasing flash memory cell thereof |
| CN103839587A (en) * | 2014-03-17 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Electric erasable programmable read-only memory and operating method |
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