CN106815801A - Median filter circuit structure and middle value-acquiring method - Google Patents
Median filter circuit structure and middle value-acquiring method Download PDFInfo
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Abstract
The invention provides a kind of median filter circuit structure and middle value-acquiring method, the structure includes：For depositing deposit upper cycle 1 data register of data of tactic N by size；For receiving n-th data and the increased bit wide of its bit wide being increased into circuit；For the N 1 in the n-th data and data register after the increase bit wide for increasing bit wide circuit output, tactic data are compared and generate comparing and the ranking circuit of new order by size；And for completing the decay of data and termination and remainder data being stored in the decay of the life cycle in data register and termination circuit.Median filter circuit structure of the invention reduces the complexity of logic circuit so that it can adapt to clock speed higher on the basis of register resources consumption is reduced.
Description
Technical field
The present invention relates to digital integrated electronic circuit technical field, and in particular to a kind of median filter circuit structure and acquisition
The method of intermediate value.
Background technology
Medium filtering is the nonlinear filtering technique commonly used in Digital Image Processing and signal transacting.At digital picture
In reason, with conventional mean filter, gaussian filtering and Wiener filtering etc. together form common image optimization and pretreatment side
Method.Medium filtering is mainly used in processing salt-pepper noise.The bad point of the appearance in CIS image processing circuits, because its is defeated
Go out characteristic similar to salt-pepper noise, so conventional median filter is pre-processed.Median filtering algorithm, has obtained greatly excellent
Change, wherein the median filtering technology of the Fast Median Filtering accelerated based on average and self adaptation has obtained preferable effect.But it is right
In digital circuit, conventional medium filtering structure is still two classes：
, there is the buffering area deposited for the data of N to depth, and add the size data that depth is N and post in the first kind
Storage, the size order for storing N number of data.By sorting confirmation sequentially, and finally confirm that intermediate value is size data and posts
Corresponding that data in (N+1)/2 in storage.
, there is the buffering area deposited for the data of N to depth, and add the turnover order that depth is N and post in Equations of The Second Kind
Storage.N number of data are arranged in order, newest when new data enters fashionable, and newest N number of data are resequenced by size,
Update the sequencing when top n data.
In existing method, first kind medium filtering structure is optimized, the depth of data storage device is subtracted from N number of
It it is less N-1, so as to realize smaller circuit area.But which introduce unnecessary data rearrangement circuit, circuit structure according to
It is old to there is optimization space.
The content of the invention
In order to overcome problem above, the present invention is intended to provide a kind of median filter circuit structure, so as to reduce logic electricity
The complexity on road.
In order to achieve the above object, the invention provides a kind of median filter circuit structure, it is characterised in that including：
Data register, compare and ranking circuit, bit wide increase circuit and life cycle decay and termination circuit；The median filter
Circuit structure is used to carry out medium filtering to N number of m bit data, and N is the integer more than or equal to 2；M is whole more than or equal to 1
Number；Wherein,
Data register, for depositing deposit upper cycle tactic N-1 data by size；
Bit wide increases circuit, receives n-th data, and the bit wide of m bit of n-th data is increased into n bit data bit,
N+m bit after being increased, and initial value N is set by n bit high, low m bit holding is constant, and will increase bit wide
N-th data is activation afterwards is compared and ranking circuit；
Comparing and ranking circuit, post for the n-th data after the increase bit wide for increasing bit wide circuit output with data
N-1 data tactic by size in storage are compared, it is determined that increase the position of the n-th data after bit wide, from
And new order is generated, and export in life cycle decay and termination circuit；
Life cycle decays and termination circuit, and 2 are subtracted for n bit high of all data to receivingm, to complete height
The decay of n bit, and that group of data that n bit wherein high for 0 are deleted, decay and the termination of data are completed, by its remainder
According to being stored in data register, think that next cycle is standby.
Preferably, increased n bit data bit is life cycle bit, for characterize data in whole median filter
In existence time；Life cycle bit preset value is N, often carries out a size order and compares and sort, life cycle bit
Position subtracts 1, and when its value is changed into 0, the life termination of the data clears out of whole median filter, ensures that a upper cycle posted with this
The data volume deposited is always N-1；Life cycle bit size of each data is 1~N-1.
Preferably, the bit wide of the data in life cycle decay and termination circuit is n, also, the relation of N and n is 2(n-1)
≤N≤2n, n is the integer more than or equal to 1.
Preferably, the bit wide for increasing the n-th data after bit wide is m+n, and total register consumption is (m+n) * (N-1).
Preferably, total bit wide of the data register is m+n.
In order to achieve the above object, obtained using above-mentioned median filter circuit structure present invention also offers a kind of
The method of intermediate value, it includes：
Step 01：At the end of a upper cycle is fast, after life cycle decays and termination circuit will complete decay and termination
Data, are sequentially stored in data register, think that next cycle is standby；
Step 02：Next cycle just starts, and bit wide increases circuit and receives n-th data, and increases the position of the n-th data
Width, then will increase the n-th data is activation after bit wide to being compared and ranking circuit；
Step 03：Comparing and ranking circuit will increase the n-th data after bit wide and press big with N-1 in data register
Small tactic data are compared, it is determined that increase the position of the n-th data after bit wide, so that new order is generated, and so
After export life cycle decay and termination circuit in；
Step 04：Life cycle decays and termination circuit subtracts 2 to n bit high of all data for receivingm, to complete
The decay of n bit high, and that group of data that n bit wherein high for 0 are deleted, decay and the termination of data are completed, by remaining
Data are stored in data register, think that next cycle is standby；
Step 05：Repeat step 01~04, until completing N number of loop cycle.Acquisition intermediate value according to claim 5
Method, it is characterised in that in step 04, the data bit width employed in life cycle decay and termination circuit is n, also, N
It is 2 with the relation of n(n-1)≤N≤2n, n is the integer more than or equal to 1.
Preferably, the increased n bit data bit of institute is life cycle bit, for characterize data in whole medium filtering
Existence time in device；Life cycle bit preset value is N, often carries out a size order and compares and sort, life cycle
Bit subtracts 1, and when its value is changed into 0, the life termination of the data clears out of whole median filter, and a upper cycle was ensured with this
The data volume of deposit is always N-1；Life cycle bit size of each data is 1~N-1.
Preferably, in step 02, the bit wide for increasing the n-th data after bit wide is m+n, and total register consumption is (m+
n)*(N-1)。
Preferably, total bit wide of the data register for being used is m+n.
It is high instant invention overcomes existing median filter consumed register resource, circuit complexity shortcoming high, the present invention
Circuit structure reduce register resources consumption on the basis of, reduce logic circuit complexity so that it can adapt to more
Clock speed high.
Brief description of the drawings
Fig. 1 is the structural representation of the data register of a preferred embodiment of the invention
Fig. 2 is the schematic diagram of the Median Filter Circuit structure of a preferred embodiment of the invention
Fig. 3 is the schematic flow sheet of the method for the acquisition intermediate value of a preferred embodiment of the invention
Fig. 4 is that the N of a preferred embodiment of the invention is 5 and the schematic diagram of median filter circuit structure when m is 8
Specific embodiment
To make present disclosure more clear understandable, below in conjunction with Figure of description, present disclosure is made into one
Step explanation.Certainly the invention is not limited in the specific embodiment, the general replacement known to those skilled in the art
Cover within the scope of the present invention.
The present invention is described in further detail below in conjunction with accompanying drawing 1~4 and specific embodiment.It should be noted that, accompanying drawing
In the form of simplifying very much, using non-accurately ratio, and only it is used to convenience, clearly reaches aid illustration the present embodiment
Purpose.
Fig. 1~2 are referred to, in the present embodiment, a kind of median filter circuit structure includes：Data register, compare and
Ranking circuit, bit wide increase circuit and life cycle decay and termination circuit.In the present embodiment, median filter circuit structure is used
In medium filtering is carried out to N number of m bit data, N is the integer more than or equal to 2；M is the integer more than or equal to 1.
Data register, refers to Fig. 1, for depositing deposit upper cycle tactic N-1 data by size；Here
Data register total bit wide be m+n.
Fig. 2 is referred to, bit wide increases circuit, receives n-th data, and the bit wide of m bit of n-th data is increased into n
Bit data bit, n+m bit after being increased, and initial value N is set by n bit high, low m bit holding is constant, and
The n-th data is activation after bit wide will be increased to being compared and ranking circuit；Here, the bit wide of the n-th data after bit wide is increased
It is m+n, total register consumption is (m+n) * (N-1).Here, the increased n bit data bit of institute is life cycle bit, is used
In existence time of the characterize data in whole median filter；Life cycle bit preset value is N, often carries out a size
Order compares and sorts, and life cycle bit subtracts 1, and when its value is changed into 0, the life termination of the data clears out of whole intermediate value
Wave filter, ensures the data volume of upper cycle deposit always as N-1 with this；Life cycle bit size of each data is 1~N-
1。
Fig. 2 is referred to, is compared and ranking circuit, for the n-th number after the increase bit wide for increasing bit wide circuit output
It is compared according to N-1 data tactic by size in data register, it is determined that increasing the n-th data after bit wide
Position, so as to generate new order, and export in life cycle decay and termination circuit；
Fig. 2, life cycle decay and termination circuit are referred to, is subtracted for n bit high of all data to receiving
2m, to complete the decay of n bit high, and that group of data that n bit wherein high for 0 are deleted, complete decay and the end of data
Knot, remainder data is stored in data register, thinks that next cycle is standby.Here life cycle decay and termination circuit in
The bit wide of data be n, n is the integer more than or equal to 1, also, the relation of N and n is 2(n-1)≤N≤2n。
Additionally, Fig. 3 is referred to, the side that intermediate value is obtained using above-mentioned median filter circuit structure in the present embodiment
Method, including：
Step 01：At the end of a upper cycle is fast, after life cycle decays and termination circuit will complete decay and termination
Data, are sequentially stored in data register, think that next cycle is standby；
Total bit wide of the data register for using here is m+n.
Step 02：Next cycle just starts, and bit wide increases circuit and receives n-th data, and increases the position of the n-th data
Width, then will increase the n-th data is activation after bit wide to being compared and ranking circuit；
Specifically, the bit wide for increasing the n-th data after bit wide is m+n, total register consumption is (m+n) * (N-1).
Step 03：Comparing and ranking circuit will increase the n-th data after bit wide and press big with N-1 in data register
Small tactic data are compared, it is determined that increase the position of the n-th data after bit wide, so that new order is generated, and so
After export life cycle decay and termination circuit in；
Step 04：Life cycle decays and termination circuit subtracts 2 to n bit high of all data for receivingm, to complete
The decay of n bit high, and that group of data that n bit wherein high for 0 are deleted, decay and the termination of data are completed, by remaining
Data are stored in data register, think that next cycle is standby；
Specifically, the data bit width employed in life cycle decay and termination circuit is n, and, n is more than or equal to 1
Integer, and, the relation of N and n is 2(n-1)≤N≤2n。
Step 05：Repeat step 01~04, until completing N number of loop cycle.
It should be noted that in the present embodiment, each cycle can be controlled using clock.
Fig. 4 is referred to, below with N=5, above-mentioned median filter circuit structure and its work is described as a example by m=8 in detail
Make method.N=3 is obtained by computing, then m+n=11.
Assuming that upper clock cycle registered data is：4ffH, 11eH, 210H and 308H (16 binary datas, by from big to small
Data arranged), input data DS5=0fH.Circuit structure shown in Figure 4 and related description.
Input data DS5 increases module by bit wide, after increasing bit wide, module output DS5=50fH.
Comparing and ranking circuit are compared to the registered data in data register and input data DS5, according to comparing
Output result, judges the position of DS5 insertions, and exports intermediate value data at the same time, according to system requirements, decides whether to Life Cycle
Phase is that 3 data i.e. 308H carries out intermediate value replacement, is changed into 310H.In fig. 4, according to comparative result, 4ffH is followed successively by order,
11eH, 210H, 50fH, 308H (not carrying out data replacement) or 310H (carrying out data replacement).
Life cycle decays and termination circuit is decayed and terminated, and life cycle bit subtracts 1 simultaneously, and data are changed into
3ffH, 01eH, 110H, 208H or 210H.Judge that the data that life cycle is 0 are 01eH, terminated.Remainder data is in order
It is stored in data register, is followed successively by 3ffH, 110H, 40fH, 208H or 210H, standby next cycle uses.
Although the present invention is disclosed as above with preferred embodiment, right embodiment is illustrated only for the purposes of explanation, and
Be not used to limit the present invention, those skilled in the art can make without departing from the spirit and scope of the present invention it is some more
Dynamic and retouching, the protection domain that the present invention is advocated should be defined by claims.
Claims (10)
1. a kind of median filter circuit structure, it is characterised in that including：Data register, compare and ranking circuit, bit wide increase
Power-up road and life cycle decay and termination circuit；The median filter circuit structure is used to carry out N number of m bit data
Medium filtering, N is the integer more than or equal to 2；M is the integer more than or equal to 1；Wherein,
Data register, for depositing tactic N-1 data by size of the upper cycle；
Bit wide increases circuit, receives n-th data, and the bit wide of m bit of n-th data is increased into n bit data bit, obtains
N+m bit after increase, and set initial value N by n bit high, low m bit holding be constant, and will be after increase bit wide
N-th data is activation is compared and ranking circuit；
Comparing and ranking circuit, for n-th data and data register after the increase bit wide for increasing bit wide circuit output
In N-1 data tactic by size be compared, it is determined that increase the position of the n-th data after bit wide, so that raw
The order of Cheng Xin, and export in life cycle decay and termination circuit；
Life cycle decays and termination circuit, and 2 are subtracted for n bit high of all data to receivingm, to complete n bit high
The decay of position, and that group of data that n bit wherein high for 0 are deleted, decay and the termination of data are completed, remainder data is stored in
In data register, think that next cycle is standby.
2. median filter circuit structure according to claim 1, it is characterised in that increased n bit data bit is made a living
Life cycle bit, for existence time of the characterize data in whole median filter；Life cycle bit preset value is N,
Often carry out a size order to compare and sort, life cycle bit subtracts 1, when its value is changed into 0, the life termination of the data,
Whole median filter is cleared out of, ensures the data volume of upper cycle deposit always as N-1 with this；The life cycle of each data
Bit size is 1~N-1.
3. median filter circuit structure according to claim 1, it is characterised in that life cycle decays and termination circuit
In the bit wide of data be n, also, the relation of N and n is 2(n-1)≤N≤2n, n is the integer more than or equal to 1.
4. median filter circuit structure according to claim 1, it is characterised in that increase the n-th data after bit wide
Bit wide be m+n, total register consumption is (m+n) * (N-1).
5. median filter circuit structure according to claim 1, it is characterised in that total bit wide of the data register
It is m+n.
6. a kind of median filter circuit structure using described in claim 1 is come the method that obtains intermediate value, it is characterised in that bag
Include：
Step 01：At the end of a upper cycle is fast, life cycle decay and termination circuit will complete the data after decay and termination,
Sequentially it is stored in data register, thinks that next cycle is standby；
Step 02：Next cycle just starts, bit wide increase circuit reception n-th data, and increases the bit wide of the n-th data,
Then the n-th data is activation after bit wide will be increased to being compared and ranking circuit；
Step 03：It is individual suitable by size with N-1 in data register that comparing and ranking circuit will increase the n-th data after bit wide
The data of sequence arrangement are compared, it is determined that increase the position of the n-th data after bit wide, so that new order is generated, and it is then defeated
Go out in life cycle decay and termination circuit；
Step 04：Life cycle decays and termination circuit subtracts 2 to n bit high of all data for receivingm, to complete n high
The decay of bit, and that group of data that n bit wherein high for 0 are deleted, decay and the termination of data are completed, by remainder data
It is stored in data register, thinks that next cycle is standby；
Step 05：Repeat step 01~04, until completing N number of loop cycle.
7. it is according to claim 6 obtain intermediate value method, it is characterised in that in step 04, life cycle decay and eventually
Data bit width employed in knot circuit is n, also, the relation of N and n is 2(n-1)≤N≤2n, n is the integer more than or equal to 1.
8. the method for obtaining intermediate value according to claim 6, it is characterised in that the increased n bit data bit of institute is life
Cycle bit, for existence time of the characterize data in whole median filter；Life cycle bit preset value is N, often
Carry out a size order to compare and sort, life cycle bit subtracts 1, when its value is changed into 0, the life termination of the data, clearly
Whole median filter is removed out, ensures the data volume of upper cycle deposit always as N-1 with this；The life cycle bit of each data
Position size is 1~N-1.
9. it is according to claim 6 obtain intermediate value method, it is characterised in that in step 02, increase bit wide after n-th
The bit wide of data is m+n, and total register consumption is (m+n) * (N-1).
10. it is according to claim 6 obtain intermediate value method, it is characterised in that total position of the data register for being used
A width of m+n.
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| CN107526571A (en) * | 2017-10-30 | 2017-12-29 | 南京火零信息科技有限公司 | A kind of circuit for comparing size in multiple data |
| CN109445748A (en) * | 2018-09-28 | 2019-03-08 | 北京空间飞行器总体设计部 | It is a kind of quickly to seek median method and system |
| CN112486454A (en) * | 2019-09-12 | 2021-03-12 | 北京华航无线电测量研究所 | Sequence multi-peak searching and sorting device based on FPGA |
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| CN112486454A (en) * | 2019-09-12 | 2021-03-12 | 北京华航无线电测量研究所 | Sequence multi-peak searching and sorting device based on FPGA |
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