CN106809798B - The preparation method of silicon-based nanometer column array - Google Patents
The preparation method of silicon-based nanometer column array Download PDFInfo
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- CN106809798B CN106809798B CN201510845784.2A CN201510845784A CN106809798B CN 106809798 B CN106809798 B CN 106809798B CN 201510845784 A CN201510845784 A CN 201510845784A CN 106809798 B CN106809798 B CN 106809798B
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00349—Creating layers of material on a substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00388—Etch mask forming
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
Abstract
The invention discloses a kind of preparation methods of silicon-based nanometer column array, including：Silicon is formed on the surface of silicon chip and bores array, and the silicon cone array includes several silicon cone；Sacrificial layer is prepared between the silicon cone that silicon bores array；Wherein, the top of the sacrificial layer is no more than the top of silicon cone array；Deposited over arrays metal is bored in sacrificial layer and silicon, second metal layer is formed with the formation the first metal layer on the surface of sacrificial layer and on the surface that silicon bores array；Remove sacrificial layer and the first metal layer；Using second metal layer as mask, etching is covered with the silicon chip of second metal layer, obtains silicon-based nanometer column array.To be covered in the second metal layer in silicon cone array surface as mask, using inductively coupled plasma etching technique, SF is used alternatingly in the preparation method of silicon-based nanometer column array according to the present invention6And C4F8It performs etching and is passivated, silicon-based nanometer column array has been prepared；The diameter and array pitch of nano-pillar in the silicon-based nanometer column array are adjustable.
Description
Technical field
The invention belongs to the preparing technical fields of silicon nanostructure, in particular, being related to a kind of silicon-based nanometer column array
Preparation method.
Background technology
The one-dimensional nano structure that silicon nano-pillar, silicon nanowires etc. are constructed on silicon substrate surface, due to excellent current-carrying
Sub- transport property and efficiently fall into luminous effect, be successfully applied to microelectronics, sensor, biological monitor with
And the numerous areas such as opto-electronic conversion.
For orderly silicon-based nano array structure, generally use optics and electron beam lithography, nano impression and Colloidal crystals
The preparation methods such as grain etching are realized.Wherein, optics and electronic beam photetching process need expensive optical device；Nano impression skill
For art as a kind of preparation method of new nanostructure, the preparation process of impression block equally uses the side of electron beam lithography
Method, cost is higher, and the period of template and characteristic size are fixed, and utilization rate is low；And colloid crystal grain etching is to utilize polyphenyl
Ethylene nanosphere is self-assembly of the mask layer of six side of packed mono-layer in silicon chip surface, then carries out dry etching and prepares a wiener
The method of rice array structure, feature is that the diameter of corresponding nanosphere can be selected to prepare different sizes, different cycles
Nano array structure, method simple possible.
Patent application CN 102633230A disclose a kind of side preparing silicon nano column array based on Nanosphere lithography technique
Method.This method is using polystyrene nanospheres as mask, using inductively coupled plasma etching technique, etches and is passivated by controlling
The ratio of step, to prepare silicon-based nano array structure.This process employs BOSCH techniques (SF is used alternatingly6And C4F8Into
Row etching and be passivated the method for realizing etch of deep silicon trenches) the characteristics of etching and inaction period can be controlled, be prepared for silicon nanometer
Column array；But the unstability of polystyrene nanospheres still can bring undesirable influence in etching process, therefore with poly-
Styrene nanosphere mask can not control the characteristic size of silicon nano column array and the pattern of side wall well.
Invention content
To solve the above-mentioned problems of the prior art, the present invention provides a kind of preparation sides of silicon-based nanometer column array
Using the mask of metal material in conjunction with inductively coupled plasma etching technique, and SF is used alternatingly in method6And C4F8Perform etching and
Passivation, has been prepared silicon-based nanometer column array；The diameter and array pitch of nano-pillar in the silicon-based nanometer column array can
It adjusts.
In order to reach foregoing invention purpose, present invention employs the following technical solutions：
A kind of preparation method of silicon-based nanometer column array, including：Silicon is formed on the surface of silicon chip bores array, the silicon cone
Array includes several silicon cone；Sacrificial layer is prepared between the silicon cone that the silicon bores array；Wherein, the top of the sacrificial layer is not
More than the top that the silicon bores array；Deposited over arrays metal is bored in the sacrificial layer and the silicon, in the sacrificial layer
The first metal layer is formed on surface and forms second metal layer on the surface that the silicon bores array；Remove the sacrificial layer and
The first metal layer；Using the second metal layer as mask, etching is covered with the silicon chip of the second metal layer, obtains silicon substrate
Nano column array.
Further, the method that the silicon cone array is formed on the surface of the silicon chip specifically includes：To the silicon chip
Hydrophilic activation process is carried out, makes the surface of the silicon chip that there is hydrophily；Nanometer ball array is prepared on the surface of the silicon chip；
Using the nanometer ball array as mask, etching is covered with the silicon chip of the nanometer ball array, with the shape on the surface of the silicon chip
Array is bored at the silicon.
Further, the material of the nanometer ball array is nanosphere in polystyrene and/or the nanometer ball array
A diameter of 10nm~1000nm.
Further, etching is covered with the silicon chip of the nanometer ball array and etching is covered with the second metal layer
The method of silicon chip be all made of inductively coupled plasma etching technique, and SF is used alternatingly6And C4F8It performs etching and is passivated.
Further, described that SF is used alternatingly6And C4F8The condition for performing etching and being passivated is：Per etching period SF6Stream
Amount is 1sccm~300sccm, O2Flow be no more than 50sccm, the time be 1s~10s, ion source power be 500W~
1500W, radio-frequency power are no more than 50W, and rf frequency is no more than 500Hz, and duty ratio is no more than 50%；Per inaction period C4F8's
Flow is 1sccm~200sccm, and the time is 1s~10s, and ion source power is 500W~1500W, and radio-frequency power is no more than 50W,
Rf frequency is no more than 500Hz, and duty ratio is no more than 50%；Silicon chip base reservoir temperature is 10 DEG C~50 DEG C, chamber pressure 10mT
~100mT.
Further, the first metal layer and the thickness of the second metal layer are 10nm~100nm；Described first
Metal layer and the material of the second metal layer are selected from any one in Ti, Al, Ni, Au, Ge, Cr, Pt.
Further, the method that the sacrificial layer is prepared between the silicon cone that the silicon bores array specifically includes：Using rotation
Tu method coats sacrificial layer material, and expendable film is formed between the silicon cone that the silicon bores array；Using oxygen plasma etch technique
Expendable film described in reduction processing forms the sacrificial layer between the silicon cone that the silicon bores array；Wherein, the top of the sacrificial layer
End is no more than the top of silicon cone array.
Further, the condition of the sacrificial layer material is coated between the silicon cone that the silicon bores array using rotation Tu method
For：In rotating speed backspin Tu 20s~60s of 200rpm~500rpm, then 1000rpm~2000rpm rotating speed backspin Tu 20s~
60s；Use the condition of expendable film described in oxygen plasma etch technique reduction processing for：O2Flow be 5sccm~50sccm,
Radio-frequency power is 10W~300W, and etching temperature is 20 DEG C~25 DEG C, and chamber pressure is 10mT~200mT.
Further, the sacrificial layer material is polymethyl methacrylate.
Further, the method that the nanometer ball array is prepared on the surface of the silicon chip is assembled selected from gas-liquid interface
Appointing in method, natural sedimentation, rotation Tu method, vertical deposition method, convection current self-assembly method, electrophoretic aided sedimentation method, colloid epitaxy
Meaning is a kind of.
The beneficial effects of the present invention are：
(1) during preparing silicon-based nanometer column array, using the dual mask of nanometer ball array and second metal layer
Technique is performed etching, the feature stablized using property in the had high selectivity of the material of second metal layer and etching process,
It overcomes and is individually using nanometer ball array in the etching process of mask, the selection of the material of nanometer ball array is than not high, property
The unstable defect of matter so that the silicon-based nanometer column array being prepared has the spy of high-aspect-ratio and high quality sidewall profile
Point；
(2) during preparing sacrificial layer, the mother that silicon is bored in the silicon cone array being exposed to above sacrificial layer can be controlled
Line length, to which indirect control second metal layer bores the silicon mask area of array, to reach control silicon-based nanometer column battle array
The purpose in the diameter of nano-pillar and array gap in row, so that the silicon-based nanometer column array being prepared can be applied to not
Same field；
(3) by adjusting the diameter of nanosphere in nanometer ball array, the silicon cone array of different cycles can be obtained, compare other
The method that such as optical mask etching technics is used to prepare silicon cone array, the present invention have the advantages that method is simple, of low cost.
Description of the drawings
What is carried out in conjunction with the accompanying drawings is described below, above and other aspect, features and advantages of the embodiment of the present invention
It will become clearer, in attached drawing：
Fig. 1 is the structural schematic diagram of 1 silicon chip for being covered with polystyrene nanospheres array according to an embodiment of the invention；
Fig. 2 is the structural schematic diagram of 1 silicon chip with silicon cone array according to an embodiment of the invention；
Fig. 3 is the structural schematic diagram of 1 silicon chip for being covered with expendable film according to an embodiment of the invention；
Fig. 4 is the structural schematic diagram of 1 silicon chip for being covered with sacrificial layer according to an embodiment of the invention；
Fig. 5 be according to an embodiment of the invention 1 be covered with the first metal layer and the structure of the silicon chip of second metal layer is shown
It is intended to；
Fig. 6 be according to an embodiment of the invention 1 using second metal layer as the structural schematic diagram of the silicon chip of mask；
Fig. 7 is the structural representation of 1 silicon-based nanometer column array for being covered with second metal layer according to an embodiment of the invention
Figure；
Fig. 8 is the structural schematic diagram of 1 silicon-based nanometer column array according to an embodiment of the invention.
Specific implementation mode
Hereinafter, with reference to the accompanying drawings to detailed description of the present invention embodiment.However, it is possible to come in many different forms real
The present invention is applied, and the present invention should not be construed as limited to the specific embodiment illustrated here.On the contrary, providing these implementations
Example is in order to explain the principle of the present invention and its practical application, to make others skilled in the art it will be appreciated that the present invention
Various embodiments and be suitable for the various modifications of specific intended application.In the accompanying drawings, for the sake of clarity, element can be exaggerated
Shape and size, and identical label will be used to indicate same or analogous element always.
Embodiment 1
Fig. 1 to Fig. 8 is the structural schematic diagram of the preparation method of 1 silicon-based nanometer column array according to an embodiment of the invention,
It is detailed hereinafter with reference to being carried out to the preparation method of according to an embodiment of the invention 1 silicon-based nanometer column array shown in Fig. 1 to Fig. 8
Description.
Step 1：Hydrophilic activation process is carried out to silicon chip 1a, makes the surface of the silicon chip 1a that there is hydrophily.
In the present embodiment, the cylinder that silicon chip 1a is 2 cun in basal diameter, thickness are 400 μm.But the present invention is not
The basal diameter of limited to this, silicon chip 1a can also be that 4 cun, 6 cun, 8 cun, 12 cun are differed, and its thickness general control is at 200 μm
In the range of~600 μm.
Organic washing is carried out to silicon chip 1a first, to remove the organic impurities etc. of silicon chip 1a surface adhesions；Organic washing
Actual conditions are：Successively using acetone, ethyl alcohol, deionized water as cleaning agent, to the silicon chip 1a be cleaned by ultrasonic respectively 5min~
15min。
Then hydrophilic activation process is carried out to the silicon chip 1a Jing Guo organic washing；Specifically, silicon chip 1a is placed in volume ratio
It is 3:1 dense H2SO4And H2O2Mixed solution in, heat 60min at 85 DEG C, silicon chip 1a cleaned with deionized water
.Silicon chip 1a by hydrophilic activation process, surface have hydrophily.
Step 2：Using gas-liquid interface construction from part on the surface of the silicon chip 1a self-assembled nanometer ball, silicon chip 1a's
Nanometer ball array 2 is formed on surface, as shown in Figure 1.
In the present embodiment, the material of the nanosphere is polystyrene, and the polystyrene nanospheres is a diameter of
500nm。
Certainly, the method that nanometer ball array 2 is formed on the surface of silicon chip 1a can also be natural sedimentation, rotation Tu method,
Vertical deposition method, convection current self-assembly method, electrophoretic aided sedimentation method, colloid epitaxy etc..
Step 3：It is mask with nanometer ball array 2, is received using being covered with described in inductively coupled plasma etching technique etching
The silicon chip 1a of rice ball array 2, the nanometer ball array 2 is etched disappearance, on the surface for being covered with nanometer ball array 2 of silicon chip 1a
Upper formation silicon bores array 11, is bored including several silicon as shown in Fig. 2, the silicon bores array 11.
When using the silicon chip 1a of nanometer ball array 2 is covered with described in inductively coupled plasma etching technique etching, specifically
Using BOSCH techniques, that is to say, that SF is used alternatingly6And C4F8It performs etching and is passivated；Specifically, in the present embodiment, it often carves
Lose period SF6Flow be 200sccm, O2Flow be 20sccm, time 5s, ion source power (i.e. ICP power) is
1500W, radio-frequency power 40W；Per inaction period C4F8Flow be 80sccm, time 3s, ICP power 800W；Etching week
Phase and inaction period are 10, and during etching and passivation, silicon chip base reservoir temperature is 10 DEG C, chamber pressure 10mT.
Wherein, sccm indicates that milliliter is per minute under mark condition, and 1mT is equivalent to 0.133Pa.
The distinguishing feature of BOSCH techniques is exactly that can adjust to be passivated in etching process and etch shared proportion, to obtain
Micro-structure with different lateral pattern.When forming nanometer ball array 2 using polystyrene nanospheres, since polystyrene is received
Rice ball has low etching selection ratio, its diameter, which is gradually reduced until, in etching process loses mask effect, finally in silicon chip
Being covered on the surface of nanometer ball array 2 for 1a obtains silicon cone array 11.
Step 4：In the sidespin Tu sacrificial layer material for boring array 11 with silicon of silicon chip 1a, the silicon of array 11 is bored in silicon
Between cone, silicon bores top and the surface of silicon cone both sides is respectively formed on expendable film 3a, as shown in Figure 3.
In the present embodiment, polymethyl methacrylate (abbreviation PMMA) is because it has many advantages, such as high resolution, easy cleaning,
It is the preferred material of expendable film 3a.
Specifically, it is in the actual conditions of the sidespin Tu sacrificial layer material for boring array 11 with silicon of silicon chip 1a：First
In the PMMA of the slow-speed of revolution backspin Tu 20s of 200rpm, then in the PMMA of the high rotating speed backspin Tu 60s of 1000rpm, in the silicon
Between the silicon cone of cone array 11, silicon bores top and the surface of silicon cone both sides has been respectively formed on the expendable film using PMMA as material
3a。
Step 5：Using oxygen plasma etch technique reduction processing be covered in silicon bore array 11 silicon cone between, silicon cone
Expendable film 3a on the surface of top and silicon cone both sides, partial sacrifice film 3a are etched removal, until exposing the silicon cone battle array
The top of row 11, the expendable film 3a that residue is retained between the silicon cone of silicon cone array 11 form sacrificial layer 3；That is, sacrificing
The top of layer 3 is no more than the top of silicon cone array 11, as shown in Figure 4.
In the present embodiment, using the concrete technology condition of expendable film 3a described in oxygen plasma etch technique reduction processing
For：O2Flow be 10sccm, radio-frequency power 50W, etching temperature is 20 DEG C~25 DEG C, and preferably 20 DEG C, chamber pressure is
40mT, etch period 100s.
Step 6：Deposited metal on array 11 is bored in sacrificial layer 3 and silicon using electron-beam vapor deposition method, in sacrificial layer 3
It is respectively formed uniform the first metal layer 41 and second metal layer 42 on surface and on the surface of silicon cone array 11, such as Fig. 5 institutes
Show；In Figure 5, the as the first metal layer 41 for being covered in 3 surface of sacrificial layer in A dotted line frames, and being covered in B dotted line frames
What silicon bored 11 surface of array is second metal layer 42.
In the present embodiment, the first metal layer 41 and the material of second metal layer 42 are W metal, and thickness is
50nm。
Step 7：Sacrificial layer 3 and the first metal layer 41 positioned at its surface are removed, the of 11 surface of silicon cone array is covered in
Two metal layers 42 keep original state, as shown in Figure 6.
Specifically, in the present embodiment, because the material of sacrificial layer 3 is PMMA, acetone, chloroform, tetrahydrofuran are dissolved in
In equal organic solvents, therefore, the silicon chip 1a that will be covered with the first metal layer 41 and second metal layer 42 is placed in acetone at ultrasound
5min~10min is managed, sacrificial layer 3 is dissolved and will together be removed positioned at the first metal layer 41 on its surface.
Step 8：It is mask with second metal layer 42, is covered with using described in inductively coupled plasma etching technique etching
The silicon chip 1a of second metal layer 42, the silicon chip 1a between silicon cone array 11 are etched removal, obtain silicon-based nanometer column array 1, such as
Shown in Fig. 8.
As can be seen from Figure 8, in the silicon-based nanometer column array 1, there is the nano-pillar 12 of several array arrangements,
And each 12 top of nano-pillar maintains silicon cone, and array 11 is bored to form silicon.
When using the silicon chip 1a of second metal layer 42 is covered with described in inductively coupled plasma etching technique etching, specifically
Using BOSCH techniques, that is to say, that SF is used alternatingly6And C4F8It performs etching and is passivated；Specifically, in the present embodiment, it often carves
Lose period SF6Flow be 280sccm, O2Flow be 28sccm, time 7s, ICP power 1500W, radio-frequency power is
40W；Per inaction period C4F8Flow be 80sccm, time 6s, ICP power 800W；Etching period and inaction period are
10, during etching and passivation, silicon chip base reservoir temperature is 10 DEG C, chamber pressure 10mT.
It is worth noting that although using identical method and condition respectively to being covered with second in step 8 and step 3
The silicon chip 1a of metal layer 42 and the silicon chip 1a for being covered with nanometer ball array 2 are performed etching, but in step 8, in silicon chip 1a
The top of silicon cone array 11 is covered with the second metal layer 42 of hard, is selected by the etching of the second metal layer 42 of material of W metal
Select than be far longer than in step 3 using polystyrene as the etching selection ratio of the nanometer ball array 2 of material, therefore etched
Cheng Zhong, the shape and size of second metal layer 42 can remain unchanged, and after etching and passivating conditions balance, it is eventually located at silicon cone
Silicon chip 1a between array 11 is etched away, to obtain silicon-based nanometer column array 1.
Step 9：The silicon-based nanometer column array 1 for being covered with second metal layer 42 that step 8 obtains is placed in dilute hydrochloric acid
5min~10min is cleaned, second metal layer 42 is removed, then cleaned and dried up with deionized water, obtains silicon substrate as shown in Figure 8 and receive
Rice column array 1.
It is worth noting that in the present embodiment, when preparing sacrificial layer 3, by controlling the thickness of sacrificial layer 3, control
It is exposed to silicon element of a cone length in the silicon cone array 11 of 3 top of the sacrificial layer, second as mask of indirect control
The mask area of metal layer 42, to control the diameter of nano-pillar 12 and the array gap of nano-pillar 12, so as to be prepared
Silicon-based nanometer column array 1 can be applied to different fields.The preparation of 1 silicon-based nanometer column array according to an embodiment of the invention
The easily prepared silicon-based nanometer column array 1 for obtaining that there is high-aspect-ratio of method, that is to say, that in the silicon-based nanometer column array 1
In, the array gap between nano-pillar 12 has high-aspect-ratio, and it is exactly to make the silicon that the characteristic of high-aspect-ratio, which most directly embodies,
There is base nano column array 1 specific surface area of bigger to be increased heterogeneous when it is applied in organic-inorganic heterogeneous battery
The specific surface area of knot can effectively improve photoelectric conversion efficiency.At the same time, the silicon-based nanometer column that the present embodiment is prepared
There is silicon to bore array 11 on the top of nano-pillar 12 in array 1, and the setting of silicon cone array 11 can be such that effective refraction coefficient slowly becomes
Change, improve anti-reflection performance, increase the absorption to light, improve laser desorption ionisation performance, to the detection applied to small molecule.
Embodiment 2
In the description of embodiment 2, details are not described herein with the something in common of embodiment 1, only describes with embodiment 1 not
Same place.Embodiment 2 and the difference of embodiment 1 are as described below.
In step 2, a diameter of 800nm of the polystyrene nanospheres.
In step 3, use the actual conditions of BOSCH techniques for：Per etching period SF6Flow be 100sccm, O2's
Flow is 20sccm, time 8s, ICP power 1000W, radio-frequency power 40W, rf frequency 333Hz, and duty ratio is
30%；Per inaction period C4F8Flow be 20sccm, time 5s, ICP power 600W, radio-frequency power 20W, radio frequency frequency
Rate is 333Hz, duty ratio 25%；Etching period and inaction period are 15, during etching and passivation, silicon chip base
Bottom temperature is 10 DEG C, chamber pressure 30mT.
In step 5, use the concrete technology condition of oxygen plasma etch technique reduction processing expendable film 3a for：O2
Flow be 20sccm, radio-frequency power 40W, etching temperature be 20 DEG C, chamber pressure 60mT, etch period 80s.
In step 6, the material of the first metal layer 41 and second metal layer 42 is metal Au.
In step 8, use the actual conditions of BOSCH techniques for：Per etching period SF6Flow be 100sccm, O2's
Flow is 20sccm, time 10s, ICP power 1200W, radio-frequency power 45W, rf frequency 333Hz, and duty ratio is
30%；Per inaction period C4F8Flow be 20sccm, time 6s, ICP power 800W, radio-frequency power 30W, radio frequency frequency
Rate is 333Hz, duty ratio 25%；Etching period and inaction period are 15, during etching and passivation, silicon chip base
Bottom temperature is 10 DEG C, chamber pressure 30mT.
Silicon-based nanometer column array 1 has been prepared with reference to described in embodiment 1 in remaining step.
In the preparation method of silicon-based nanometer column array according to the present invention, the effect of nanometer ball array 2 is by certainly
Body is gradually etched removal, and the surface of silicon chip 1a is made to form silicon cone array 11, and the size of the nanosphere in nanometer ball array 2 is
The gradient of each silicon element of a cone in controllable silicon cone array 11；Therefore, it is used to prepare the nanosphere of nanometer ball array 2 not
The polystyrene nanospheres being limited in above-described embodiment 1 and embodiment 2, other can play gradually to be etched and eliminate and play mask
The nanosphere of effect, while the diameter of polystyrene nanospheres is not limited to described in above-described embodiment 1 and embodiment 2
500nm and 800nm, usually, a diameter of 10nm~1000nm for controlling the nanosphere can be obtained with different silicon cone nuts
The silicon of line gradient bores array 11；That is, the controlled diameter of nanosphere is made with different cycles in nanometer ball array 2
Silicon bore array 11.
At the same time, when using inductively coupled plasma etching technique etching be covered with nanometer ball array 2 silicon chip 1a or
When being covered with the silicon chip 1a of second metal layer 42, the actual conditions of BOSCH techniques are also not necessarily limited to above-described embodiment 1 and embodiment 2
Described in, it is generally per etching period：SF6Flow be 1sccm~300sccm, O2Flow be no more than 50sccm, the time is
1s~10s, ICP power are 500W~1500W；Radio-frequency power is no more than 50W, and rf frequency is no more than 500Hz, and duty ratio does not surpass
Cross 50%；It is generally per inaction period：C4F8Flow be 1sccm~200sccm, the time be 1s~10s, ICP power 500W
~1500W；Radio-frequency power is no more than 50W, and rf frequency is no more than 500Hz, and duty ratio is no more than 50%；Etching period and passivation
Period determines according to period, gap and the depth of the nano-pillar 12 of required preparation, during etching and passivation, silicon chip base
Bottom temperature is 10 DEG C~50 DEG C, and chamber pressure is 10mT~100mT.
Tu method is revolved when the side for boring array 11 with silicon of silicon chip 1a prepares expendable film 3a when using, low turn of general control
Speed is 200rpm~500rpm, the rotation Tu time is 20s~60s；High rotating speed is 1000rpm~2000rpm, and the rotation Tu time is 20s
~60s；And when come when preparing required sacrificial layer 3, controlling O using oxygen plasma etch technique etches sacrificial film 3a2Stream
Amount is 5sccm~50sccm, and radio-frequency power is 10W~300W, and etching temperature is 20 DEG C, and chamber pressure is that 10mT~200mT is
It can.Certainly, the preparation of expendable film 3a and reduction processing are not limited to the rotation Tu method described in above-described embodiment 1 and embodiment 2
And oxygen plasma etch technique, other prepare the method for sacrificial layer 3 between may be implemented in silicon cone array 11.
It is worth noting that ensure that 12 top of nano-pillar in the silicon-based nanometer column array 1 being prepared is bored with silicon
Array 11, the top of sacrificial layer 3 should be less than the top of silicon cone array 11；And the second gold medal for playing the role of mask prepared later
The mask area for belonging to layer 42 plays decisive role to the array pitch of nano-pillar 12, and therefore, battle array is bored in the top of sacrificial layer 3 away from silicon
The vertical range on the top of row 11 is determined according to the requirement of pre-prepared silicon-based nanometer column array 1, that is to say, that sacrificial layer 3
Thickness determined according to the requirement of pre-prepared silicon-based nanometer column array 1.When nanometer in pre-prepared silicon-based nanometer column array 1
When the array pitch of column 12 requires smaller, then the thinner thickness of sacrificial layer 3, the i.e. top of sacrificial layer 3 is required to bore array 11 away from silicon
Top vertical range it is larger, then silicon element of a cone is longer in the silicon cone array 11 covered by second metal layer 42；And when pre-
When the array pitch of nano-pillar 12 requires larger in the silicon-based nanometer column array 1 of preparation, then the top of sacrificial layer 3 is required to be bored away from silicon
The vertical range on the top of array 11 is smaller, then the silicon element of a cone in the silicon cone array 11 covered by second metal layer 42 compared with
It is short.
On the other hand, it is also affected by the length of silicon element of a cone in silicon that second metal layer 42 covers cone array 11 prefabricated
The diameter of nano-pillar 12 in standby silicon-based nanometer column array 1.
Certainly, it if the array pitch of nano-pillar 12 requires to differ in size in pre-prepared silicon-based nanometer column array 1, is making
When standby sacrificial layer 3, by controlling preparation process, sacrificial layer 3 of varying thickness is prepared, in this way, when sacrificial layer 3 and being located at it
After the first metal layer 41 on surface is stripped, it is covered in the size of the second metal layer 42 at each silicon vertex of a cone end in silicon cone array 11
It is then different；When being covered with the silicon chip 1a of second metal layer 42 using inductively coupled plasma etching technique etching, that is, form
The silicon-based nanometer column array 1 that array pitch does not wait.
Although the present invention has shown and described with reference to specific embodiment, it should be appreciated by those skilled in the art that：
In the case where not departing from the spirit and scope of the present invention limited by claim and its equivalent, can carry out herein form and
Various change in details.
Claims (10)
1. a kind of preparation method of silicon-based nanometer column array, which is characterized in that including：
Silicon is formed on the surface of silicon chip and bores array, and the silicon cone array includes several silicon cone；
Sacrificial layer is prepared between the silicon cone that the silicon bores array；Wherein, the top of the sacrificial layer is no more than silicon cone battle array
The top of row；
Deposited over arrays metal is bored in the sacrificial layer and the silicon, to form the first metal layer on the surface of the sacrificial layer
And form second metal layer on the surface that the silicon bores array；
Remove the sacrificial layer and the first metal layer；
Using the second metal layer as mask, etching is covered with the silicon chip of the second metal layer, obtains silicon-based nanometer column array.
2. preparation method according to claim 1, which is characterized in that form the silicon cone battle array on the surface of the silicon chip
The method of row specifically includes：
Hydrophilic activation process is carried out to the silicon chip, makes the surface of the silicon chip that there is hydrophily；
Nanometer ball array is prepared on the surface of the silicon chip；
Using the nanometer ball array as mask, etching is covered with the silicon chip of the nanometer ball array, on the surface of the silicon chip
It is upper to form the silicon cone array.
3. preparation method according to claim 2, which is characterized in that the material of the nanometer ball array is polystyrene,
And/or in the nanometer ball array nanosphere a diameter of 10nm~1000nm.
4. preparation method according to claim 2, which is characterized in that etching be covered with the nanometer ball array silicon chip,
And the method for etching the silicon chip for being covered with the second metal layer is all made of inductively coupled plasma etching technique, and alternately make
Use SF6And C4F8It performs etching and is passivated.
5. preparation method according to claim 4, which is characterized in that described that SF is used alternatingly6And C4F8Perform etching with it is blunt
The condition of change is：Per etching period SF6Flow be 1sccm~300sccm, O2Flow be no more than 50sccm, the time be 1s~
10s, ion source power are 500W~1500W, and radio-frequency power is no more than 50W, and rf frequency is no more than 500Hz, and duty ratio does not surpass
Cross 50%；Per inaction period C4F8Flow be 1sccm~200sccm, the time be 1s~10s, ion source power be 500W~
1500W, radio-frequency power are no more than 50W, and rf frequency is no more than 500Hz, and duty ratio is no more than 50%；Silicon chip base reservoir temperature is 10
DEG C~50 DEG C, chamber pressure is 10mT~100mT.
6. preparation method according to claim 1, which is characterized in that the first metal layer and the second metal layer
Thickness is 10nm~100nm；The first metal layer and the material of the second metal layer be selected from Ti, Al, Ni, Au, Ge,
Any one in Cr, Pt.
7. preparation method according to claim 1, which is characterized in that described in being prepared between the silicon cone that the silicon bores array
The method of sacrificial layer specifically includes：
Sacrificial layer material is coated using rotation Tu method, expendable film is formed between the silicon cone that the silicon bores array；
Using expendable film described in oxygen plasma etch technique reduction processing, between the silicon cone that the silicon bores array described in formation
Sacrificial layer；Wherein, the top of the sacrificial layer is no more than the top of silicon cone array.
8. preparation method according to claim 7, which is characterized in that the silicon for boring array in the silicon using rotation Tu method bores it
Between coat the condition of the sacrificial layer material and be：In rotating speed backspin Tu 20s~60s of 200rpm~500rpm, then in 1000rpm
Rotating speed backspin Tu 20s~60s of~2000rpm；
Use the condition of expendable film described in oxygen plasma etch technique reduction processing for：O2Flow be 5sccm~50sccm,
Radio-frequency power is 10W~300W, and etching temperature is 20 DEG C~25 DEG C, and chamber pressure is 10mT~200mT.
9. preparation method according to any one of claims 1 to 8, which is characterized in that the sacrificial layer material is poly- methyl-prop
E pioic acid methyl ester.
10. preparation method according to claim 2, which is characterized in that prepare the nanometer on the surface of the silicon chip
The method of ball array is selected from gas-liquid interface construction from part, natural sedimentation, rotation Tu method, vertical deposition method, convection current self-assembly method, electrophoresis
Assist any one in sedimentation, colloid epitaxy.
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