CN106793246B - Leadage circuit and its control method and LED control circuit - Google Patents
Leadage circuit and its control method and LED control circuit Download PDFInfo
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- CN106793246B CN106793246B CN201611030982.4A CN201611030982A CN106793246B CN 106793246 B CN106793246 B CN 106793246B CN 201611030982 A CN201611030982 A CN 201611030982A CN 106793246 B CN106793246 B CN 106793246B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
- H05B45/37—Converter circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
Abstract
The invention discloses a kind of leadage circuit and its control methods and LED control circuit, the present invention is applied to the LED control circuit of controllable silicon light modulation, directly or indirectly detection input voltage zero crossing, after being delayed for the second time at input voltage zero crossing, to generate leakage current, controllable silicon dimmer turn-on instant and driving circuit input current reach time of the predetermined value (the maintenance electric current of controllable silicon dimmer) between the moment at the first time for module of releasing work.Within first time time, leadage circuit generates loss, when first time being greater than predetermined value, extends for the second time；When first time being less than predetermined value, shortened for the second time, so that the time is close or equal to predetermined value at the first time.Using the present invention, power consumption of releasing adaptively can be reduced, and improve system effectiveness to adjust the second time as delay time according to the size of first time and predetermined value.
Description
Technical field
The present invention relates to power electronics fields, and in particular to a kind of leadage circuit and its control method and LED control
Circuit.
Background technique
LED light due to its environmental protection more more energy efficient than traditional fluorescent lamp and incandescent lamp, so LED light slowly replacing it is existing
Fluorescent lamp and incandescent lamp.In the incandescent lamp with controllable silicon dimmer, similarly wish to use LED light to replace, thus
LED needs compatible silicon controlled light modulator.But by LED light come replace incandescent lamp application in, due in controlled silicon conducting,
Its output end voltage has biggish voltage change ratio (dv/dt), causes to generate biggish surge current in input terminal.This surge
Current oscillation amplitude is big, and the duration is short, and silicon-controlled mistake is easily caused to turn off, and influences the steady operation of LED drive circuit, makes
LED light generates flashing；In addition, the input current of silicon-controlled device, which need to be greater than it, maintains electric current, electricity is maintained when input current is less than
When stream, silicon-controlled shutdown is easily caused, also results in the flashing of LED.In order to solve the above-mentioned technical problem, in the prior art
Using following scheme, but there are still certain technological deficiencies.
Circuit diagram as shown in Figure 1 illustrates the leadage circuit of the prior art, i.e. current source I10 and adjustment pipe M00
It is composed in series leadage circuit, current source I10 can be replaced with resistance.When controllable silicon dimmer conducting, linear LED drive circuit
When electric current is difficult to reach the maintenance electric current of controllable silicon dimmer, the adjustment pipe M00 of leadage circuit is connected, and leadage circuit generation is released
Electric current iblr, so that input current can achieve maintenance electric current.As shown in Fig. 2, illustrating input voltage vin and input current
The waveform of iin, the electric current that dash area, that is, leadage circuit generates, this part leakage current can bring additional power consumption.And it can
Control silicon dimmer conduction angle is bigger, and the time t1 that leadage circuit generates leakage current iblr is longer, and bigger, transfer efficiency is lost
It is lower.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of small power consumption, high-efficient leadage circuit and its method and LED
Control circuit, to solve technical problem of the existing technology.
The technical solution of the invention is as follows, provides a kind of leadage circuit with flowering structure, comprising:
It releases module, exchange input obtains input voltage through controllable silicon dimmer and rectifier bridge and supplies through driving circuit load
Electricity, the both ends of the module of releasing are connect with the high cold end of input voltage respectively；
It releases control circuit, is connect with the control terminal of the module of releasing；Directly or indirectly detection input voltage zero crossing,
Input voltage zero crossing be delayed the second time after, module of releasing described in control generate leakage current, the driving circuit it is defeated
Enter electric current to reach the predetermined value moment then to control leakage current be zero；Controllable silicon dimmer turn-on instant is defeated with the driving circuit
Enter electric current and reaches the time between the predetermined value moment at the first time；
Wherein, when the first time being greater than the reference time, then extended for the second time；It is less than reference when first time
When the time, then shortened for the second time, so that leveling off to the reference time at the first time.
Preferably, the control circuit of releasing includes input voltage detection circuit, driving circuit input electric cur- rent measure
Circuit and logic circuit, the logic circuit are connect with the control terminal for module of releasing, and the input voltage detection circuit is adopted
Sample input voltage then after second time that was delayed, is controlled when input voltage sampled signal reaches threshold voltage through logic circuit
The module of releasing generates leakage current；The driving circuit input electric cur- rent measure circuit detects driving circuit input current,
It is then zero through logic circuit control leakage current when sample rate current reaches the threshold current of characterization predetermined value；By described first
Time is compared with the reference time, and second time is correspondingly adjusted according to comparison result.
Preferably, the control circuit of releasing further includes time delay module and time comparison module, the delay mould
Block is connect with the output end of input voltage detection circuit, logic circuit and time comparison module respectively, and the time delay module exists
The second time of delay is carried out when input voltage sampled signal reaches threshold voltage, after delay, is controlled by logic circuit
Leakage current is generated, is carried out at the first time compared with the reference time in the time comparison module, and knot will be compared
Fruit feeds back to the time delay module to adjust second time.
Preferably, the logic circuit includes the first trigger and the second trigger, the time delay module output
The status signal whether characterization delay terminates, the set end of first trigger receive the shape whether the characterization delay terminates
State signal, the output end of input voltage detection circuit and the output end of time delay module are respectively connected to NAND gate, the NAND gate
Output end is connect with the resetting end of first trigger；The output end of first trigger triggers after negating with described second
The set end of device connects, and the output end of driving circuit input electric cur- rent measure circuit negates rear and second trigger resetting end
The output end of connection, the output end of second trigger and the driving circuit input electric cur- rent measure circuit is separately connected and door
Two input terminals, the output end of the output end with door and the first trigger is separately connected or two input terminals of door, institute
State or door output characterization whether Shi Neng signal is to the module of releasing, when the output end output with door is for characterization first
Between timing signal.
Preferably, the control circuit of releasing includes driving circuit input electric cur- rent measure circuit, leakage current detection
Circuit and logic circuit, the logic circuit are connect with the control terminal for module of releasing, the driving circuit input current inspection
Slowdown monitoring circuit samples driving circuit input current, and is compared with threshold current；The leakage current detection circuit is inputting
During voltage zero-cross detects, module of releasing described in the logic circuit control generates leakage current, samples the leakage current, and
Threshold value is compared with releasing；When the driving circuit input current is lower than the threshold current, starts timing, let out until described
Discharge stream reaches when releasing threshold value, and timing terminates, and the timing time is as the third time.
When the driving circuit input current is lower than the threshold current, judge that input voltage reaches after the third time
To zero crossing；And it can timing or not timing update third time.
Preferably, when judging that input voltage reaches zero crossing, be delayed after the second time, control through logic circuit described in
Module of releasing generates leakage current；The driving circuit input electric cur- rent measure circuit detects driving circuit input current, when adopting
It is then zero through logic circuit control leakage current when sample electric current reaches the threshold current of characterization predetermined value；By the first time
It is compared with the reference time, second time is correspondingly adjusted according to comparison result.
Preferably, the control circuit of releasing further includes time delay module, time comparison module and zero passage judgment module,
The time delay module is connect with the output end of zero passage judgment module, logic circuit and time comparison module respectively, the zero passage
Judgment module is connect with the output end of the output end of leakage current detection circuit and driving circuit input electric cur- rent measure circuit respectively；
Timing is carried out to the third time by the zero passage judgment module, and judges the zero passage point moment of input voltage, the delay mould
Block receives the signal of the characterization zero passage point moment of the zero passage judgment module output, and is delayed for the second time, after delay, leads to
It crosses logic circuit control and generates leakage current, the ratio of first time and the reference time are carried out in the time comparison module
Compared with, and comparison result is fed back into the time delay module to adjust second time.
Preferably, the logic circuit includes third trigger and the 4th trigger, the time delay module output
The status signal whether characterization delay terminates, the set end of the third trigger receive the shape whether the characterization delay terminates
State signal, the output end of zero passage judgment module and the output end of time delay module are respectively connected to NAND gate, the output of the NAND gate
End is connect with the resetting end of the third trigger；The output end of the third trigger negates rear and the 4th trigger
Set end connection, the output end of driving circuit input electric cur- rent measure circuit negate the rear resetting end with the 4th trigger and connect
Connect, the output end of the 4th trigger and the output end of the driving circuit input electric cur- rent measure circuit be separately connected first with
Two input terminals of door, the letter whether output end and characterization zero passage judgment module of driving circuit input electric cur- rent measure circuit enable
Number it is respectively connected to two input terminals of second Yu door；Described first touches with the output end of door, second with the output end and third of door
The output end of hair device is separately connected or three input terminals of door, and described or door output characterization whether release to described by Shi Neng signal
Module, described first exports the timing signal for characterizing first time with the output end of door.
Another technical solution of the invention is to provide a kind of control method of the leadage circuit of following steps:
Exchange input obtains input voltage through driving circuit to load supplying through controllable silicon dimmer and rectifier bridge, mould of releasing
The both ends of block are connect with the high cold end of input voltage respectively；
Directly or indirectly detection input voltage zero crossing, after input voltage zero crossing was delayed for the second time, described in control
Module of releasing generates leakage current, and the input current of the driving circuit reaches the predetermined value moment, and then to control leakage current be zero；
The input current of controllable silicon dimmer turn-on instant and the driving circuit reach the time between the predetermined value moment be first when
Between；
Wherein, when the first time being greater than the reference time, then extended for the second time；It is less than reference when first time
When the time, then shortened for the second time, so that leveling off to the reference time at the first time.
Another technical solution of the invention is to provide a kind of LED control circuit with flowering structure, comprising: to take up an official post
It anticipates a kind of leadage circuit and LED drive circuit, the LED drive circuit is linear drive circuit or switching circuit.
Using circuit structure and method of the invention, compared with prior art, have the advantage that the present invention be applied to can
The LED control circuit of silicon light modulation is controlled, input voltage zero crossing is directly or indirectly detected, the delay second at input voltage zero crossing
After time, module of releasing works to generate leakage current, and controllable silicon dimmer turn-on instant reaches with driving circuit input current
Time of the predetermined value (the maintenance electric current of controllable silicon dimmer) between the moment is at the first time.Within first time time, let out
Road generation loss of discharging extended for the second time when first time being greater than predetermined value；When first time being less than predetermined value, contracting
Short second time, so that the time is close or equal to predetermined value at the first time.Using the present invention, can adaptively according to first when
Between size with predetermined value reduce power consumption of releasing to adjust the second time as delay time, and improve system effect
Rate.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the silicon-controlled LED control circuit using leadage circuit of the prior art；
Fig. 2 is the working waveform figure of prior art Fig. 1；
Fig. 3 is the working waveform figure of leadage circuit of the present invention；
Fig. 4 is flow diagram of the invention；
Fig. 5 is the circuit structure diagram of leadage circuit embodiment one of the present invention；
Fig. 6 is the flow diagram of the logic circuit of leadage circuit embodiment one of the present invention；
Fig. 7 is the structural schematic diagram of logic circuit in leadage circuit embodiment one of the present invention；
Fig. 8 is the structural schematic diagram of time comparison module in leadage circuit embodiment one of the present invention；
Fig. 9 is the structural schematic diagram of time delay module in leadage circuit embodiment one of the present invention；
Figure 10 is the working waveform figure of leadage circuit embodiment one of the present invention；
Figure 11 is the circuit structure diagram of leadage circuit embodiment two of the present invention；
Figure 12 is the flow diagram of the logic circuit of leadage circuit embodiment two of the present invention；
Figure 13 is the structural schematic diagram of logic circuit in leadage circuit embodiment two of the present invention；
Figure 14 is the flow diagram of zero passage judgment module in leadage circuit embodiment two of the present invention；
Figure 15 is the working waveform figure of leadage circuit embodiment two of the present invention.
Specific embodiment
The preferred embodiment of the present invention is described in detail below in conjunction with attached drawing, but the present invention is not restricted to these
Embodiment.The present invention covers any substitution made in the spirit and scope of the present invention, modification, equivalent method and scheme.
In order to make the public have thorough understanding to the present invention, it is described in detail in the following preferred embodiment of the present invention specific
Details, and the present invention can also be understood completely in description without these details for a person skilled in the art.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It should be noted that attached drawing is adopted
With more simplified form and using non-accurate ratio, only to facilitate, lucidly aid in illustrating the embodiment of the present invention
Purpose.
Refering to what is shown in Fig. 3, illustrating the work wave of leadage circuit of the present invention.Input voltage vin, input are illustrated in figure
The waveform of electric current iin and leakage current iblr.By directly or indirectly detecting input voltage vin zero crossing, reached in input voltage
It is then delayed after the second time t2 when to zero crossing, control leadage circuit generates leakage current iblr, when controllable silicon dimmer is connected
Carve and driving circuit input current iin2 reach predetermined value (the generally maintenance electric current of controllable silicon dimmer) between the moment when
Between be first time t1.In first time t1, leadage circuit generates loss, when t1 is greater than predetermined value T, increases for the second time
t2；When t1 is less than predetermined value T, reduce the second time t2, so that first time time t1 is close or equal to predetermined value T.In figure,
+ VF and-VF is equal to the conduction threshold of diode.
Refering to what is shown in Fig. 4, illustrating the flow diagram of leadage circuit of the present invention.First judge input voltage vin whether zero passage,
It is positioned proximate to be compared in zero threshold voltage with sampled voltage, input voltage vin can also be obtained indirectly by other amounts
At the time of zero passage.The input voltage vin is exchange input through the obtained input voltage vin of controllable silicon dimmer.Defeated
Enter voltage over zero to be delayed after the second time t2, module of releasing described in control is enabled to generate leakage current iblr.When input electricity
After pressing Vin zero passage, start timing, the input current iin2 of the driving circuit reaches predetermined value (generally using controllable silicon light modulation
The maintenance size of current of device) moment, then leadage circuit does not enable, and leakage current zero, timing terminates at this time；Above-mentioned timing time
As the input current of controllable silicon dimmer turn-on instant and the driving circuit reaches the time between the predetermined value moment, is the
One time t1.When the first time t1 is greater than reference time T, then extend the second time t2；When first time t1 is less than
When reference time T, then shorten the second time t2, so that leveling off to reference time T at the first time.This method shortens when releasing
Between, reduce power consumption of releasing, lifting system efficiency.
Refering to what is shown in Fig. 5, the circuit structure of leadage circuit embodiment one of the present invention is illustrated, applied to controllable silicon light modulation
In LED control circuit.LED control circuit includes leadage circuit and LED drive circuit, and the leadage circuit includes module of releasing
With control circuit of releasing, the leadage circuit be used to solve under controllable silicon dimmer as input current it is too small caused by
Flicker problem, and overcome technological deficiency present in the prior art.Its input power is exchange input, and the exchange input warp can
The input voltage vrec that direct current is exported after control silicon light modulator U02 and rectifier bridge U01, i.e., as the input voltage of LED load.Exchange
Input is connected to rectifier bridge U01 by controllable silicon dimmer U02, and the positive output end of rectifier bridge is connect with the anode of diode D00,
LED drive circuit anode is connect with the cathode of the diode D00.Certain capacitive can be presented in usual LED drive circuit, therefore,
Diode D00 is added between vrec and LED drive circuit；When exchange input absolute value reduce when, LED drive circuit due to
With capacitive, voltage can reduce relatively slow, and the sampling resistor that joined diode D00 and input voltage vrec detection circuit can will
The absolute value of vrec voltage follow exchange input, to guarantee the accuracy sampled to input voltage.
The leadage circuit includes releasing module and to release control circuit, the module of releasing include adjustment pipe and with
Concatenated current source or resistance are managed in the adjustment.Main improvement of the invention is release control circuit and corresponding controlling party
Method.The control circuit of releasing includes input voltage vrec detection circuit, driving circuit input electric cur- rent measure circuit and logic
Circuit U 12, the logic circuit U12 are connect with the control terminal for the module U03 that releases, the input voltage vrec detection circuit
Sampled input voltage (is compared), then when input voltage sampled signal reaches threshold voltage VREF1 in comparator U10
After the second time t2 that is delayed, leakage current iblr is generated through the module U03 that releases described in logic circuit U12 control；The drive
Dynamic circuit input electric cur- rent measure circuit detects driving circuit input current iin2, when sample rate current reaches the threshold value of characterization predetermined value
It (is compared in comparator U40) when electric current VREF4, is then zero through logic circuit U12 control leakage current iblr；It will be described
First time t1 is compared with the reference time T, and the second time t2 is correspondingly adjusted according to comparison result.When described
Driving circuit be linear drive circuit when, the electric current of the adjustment pipe M30 of the linear driving circuit of sample streams can be used to characterize
The input current in2 of the driving circuit.
The control circuit of releasing further includes time delay module U13 and time comparison module U14, the time delay module U13
Input voltage crossover point signal ZVD for generating to input voltage vrec detection circuit is delayed, and after delay,
Signal is passed into logic circuit U12, so that the module U03 that releases is enabled.When the time comparison module U14 is used for first
Between t1 be compared with the reference time T, to realize feedback regulation to the second time t2.The time delay module U13 points
It is not connect with the output end of input voltage vrec detection circuit, logic circuit U12 and time comparison module U13, the delay
Module U13 is carrying out the second time t2 of delay when input voltage sampled signal reaches threshold voltage VREF1, after delay,
It is controlled by logic circuit U12 and generates leakage current iblr, first time t1 and institute are carried out in the time comparison module U14
The comparison of reference time T is stated, and comparison result is fed back into the time delay module to adjust the second time t2.
Refering to what is shown in Fig. 6, illustrating the flow diagram of one logic circuit U12 of leadage circuit embodiment of the present invention.This attached drawing
In conjunction with Fig. 5, the specific implementation step of embodiment one is obtained are as follows: the initial value of t2 is 0.AC power source through controllable silicon dimmer U02,
Voltage vrec after rectifier bridge U01, after being rectified.Resistance R10, R11 divide vrec, the voltage on resistance R11
When lower than reference voltage VREF1, the output ZVD of comparator U10 is overturn, and the starting point as input voltage vrec zero crossing is believed
Number.The negative input end of comparator U10 is connected to R11, reference voltage is connected to for the positive input terminal of comparator U10.When defeated
When entering voltage zero-cross, voltage is lower than VREF1 on resistance R11, then the output ZVD of comparator U10 becomes high level from low level.
The high level signal of ZVD is delayed after t2 through delay circuit U13, delay circuit output signal ZVDLY overturning, and is input to logic electricity
Leadage circuit enabler flags position EN is set 1 by road U12, logic circuit U12, and leadage circuit is enabled, and busbar voltage vrec is pulled down to
Close to 0V.When the output ZVD of comparator U10 is low, i.e. t01 moment in Fig. 3, logic circuit U12 starts timing, timing signal
BLT is got higher from low.Driving circuit input electric cur- rent measure circuit detects iin2 electric current, when voltage RS is low on current sampling resistor R40
When reference voltage VREF4, i.e. between t01-t02, leadage circuit U03 continues to enable.When voltage RS is higher than reference voltage VREF4
When, the output signal ZC overturning of comparator U40, logic circuit U12 timing terminates timing signal BLT and is lower by height, released simultaneously
Circuit U 03 does not enable, i.e., leadage circuit does not generate leakage current.T01-t02 is the time t1 that leadage circuit generates power consumption, i.e.,
BLT is exported between t01-t02 as height.Timing signal BLT is connected to the input terminal of time comparison circuitry U14, when t1 is greater than T
When, time comparison circuitry U14 output delay direction flag BLDIR is high level；Conversely, delay direction flag BLDIR is
Low level.Delay circuit U13 according to delay direction flag BLDIR adjustment input voltage crossover point signal ZVD after delay when
Between t2, t1 is adjusted to T or close to T.Wherein delay t2 minimum value is 0, is up to half of power frequency period or more.
Refering to what is shown in Fig. 7, illustrating the circuit structure of logic circuit in leadage circuit embodiment one of the present invention.Described patrols
Collecting circuit includes the first trigger U12_1 and the second trigger U12_5, and whether the time delay module output characterization delay terminates
Status signal ZVDLY, the set end S of first trigger receives the status signal whether the characterization delay terminates
ZVDLY, the output end of input voltage detection circuit and the output end of time delay module U13 are respectively connected to NAND gate U12_2, it is described with
The output end of NOT gate U12_2 is connect with the resetting end R of the first trigger U12_1；The output of the first trigger U12_1
End negates the rear set end with second trigger and connect, the output end of driving circuit input electric cur- rent measure circuit negate afterwards and
The resetting end R connection of the second trigger U12_5, the output end and the driving circuit of the second trigger U12_5 are defeated
The output end for entering current detection circuit is separately connected two input terminals with door U12_4, the output end with door U12_4 and the
The output end of one trigger U12_1 is separately connected or two input terminals of door U12_3, and whether described or door U12_3 output characterization
Enabled signal EN to the module U03 that releases, it is described to export the timing for characterizing first time with door U12_4 output end
Signal BLT.Although giving the structure of a specific logic circuit above, it can be replaced, and be not limited to
Above structure.
Refering to what is shown in Fig. 8, illustrating the circuit structure of time comparison module in leadage circuit embodiment one of the present invention.Logic
Effective time signal B LT control switch S14_1, S14_2 of releasing that circuit U 12 generates, when BLT is high, S14_1 is connected, electric current
Source I14 charges to capacitor C14, and high level signal, delay plus-minus mark are exported when capacitor C14 voltage is greater than reference voltage VREF14
Will signal BLDIR is height, while counter U14_6 being reset, and illustrates that delay time needs to lengthen；When BLT is low, S14_2 is led
Logical C14 electric discharge.
T=C14*Vref14/I14；
When the BLT time being shorter than T, the duration is more than T5, and counter U14_6 adds counting to generate carry, and U14_5 resets,
BLDIR be it is low, illustrate delay time needs shorten.
T5=TCLK14*2N1
Wherein N1 is the digit of counter U14_6.
Refering to what is shown in Fig. 9, illustrating the circuit structure of time delay module in leadage circuit embodiment one of the present invention.Delay plus-minus
Plus-minus counting enable signal of the flag bit as counter U13_1, U13_2；Clock signal of the CLK13 as counter U13_2,
Its period is the minimum step of delay；When input voltage zero passage, ZVD signal is high level, and R/S trigger U13-5 output is high
Level is made until R/S trigger U13-5 output resets, and generates ZVDC signal when driving circuit input current flag bit ZC sets 0
For the clock signal of counter U13-1.When delay plus-minus flag signal BLDDIR is 1, counter U13_1, U13_2 add meter
Number；When delay plus-minus flag signal BLDDIR is 0, counter U13_1 subtracts counting, counter U13_2 adds counting.Work as counting
When device U13_1, U13_2 count value is identical, biconditional gate U13_3 exports high level, exports high level with door U13_4, ZVDLY is defeated
High level out, as ZVD delay after zero cross signal, after through logic circuit U12 generate leadage circuit enable signal.
Refering to what is shown in Fig. 10, illustrating the work wave of leadage circuit embodiment one of the present invention.Illustrate input voltage
The corresponding specific waveform of Vin, input current iin, leakage current iblr, enable signal EN and sampled signal RS.By in figure
As can be seen that the leakage current iblr working time is longer in initial power-on, after delay process, the iblr time is shorter and shorter,
It releases within time T until maintaining minimum, ensure that leadage circuit has lower power consumption.
With reference to shown in Figure 11, the circuit structure of leadage circuit embodiment two of the present invention is illustrated.This scheme may not need defeated
Enter voltage vrec detection circuit, can also achieve the effect that above scheme, to simplify peripheral element, i.e., detects by other means
The zero crossing of input voltage vrec, but need to increase leakage current iblr detection circuit.
In the present embodiment, the control circuit of releasing includes driving circuit input electric cur- rent measure circuit, leakage current inspection
Slowdown monitoring circuit and logic circuit U11, the logic circuit U11 are connect with the control terminal for the module U03 that releases, the driving circuit
Input electric cur- rent measure circuit sampling driving circuit input current, and be compared with threshold current, the leakage current detection
For circuit when input voltage zero passage detection is enabled, module of releasing described in the logic circuit control generates leakage current, and samples
The leakage current is sampled by resistance R50, and is compared with threshold value of releasing (being characterized with VREF4)；The driving circuit
When input current is lower than the threshold current VREF4 (Low threshold for being close to zero of reference signal characterization), i.e. driving is electric
Road input current starts timing, when the leakage current iblr, which reaches, releases threshold value, timing knot close to zero or zero passage
Beam, the timing time are reached after the threshold current again through by the driving circuit input current as third time T3
Judge that input voltage reaches zero crossing at the time of three time T3.
It when judging that input voltage reaches zero crossing, is delayed after the second time t2, through releasing described in logic circuit U11 control
Module generates leakage current iblr；The driving circuit input electric cur- rent measure circuit detects driving circuit input current, when adopting
It is then zero through logic circuit U11 control leakage current iblr when sample electric current reaches the threshold current of characterization predetermined value；By described
One time t1 is compared with the reference time T, and the second time t2 is correspondingly adjusted according to comparison result.
The control circuit of releasing further includes time delay module U13, time comparison module U14 and zero passage judgment module U15,
The time delay module U13 connects with the output end of zero passage judgment module U15, logic circuit U11 and time comparison module U14 respectively
It connects, the zero passage judgment module U15 is electric with the output end of leakage current detection circuit and driving circuit input electric cur- rent measure respectively
The output end on road connects；Timing is carried out to third time T3 by the zero passage judgment module, and judges the zero crossing of input voltage
Moment, the time delay module receive the signal of the characterization zero passage point moment of the zero passage judgment module output, and delay second
Time t2 after delay, is controlled by logic circuit U11 and is generated leakage current iblr, in the time comparison module U14
First time t1 is carried out with the reference time T compared with, and comparison result fed back into the time delay module with described in adjusting
Second time t2.
With reference to shown in Figure 12, the flow diagram of two logic circuit U11 of leadage circuit embodiment of the present invention is illustrated.This attached drawing
In conjunction with Figure 11, the specific implementation step of embodiment two is obtained are as follows:
The initial value of second time t2 is 0.AC power source is rectified after controllable silicon dimmer U02, rectifier bridge U01
Voltage vrec afterwards.Input voltage zero passage detection enable signal CTL is used for the detection of input voltage zero-crossing timing third time, and
And in order to guarantee the accuracy of third time while reduce power consumption of releasing, CTL can be the square-wave signal far below work frequency.
When powering on for the first time, input voltage zero passage detection enable signal CTL is high level, as long as the electricity of driving circuit input current sampling at this time
It hinders R40 voltage RS and is lower than reference voltage Vref 4, comparator U40 output end is high level, and leadage circuit U03 is in enabled work
State.When input voltage is higher, LED current is big, and driving circuit sampling resistor R40 voltage is higher than VREF4, comparator U40 output
Low level, input voltage zero cross signal ZVD is low level at this time；When input voltage is reduced by height, driving circuit input current is adopted
Sample resistance R40 voltage reduces, and when driving circuit input current sampling resistor R40 voltage RS is lower than VREF4, comparator U40 is defeated
It overturns out, leadage circuit U03 is enabled, and input voltage zero-crossing detection circuit U15 starts timing；Leakage current iblr sampling resistor
R50 voltage is higher than reference voltage VREF5, and comparator U50 exports low level；Input voltage continues to reduce, and when close to 0V, releases
Electric current iblr is decreased to close to 0, and leakage current iblr sampling resistor R50 voltage is lower than reference voltage VREF5, and comparator U50 is defeated
High level out, input voltage crossover point signal ZVD becomes high level, while input voltage zero-crossing detection circuit U15 counts knot
Beam, between timing time T3, as driving circuit input current iin2 failing edge zero crossing and input voltage zero crossing when
Between T3.
When input voltage zero passage detection enable signal CTL is low level, each power frequency period later works as driving circuit
Input current sampling resistor R40 voltage is by being higher than when reference voltage VREF4 becomes less than reference voltage VREF4 (on comparator U40
Rise edge) delay T3 generation input voltage crossover point signal ZVD.The high level signal of ZVD is delayed after t2 through time delay process U13, warp
Logic circuit U11 is crossed, leadage circuit working mark position EN is set 1 by logic circuit U11, and leadage circuit is enabled, busbar voltage vrec
It is pulled down to close to 0V.When the output ZCBLD of leakage current detection comparator U50 is low, i.e. t01 moment in Figure 15, the time
Comparison circuit U14 starts to work.Driving circuit input electric cur- rent measure circuit detects iin2 electric current, when on current sampling resistor R40
When voltage RS is lower than reference voltage VREF4, i.e. between t01-t02, leadage circuit U03 continues to enable.When voltage RS is higher than reference
When voltage VREF4, the output signal ZC of comparator U40 is overturn, and time comparison circuitry U14 work terminates, while leadage circuit U03
It does not enable, i.e., leadage circuit does not generate leakage current.It is the time t1 that leadage circuit generates power consumption from t01-t02, when t1 is big
When T, time comparison circuitry output delay direction flag BLDIR is high level；Conversely, delay direction flag BLDIR is
Low level.Delay circuit U13 according to delay direction flag BLDIR adjustment input voltage crossover point signal ZVD after delay when
Between t2, t1 is adjusted to T or close to T.Wherein delay t2 minimum value is 0, is up to half of power frequency period or more.With reference to Figure 13
It is shown, illustrate the circuit structure of logic circuit in leadage circuit embodiment two of the present invention.When input voltage zero-crossing examination makes
When energy signal CTL is high level, as long as driving circuit input current iin2 is lower than setting value, i.e. when ZC is high level, with door
U11_6 output is high level, and three inputs or door U11_3 export high level, and leadage circuit is enabled, input voltage zero-crossing examination electricity
Road U15 detects input voltage zero crossing, such as 0-t07 in Figure 15, and holding time T3.When the enabled letter of input voltage zero-crossing examination
It is low level with door U11_6 output when number CTL is low level.When driving circuit input current iin2 detection circuit ZC is by low electricity
When flat overturning is high level (t03), delay time T3, ZVD signal becomes high level from low level, even if ZC is high electricity at this time
It is flat, but R/S trigger U11_1 (the t01 moment resets), U11_5 (the t02 moment resets) export low level, are with door U11_4 output
Low level, leadage circuit do not enable.When delay circuit U13 output signal ZVDLY sets 1, R/S trigger U11_1 output is
High level, leadage circuit enable signal EN are high level, and leadage circuit is enabled, and input voltage vrec is 0, until controllable silicon light modulation
Device conducting, ZVD are low, R/S trigger U11_1 output low level, U11_5 output high level, at this time if ZC is height, with door
U11_4 exports high level, and leadage circuit enable signal EN continues as high level, silicon-controlled steady to maintain input current to guarantee
Fixed conducting；When ZC is low, U11_4, U11_5 output reset, and leadage circuit enable signal EN is low, leadage circuit stopping work
Make.It is the time signal B LT (t01~t02) that leadage circuit generates power consumption with door U11_4 output.
With reference to shown in Figure 14, the process that zero passage judgment module U15 works in leadage circuit embodiment two of the present invention is illustrated
Block diagram.It is detected by zero passage judgment module U15 and saves driving circuit input current iin2 zero crossing and leakage current iblr mistake
Zero crossing time.In the case where zero passage judgment module U15 is enabled, judge whether driving circuit input current is lower than threshold current,
When it is lower than threshold current, then module of releasing is enabled to generate leakage current.When leakage current is lower than respective threshold, then save
The moment updates third time T3.Third time T3 is to be lower the time being lower to ZCBLD by height from ZC by height.
With reference to shown in Figure 15, the work wave of leadage circuit embodiment two of the present invention is illustrated.Illustrate input voltage
The corresponding specific waveform of Vin, input current iin, leakage current iblr, enable signal EN, CTL and sampled signal RS.By
In figure as can be seen that similar to embodiment one, in initial power-on, the leakage current iblr working time is longer, through delay process
Afterwards, the iblr time is shorter and shorter, releases within time T until maintaining minimum, ensure that leadage circuit has lower power consumption.
In addition to this, although embodiment is separately illustrated and is illustrated above, it is related to the common technology in part, in this field
Those of ordinary skill apparently, can be replaced and integrate between the embodiments, be related to one of embodiment and record is not known
Content, then can refer to another embodiment on the books.
Embodiments described above does not constitute the restriction to the technical solution protection scope.It is any in above-mentioned implementation
Made modifications, equivalent substitutions and improvements etc., should be included in the protection model of the technical solution within the spirit and principle of mode
Within enclosing.
Claims (11)
1. a kind of leadage circuit, it is characterised in that: include:
It releases module, exchange input obtains input voltage through driving circuit to load supplying through controllable silicon dimmer and rectifier bridge,
The both ends of the module of releasing are connect with the high cold end of input voltage respectively；
It releases control circuit, is connect with the control terminal of the module of releasing；Directly or indirectly detection input voltage zero crossing, defeated
Enter voltage over zero to be delayed after the second time, module of releasing described in control generates leakage current, the input electricity of the driving circuit
Stream reaches the predetermined value moment, and then to control leakage current be zero；The input electricity of controllable silicon dimmer turn-on instant and the driving circuit
Stream reaches the time between the predetermined value moment at the first time；
Wherein, when the first time being greater than the reference time, then extended for the second time；It is less than the reference time when first time
When, then shortened for the second time, so that leveling off to the reference time at the first time.
2. leadage circuit according to claim 1, it is characterised in that: the control circuit of releasing includes input voltage inspection
Slowdown monitoring circuit, driving circuit input electric cur- rent measure circuit and logic circuit, the logic circuit and the control terminal for module of releasing connect
It connects, the input voltage detection circuit sampled input voltage is then prolonging when input voltage sampled signal reaches threshold voltage
When the second time after, through logic circuit control described in release module generate leakage current；The driving circuit input current inspection
Slowdown monitoring circuit detects driving circuit input current, when sample rate current reaches the threshold current of characterization predetermined value, then through logic circuit
Controlling leakage current is zero；The first time is compared with the reference time, is correspondingly adjusted according to comparison result
Second time.
3. leadage circuit according to claim 2, it is characterised in that: the control circuit of releasing further includes time delay module
With time comparison module, the time delay module respectively with the output end of input voltage detection circuit, logic circuit and time ratio
It being connected compared with module, the time delay module is carrying out the second time of delay when input voltage sampled signal reaches threshold voltage,
It after delay, is controlled by logic circuit and generates leakage current, first time and institute are carried out in the time comparison module
The comparison of reference time is stated, and comparison result is fed back into the time delay module to adjust second time.
4. leadage circuit according to claim 3, it is characterised in that: the logic circuit includes the first trigger and the
Two triggers, the status signal whether the time delay module output characterization delay terminates, the set end of first trigger
Receive the status signal whether the characterization delay terminates, the output end of input voltage detection circuit and the output end of time delay module
It is respectively connected to NAND gate, the output end of the NAND gate is connect with the resetting end of first trigger；First trigger
Output end negate the rear set end with second trigger and connect, the output end of driving circuit input electric cur- rent measure circuit takes
It is connect after anti-with the resetting end of second trigger, the output end of second trigger and the driving circuit input current
The output end of detection circuit is separately connected two input terminals with door, described and the output end of door and the output end of the first trigger
Be separately connected or two input terminals of door, whether Shi Neng signal is to the module of releasing for described or door output characterization, it is described and
The output end of door exports the timing signal for characterizing first time.
5. leadage circuit according to claim 1, it is characterised in that: the control circuit of releasing includes that driving circuit is defeated
Enter current detection circuit, leakage current detection circuit and logic circuit, the logic circuit and the control terminal for module of releasing connect
It connects, the driving circuit input electric cur- rent measure circuit sampling driving circuit input current, and is compared with threshold current；Institute
The leakage current detection circuit stated during input voltage zero passage detection, let out by module generation of releasing described in the logic circuit control
Discharge stream samples the leakage current, and is compared with threshold value of releasing；The driving circuit input current is lower than the threshold value
When electric current, driving circuit input current starts timing, until the leakage current reaches threshold value of releasing close to zero or zero passage
When, timing terminates, and the timing time is as the third time.
6. leadage circuit according to claim 5, it is characterised in that: be lower than the threshold in the driving circuit input current
When being worth electric current, judge that input voltage reaches zero crossing after the third time；And timing or not timing update the third time.
7. leadage circuit according to claim 5, it is characterised in that: when judging that input voltage reaches zero crossing, delay
After second time, through logic circuit control described in release module generate leakage current；The driving circuit input electric cur- rent measure
Circuit detects driving circuit input current, when sample rate current reaches the threshold current of characterization predetermined value, then through logic circuit control
Leakage current processed is zero；The first time is compared with the reference time, institute is correspondingly adjusted according to comparison result
Stated for the second time.
8. leadage circuit according to claim 7, it is characterised in that: the control circuit of releasing further includes delay mould
Block, time comparison module and zero passage judgment module, the time delay module are electric with the output end of zero passage judgment module, logic respectively
Road is connected with time comparison module, the zero passage judgment module respectively with the output end and driving circuit of leakage current detection circuit
The output end of input electric cur- rent measure circuit connects；Timing is carried out to the third time by the zero passage judgment module, and judges to input
The zero passage point moment of voltage, the time delay module receive the letter of the characterization zero passage point moment of the zero passage judgment module output
Number, and be delayed for the second time, after delay, is controlled by logic circuit and generate leakage current, in the time comparison module
Comparison result is fed back to the time delay module to adjust described the at the first time compared with the reference time by middle progress
Two times.
9. leadage circuit according to claim 8, it is characterised in that: the logic circuit includes third trigger and
Four triggers, the status signal whether the time delay module output characterization delay terminates, the set end of the third trigger
Receive the status signal whether the characterization delay terminates, the output end of zero passage judgment module and the output end difference of time delay module
NAND gate is accessed, the output end of the NAND gate is connect with the resetting end of the third trigger；The third trigger it is defeated
Outlet negates the rear set end with the 4th trigger and connect, after the output end of driving circuit input electric cur- rent measure circuit negates
It is connect with the resetting end of the 4th trigger, the output end and the driving circuit input electric cur- rent measure of the 4th trigger
The output end of circuit is separately connected two input terminals of first Yu door, the output end and table of driving circuit input electric cur- rent measure circuit
The signal whether zero judgment module enables of going on a punitive expedition is respectively connected to two input terminals of second Yu door；Described first with the output of door
End, second are separately connected or three input terminals of door with the output end of the output end of door and third trigger, the output of described or door
Whether Shi Neng signal is to the module of releasing for characterization, described first with the output end output of door by characterizing based on first time
When signal.
10. a kind of control method of leadage circuit, it is characterised in that:
Exchange input obtains input voltage through driving circuit to load supplying through controllable silicon dimmer and rectifier bridge, module of releasing
Both ends are connect with the high cold end of input voltage respectively；
Directly or indirectly detection input voltage zero crossing is released described in control after input voltage zero crossing was delayed for the second time
Module generates leakage current, and the input current of the driving circuit reaches the predetermined value moment, and then to control leakage current be zero；Controllably
The input current of silicon dimmer conduction moment and the driving circuit reaches the time between the predetermined value moment at the first time；
Wherein, when the first time being greater than the reference time, then extended for the second time；It is less than the reference time when first time
When, then shortened for the second time, so that leveling off to the reference time at the first time.
11. a kind of LED control circuit, it is characterised in that: driven including above any one leadage circuit of claim 1-9 and LED
Dynamic circuit, the LED drive circuit are linear drive circuit or switching circuit.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611030982.4A CN106793246B (en) | 2016-11-16 | 2016-11-16 | Leadage circuit and its control method and LED control circuit |
| US15/490,002 US10143051B2 (en) | 2016-11-16 | 2017-04-18 | Bleeder circuit and control method thereof, and LED control circuit |
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| CN201611030982.4A CN106793246B (en) | 2016-11-16 | 2016-11-16 | Leadage circuit and its control method and LED control circuit |
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| CN106793246B true CN106793246B (en) | 2019-04-02 |
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| CN107864532B (en) * | 2017-11-03 | 2023-09-26 | 杰华特微电子股份有限公司 | LED dimming circuit and method and LED control circuit |
| CN107995730B (en) | 2017-11-30 | 2020-01-07 | 昂宝电子（上海）有限公司 | System and method for phase-based control in connection with TRIAC dimmers |
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Address after: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province, 310030 Patentee after: Jiehuate Microelectronics Co.,Ltd. Address before: Room 424, building 1, 1500 Wenyi West Road, Cangqian street, Yuhang District, Hangzhou City, Zhejiang Province Patentee before: JOULWATT TECHNOLOGY (HANGZHOU) Co.,Ltd. |