CN106784313A - OTFT and preparation method thereof - Google Patents
OTFT and preparation method thereof Download PDFInfo
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- CN106784313A CN106784313A CN201611227663.2A CN201611227663A CN106784313A CN 106784313 A CN106784313 A CN 106784313A CN 201611227663 A CN201611227663 A CN 201611227663A CN 106784313 A CN106784313 A CN 106784313A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 239000004065 semiconductor Substances 0.000 claims abstract description 66
- 239000012212 insulator Substances 0.000 claims abstract description 56
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910003437 indium oxide Inorganic materials 0.000 claims abstract description 10
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910001887 tin oxide Inorganic materials 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 21
- 230000008569 process Effects 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 10
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- 239000002184 metal Substances 0.000 description 19
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 14
- 239000010409 thin film Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 13
- 239000002041 carbon nanotube Substances 0.000 description 12
- 238000000151 deposition Methods 0.000 description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 12
- 239000010931 gold Substances 0.000 description 12
- SKRWFPLZQAAQSU-UHFFFAOYSA-N stibanylidynetin;hydrate Chemical compound O.[Sn].[Sb] SKRWFPLZQAAQSU-UHFFFAOYSA-N 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 8
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 8
- 239000000956 alloy Substances 0.000 description 8
- TVFDJXOCXUVLDH-UHFFFAOYSA-N caesium atom Chemical compound [Cs] TVFDJXOCXUVLDH-UHFFFAOYSA-N 0.000 description 8
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- ZUOUZKKEUPVFJK-UHFFFAOYSA-N diphenyl Chemical compound C1=CC=CC=C1C1=CC=CC=C1 ZUOUZKKEUPVFJK-UHFFFAOYSA-N 0.000 description 8
- 239000003292 glue Substances 0.000 description 8
- 239000011733 molybdenum Substances 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 229910052717 sulfur Inorganic materials 0.000 description 8
- 239000011593 sulfur Substances 0.000 description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 8
- 239000010937 tungsten Substances 0.000 description 8
- 238000004528 spin coating Methods 0.000 description 7
- 229910000838 Al alloy Inorganic materials 0.000 description 6
- 229910001020 Au alloy Inorganic materials 0.000 description 6
- 229910001202 Cs alloy Inorganic materials 0.000 description 6
- 229910000881 Cu alloy Inorganic materials 0.000 description 6
- 229910001182 Mo alloy Inorganic materials 0.000 description 6
- 229910001252 Pd alloy Inorganic materials 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 6
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- 230000008021 deposition Effects 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 6
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 4
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- 239000002253 acid Substances 0.000 description 4
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- 239000004305 biphenyl Substances 0.000 description 4
- 239000000460 chlorine Substances 0.000 description 4
- 229910052801 chlorine Inorganic materials 0.000 description 4
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- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 4
- 125000005575 polycyclic aromatic hydrocarbon group Chemical group 0.000 description 4
- 238000000682 scanning probe acoustic microscopy Methods 0.000 description 4
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- 125000005259 triarylamine group Chemical group 0.000 description 4
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 150000001412 amines Chemical class 0.000 description 2
- 150000004982 aromatic amines Chemical class 0.000 description 2
- 230000008033 biological extinction Effects 0.000 description 2
- 229910052792 caesium Inorganic materials 0.000 description 2
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- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920000052 poly(p-xylylene) Polymers 0.000 description 2
- 229920000058 polyacrylate Polymers 0.000 description 2
- 229920002098 polyfluorene Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229920000123 polythiophene Polymers 0.000 description 2
- 235000013855 polyvinylpyrrolidone Nutrition 0.000 description 2
- 229920000036 polyvinylpyrrolidone Polymers 0.000 description 2
- 239000001267 polyvinylpyrrolidone Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- QQONPFPTGQHPMA-UHFFFAOYSA-N propylene Natural products CC=C QQONPFPTGQHPMA-UHFFFAOYSA-N 0.000 description 2
- 125000004805 propylene group Chemical group [H]C([H])([H])C([H])([*:1])C([H])([H])[*:2] 0.000 description 2
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- 238000001338 self-assembly Methods 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/464—Lateral top-gate IGFETs comprising only a single gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/80—Constructional details
- H10K10/82—Electrodes
- H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
Landscapes
- Thin Film Transistor (AREA)
Abstract
The invention provides OTFT and preparation method, OTFT includes substrate, source-drain electrode layer, organic semiconductor layer, gate insulator, gate electrode layer, organic planarization layer and indium and tin oxide film layer.Preparation method is simple, and photoresistance pattern is formed on substrate, then etches unprotected substrate portion, forms groove；Removing photoresistance layer is removed, the source-drain electrode pattern flushed with substrate is formed in a groove, form copline bottom contact structures；Organic semiconductor layer, gate insulator, gate electrode layer and organic planarization layer are sequentially formed in the contact structures of copline bottom；Via is formed in organic planarizationization layer, via extends to drain electrode surface；Indium and tin oxide film layer is formed on organic planarizationization layer.By source-drain electrode and the introducing of substrate coplanar structure design, the follow-up active layer thin film deposition inequality brought because source-drain electrode is raised in traditional overlapping configuration is solved the problems, such as, reduce the contact resistance of device and then improve its electric property.
Description
Technical field
The present invention relates to transistor arts, more particularly to a kind of OTFT and preparation method thereof.
Background technology
Since finding that organic polymer has conductive capability, the development of organic electronic material is more and more rapider.With organic
Organic electronics based on electronic material are also developed rapidly as an emerging subject, its electricity for mainly studying organic material
Learn the preparation of performance and organic electronic device.20 end of the centurys, organic electronics organic semiconductor field associated materials with
Research on device achieves progress with rapid changepl. never-ending changes and improvements.At the same time, many organic film electronic devices with practical significance
Also occur in succession, such as organic solar film battery, Organic Light Emitting Diode and OTFT, as thin film electronic device
Newcomer in part family.
Although OTFT due to the limitation of its switching speed and mobility, can not replace traditional inorganic
Field-effect transistor, but because it has the good characteristic not available for inorganic transistors so that permitted in OTFT
It is multi-field to be all widely used.OTFT electronic logic element the most basic, in FPD and plastics IC
The critical role of technical elements is self-evident.
OTFT is the FET device with organic semiconducting materials as active layer, typically by grid
Pole, organic active layer, insulating barrier, source-drain electrode are constituted.Its structure can be divided into bottom grating structure and item for the position of gate electrode
The class of grid structure two.It is different from the position of active layer according to source, drain electrode, top contact structure and the class of bottom contact structures two are divided into again.
OTFT has low cost, is easy to bending and preferably advantage compatible with Flexible Displays, is increasingly becoming future
The focus of Flexible Displays research.Its shortcoming is to be influenceed larger by process conditions, i.e. film-forming process condition and substrate surface shape
Looks have considerable influence to the mobility of device.
The content of the invention
For above-mentioned the problems of the prior art, the application provides a kind of OTFT, including：
Substrate, sets fluted on the substrate；
Source-drain electrode layer on the substrate, the source-drain electrode layer is located in the groove and the source-drain electrode
The surface of layer flushes setting with the substrate surface；
Organic semiconductor layer on source-drain electrode layer；
Gate insulator on the organic semiconductor layer；
Gate electrode layer on the gate insulator；
Organic planarization layer on the gate electrode layer, via, the via are formed in organic planarizationization layer
Extend to drain electrode surface；
Indium and tin oxide film layer, the indium and tin oxide film is connected by the via with drain electrode.
Further, the organic semiconductor layer is coated in the gate insulator；The gate electrode layer is coated on institute
In stating organic planarization layer.
Further, the gate electrode layer, gate insulator and organic semiconductor layer are coated in the organic planarization layer.
Further, the organic semiconductor layer two ends overlap on the source and drain electrodes respectively, described organic partly to lead
The thickness of body layer is 40nm~100nm plates.
Further, the thickness of the gate insulator is 50nm~900nm.
Further, the thickness of the gate electrode layer is 100nm~500nm.
Further, the thickness of the organic planarization layer is 1 μm~2 μm.
The present invention also provides the preparation method of above-mentioned OTFT, including：
Step 101：Photoresistance pattern is formed on substrate, unprotected substrate portion is then etched, groove is formed；
Step 102：Removing photoresistance layer is removed, the source-drain electrode pattern flushed with substrate is formed in a groove, form copline bottom
Contact structures；
Step 103：Organic semiconductor layer is formed in the contact structures of the copline bottom；
Step 104：Gate insulator is formed on the organic semiconductor layer；
Step 105：Gate electrode layer is formed on the gate insulator；
Step 106：Organic planarization layer is formed on the gate electrode layer；
Step 107：Via is formed in organic planarizationization layer, the via extends to drain electrode surface；
Step 108：Indium and tin oxide film layer, the indium and tin oxide film layer are formed on organic planarizationization layer
Lower surface edge at protrude out a lug boss downwards, the lug boss is just contained in the via and the drain electrode phase
Even.
Further, before forming gate insulator on the organic semiconductor layer, the organic semiconductor layer is entered
Row patterned process；Before forming organic planarization layer on the gate electrode layer, patterned process is carried out to the gate electrode layer.
Further, before forming organic planarization layer on the gate electrode layer, to the gate electrode layer, gate insulator
Patterned process is carried out with organic semiconductor layer.
Beneficial effects of the present invention：
The present invention devises a kind of source-drain electrode and the coplanar bottom contact structures of substrate, and source-drain electrode is put down altogether with substrate
The introducing of face structure design, because of the raised follow-up active layer thin film deposition for being brought of source-drain electrode in the traditional overlapping configuration of solution
Uneven problem, reduces the contact resistance of device and then improves its electric property.
Structure by improving thin film transistor (TFT) of the invention, solves the problems, such as source-drain electrode edge protuberance, and then reduce follow-up
The problem of the thin film deposition inequality that active layer film is brought by ladder.
Other features and advantages of the present invention will illustrate in the following description, and partly become from specification
It is clear that or being understood by implementing the present invention.The purpose of the present invention and other advantages can be wanted by specification, right
Specifically noted structure in book and accompanying drawing is asked to realize and obtain.
Brief description of the drawings
The invention will be described in more detail below based on embodiments and refering to the accompanying drawings.Wherein：
Fig. 1 is the flow chart of OTFT preparation method of the present invention；
Fig. 2 be first embodiment of the invention in on substrate formed groove schematic diagram；
The schematic diagram of the copline bottom contact structures that Fig. 3 is flushed for source-drain electrode in first embodiment of the invention with substrate；
Fig. 4 is that the schematic diagram of surface self-organization is carried out to source-drain electrode in first embodiment of the invention；
Fig. 5 be first embodiment of the invention in the contact structures of copline bottom formed organic semiconductor layer structural representation
Figure；
Fig. 6 be first embodiment of the invention on organic semiconductor layer formed gate insulator structural representation；
Fig. 7 is the structural representation in first embodiment of the invention in upper gate insulator formation gate electrode layer；
Fig. 8 is organic planarization layer to be formed on gate electrode layer in first embodiment of the invention and form the structural representation of via
Figure；
Fig. 9 be first embodiment of the invention in organic planarizationization layer on formed ito thin film layer structural representation；
Figure 10 be second embodiment of the invention in on substrate formed groove schematic diagram；
The schematic diagram of the copline bottom contact structures that Figure 11 is flushed for source-drain electrode in second embodiment of the invention with substrate；
Figure 12 is that the schematic diagram of surface self-organization is carried out to source-drain electrode in second embodiment of the invention；
Figure 13 be second embodiment of the invention in the contact structures of copline bottom formed organic semiconductor layer, gate insulator
The structural representation of layer, metal gate electrode layer and photoresist layer；
Figure 14 is the structural representation for being ashed organic semiconductor layer and gate insulator in second embodiment of the invention；
Figure 15 shows to form organic planarization layer in second embodiment of the invention on gate electrode layer and forming the structure of via
It is intended to；
Figure 16 be second embodiment of the invention in organic planarizationization layer on formed ito thin film layer structural representation.
In the accompanying drawings, identical part uses identical reference.Accompanying drawing is not according to actual ratio.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
It is as shown in Figure 1 the flow chart of OTFT preparation method of the present invention, comes to the present invention below with reference to Fig. 1
The preparation method of described OTFT is described in detail.
First embodiment
The present embodiment is illustrated below in conjunction with Fig. 2~Fig. 9.
In a step 101, photoresistance pattern is formed on substrate, unprotected substrate portion is then etched, groove is formed；
Specifically, using the positive photoresist with extinction characteristic, light is formed on substrate 1 by the photoetching process of standard
Resistance pattern 2, then etches unprotected substrate portion, forms 2 grooves 11 of certain depth；
As shown in Fig. 2 Fig. 2 is for, for the schematic diagram of the formation groove on substrate, 1 is substrate, and 2 are in the embodiment of the present invention
Photoresistance pattern, 11 is groove.
The lithographic method can use dry etching (dry etch) or wet etching (wet-etch).
The substrate is transparent glass substrate or pet substrate.
Next in a step 102, removing photoresistance layer is removed, the source-drain electrode pattern flushed with substrate, shape is formed in a groove
Into copline bottom contact structures；
Specifically, substrate 1 is immersed in glue, removing photoresistance layer 2 is removed.Using the modes such as inkjet printing shape in a groove
Into the source-drain electrode pattern flushed with substrate 1, copline bottom contact structures are formed.
Conductive ink dosage is instilled specifically by control so that source-drain electrode is concordant with base plan.
The conductive ink can be gold or silver-colored conductive ink.
As shown in figure 3, Fig. 3 is that the copline bottom contact structures that are flushed with substrate of source-drain electrode are shown in the embodiment of the present invention
It is intended to, 1 is substrate, and 31 is source electrode, and 32 is drain electrode.
This source-drain electrode and the coplanar structure of substrate, solve in traditional overlapping configuration because of source-drain electrode projection institute
The problem of the follow-up active layer thin film deposition inequality brought, reduces the contact resistance of device and then improves its electric property.
Specifically, the material of the source electrode can for metal, alloy, indium tin oxide (ITO), antimony tin oxide (ATO),
In conductive silver glue, conducting polymer, metallic carbon nanotubes layer and carbon nano tube metal composite bed or its any combination one
Kind；The material of the drain electrode can for metal, alloy, indium tin oxide (ITO), antimony tin oxide (ATO), conductive silver glue, lead
One kind in electric polymer, metallic carbon nanotubes layer and carbon nano tube metal composite bed or its any combination.The metal
Or alloy material can be the alloy of aluminium, copper, tungsten, molybdenum, gold, caesium, palladium or its any combination.
Specifically, the material of the source electrode can be the alloy of aluminium, copper, tungsten, molybdenum, gold, caesium, palladium or its any combination；Institute
The material for stating drain electrode can be the alloy of aluminium, copper, tungsten, molybdenum, gold, caesium, palladium or its any combination.
After forming copline bottom contact structures, in following step 103, the shape in the contact structures of the copline bottom
Into organic semiconductor layer；
Specifically, before organic semiconductor layer is formed, it is necessary on the contact structures substrate of copline bottom, to source-drain electrode
Surface self-organization treatment is carried out, self-assembled monolayer (self-assembly monolayers, SAMs) is formed, and then improve
The work function of source and drain metal electrode, is to improve device performance.
As shown in figure 4, Fig. 4 is that the schematic diagram of surface self-organization is carried out to source-drain electrode in the embodiment of the present invention, 1 is base
Plate, 31 is source electrode, and 32 is drain electrode, and 33 is SAMs.
The size of work function represents that electronics effusion semiconductor needs the minimum value of energy, also reflects to electronics constraint ability
It is strong and weak；It passes through to influence opto-electronic device carrier to inject, so as to influence the performance of device.
The thickness of the organic semiconductor layer of formation is 40nm~100nm, and the thickness of organic semiconductor layer is excellent in the present embodiment
Elect 80nm as.
Then it is patterned；Source electrode and drain electrode are not completely covered for the organic semiconductor layer.
As shown in figure 5, Fig. 5 be the embodiment of the present invention in the contact structures of copline bottom formed organic semiconductor layer knot
Structure schematic diagram, 1 is substrate, and 31 is source electrode, and 32 is drain electrode, and 4 is organic semiconductor layer.
Organic semiconductor layer is formed particular by modes such as evaporation, spin coating or printings.
Can also be doped with organic molecule in the organic semiconductor layer.
The doping of the organic molecule is the 0.0001%~1% of organic semiconductor layer gross mass.
Described organic semiconducting materials are the functional material with high carrier mobility：Polycyclic aromatic hydrocarbon, sulfur family are miscellaneous
Condensed ring, sulfur family heterocycle oligomer, tetrathiafulvalene, nitrogen-containing hetero condensed ring, triaryl amine, nitrogenous Conjugate macrocycle molecule, biphenyl, fragrance
One kind or many in amine, fluorochemical, condensed ring acid anhydrides, condensed ring acid imide, C60, C70, polythiophene, polyfluorene and its derivative
Kind.Described organic molecule is thick polycyclic aromatic hydrocarbon, the miscellaneous condensed ring of sulfur family, sulfur family heterocycle oligomer, tetrathiafulvalene, nitrogen-containing hetero
Ring, triaryl amine, nitrogenous Conjugate macrocycle molecule, biphenyl, aromatic amine, fluorochemical, condensed ring acid anhydrides, condensed ring acid imide, C60, C70
And its one or more in derivative.
By choosing suitable dopant, the stability of OTFT can be effectively improved, improve device and use
Life-span；It is the organic semiconductor layer of 40nm~100nm that the present invention forms thickness by wet processings such as evaporation or inkjet printings, just
In the making of large area, cost of manufacture is reduced.
At step 104, gate insulator is formed on the organic semiconductor layer；
As shown in fig. 6, Fig. 6 be the embodiment of the present invention on organic semiconductor layer formed gate insulator structural representation
Figure, 1 is substrate, and 31 is source electrode, and 32 is drain electrode, and 4 is organic semiconductor layer, and 5 is gate insulator.
The thickness of the gate insulator is 50~900nm.
The thickness of gate insulator is preferably 300nm in the present embodiment.
Specifically, depositing gate insulator by modes such as spin coating or printings.
The gate insulator is inorganic insulation layer or organic insulator, and inorganic insulation layer is silica, silicon nitride
It is polyvinylpyrrolidone, polyimides, propylene etc. Deng, organic insulator.
Specifically, corona treatment can also be carried out to gate insulator layer surface, to repair the gate insulator layer surface
Defect.
The plasma is chlorine based plasma, when carrying out corona treatment with chlorine based plasma, gas in cavity
It is 2.0~100mT to press, and firing frequency is 10~30000W；Low radio frequency is 10~20000W；Cooling air pressure is 10~10000mT；Gas
Body volume flow is 10~5000sccm；Process time is 1~150s.
The plasma can also be fluorine-based, epoxide, nitrogen base, phosphorus base or carbon-based plasma.
Specifically, when corona treatment is carried out with fluorine-based plasma, air pressure is 2.0~100mT in cavity, is shot high
Frequency is 10~30000W；Low radio frequency is 10~20000W；Cooling air pressure is 10~10000mT；Volumetric flow of gas be 10~
5000sccm；Process time is 1~150s
In step 105, gate electrode layer is formed on the gate insulator；
Specifically, by PVD deposition metal gate electrode layer, the thickness of gate electrode layer is 100~500nm, in the present embodiment
The thickness of gate electrode layer is preferably 200nm, and the photoetching process formation gate electrode pattern for passing through standard；
As shown in fig. 7, Fig. 7 is the structural representation in the embodiment of the present invention in upper gate insulator formation gate electrode layer, 1
It is substrate, 31 is source electrode, and 32 is drain electrode, and 4 is organic semiconductor layer, and 5 is gate insulator, and 6 is gate electrode layer.
Specifically, PVD deposition method can be vacuum evaporation, sputter coating, ion film plating etc., PVD deposition is not changing
In the case of body material, case hardness, wearability, heat resistance, corrosion resistance, self lubricity etc. are effectively improved.Service life
3~5 times are improved than preceding.
Specifically, the material of the gate electrode layer can be metal, alloy, indium tin oxide (ITO), antimony tin oxide
(ATO), conductive silver glue, conducting polymer, metallic carbon nanotubes layer and carbon nano tube metal composite bed or its any combination
In one kind；
Specifically, the material of the gate electrode layer can be the conjunction of aluminium, copper, tungsten, molybdenum, gold, caesium, palladium or its any combination
Gold.
Next, in step 106, organic planarization layer is formed on the gate electrode layer；
Specifically, depositing 1~2 μm of organic planarization layer (Planarization by modes such as spin coating or printings
Layer)。
In step 107, via is formed in organic planarizationization layer, the via extends to drain electrode surface；
Specifically, forming contact hole patterns in organic planarizationization layer, then etched by O2plasma organic
Insulating barrier is at metal leakage pole；
The material of organic planarization layer is fluorinated polymer, Parylene, methyl cyclopentenyl ketone, polyacrylate etc..
As shown in figure 8, Fig. 8 is organic planarization layer to be formed on gate electrode layer in the embodiment of the present invention and form the knot of via
Structure schematic diagram, 1 is substrate, and 31 is source electrode, and 32 is drain electrode, and 4 is organic semiconductor layer, and 5 is gate insulator, and 6 is grid electricity
Pole layer, 7 is organic planarization layer, and 71 is via.
In step 108, ito thin film layer, the lower surface side of the ito thin film layer are formed on organic planarizationization layer
A lug boss is protruded out downwards at edge, the lug boss is connected in being just contained in the via with the drain electrode.
Specifically, by the ito thin film within PVD deposition 100nm, and the photoetching process formation show electrode for passing through standard
Pattern；So far the preparation of OTFT is completed.
As shown in figure 9, Fig. 9 be the embodiment of the present invention in organic planarizationization layer on formed ito thin film layer structural representation
Figure, 1 is substrate, and 31 is source electrode, and 32 is drain electrode, and 4 is organic semiconductor layer, and 5 is gate insulator, and 6 is gate electrode layer, 7
It is organic planarization layer, 8 is ito thin film.
The present invention improves the electric property of device by improving the uniformity of active layer thin film deposition.
Second embodiment
The present embodiment is illustrated below in conjunction with Figure 10~Figure 16.
In a step 101, photoresistance pattern is formed on substrate, unprotected substrate portion is then etched, groove is formed；
Specifically, using the positive photoresist with extinction characteristic, light is formed on substrate 1 by the photoetching process of standard
Resistance pattern 2, then etches unprotected substrate portion, forms 2 grooves 11 of certain depth；
As shown in Figure 10, Figure 10 is for, for the schematic diagram of the formation groove on substrate, 1 is substrate, 2 in the embodiment of the present invention
It is photoresistance pattern, 11 is groove.
The lithographic method can use dry etching (dry etch) or wet etching (wet-etch).
The substrate is transparent glass substrate or pet substrate.
Next in a step 102, removing photoresistance layer is removed, the source-drain electrode pattern flushed with substrate, shape is formed in a groove
Into copline bottom contact structures；
Specifically, substrate 1 is immersed in glue, removing photoresistance layer 2 is removed.Using the modes such as inkjet printing shape in a groove
Into the source-drain electrode pattern flushed with substrate 1, copline bottom contact structures are formed.
Conductive ink dosage is instilled specifically by control so that source-drain electrode is concordant with base plan.
The conductive ink can be gold or silver-colored conductive ink.
As shown in figure 11, the copline bottom contact structures that Figure 11 is flushed for source-drain electrode in the embodiment of the present invention with substrate
Schematic diagram, 1 is substrate, and 31 is source electrode, and 32 is drain electrode.
This source-drain electrode and the coplanar structure of substrate, solve in traditional overlapping configuration because of source-drain electrode projection institute
The problem of the follow-up active layer thin film deposition inequality brought, reduces the contact resistance of device and then improves its electric property.
Specifically, the material of the source electrode can for metal, alloy, indium tin oxide (ITO), antimony tin oxide (ATO),
In conductive silver glue, conducting polymer, metallic carbon nanotubes layer and carbon nano tube metal composite bed or its any combination one
Kind；The material of the drain electrode can for metal, alloy, indium tin oxide (ITO), antimony tin oxide (ATO), conductive silver glue, lead
One kind in electric polymer, metallic carbon nanotubes layer and carbon nano tube metal composite bed or its any combination.The metal
Or alloy material can be the alloy of aluminium, copper, tungsten, molybdenum, gold, caesium, palladium or its any combination.
Specifically, the material of the source electrode can be the alloy of aluminium, copper, tungsten, molybdenum, gold, caesium, palladium or its any combination；Institute
The material for stating drain electrode can be the alloy of aluminium, copper, tungsten, molybdenum, gold, caesium, palladium or its any combination.
After forming copline bottom contact structures, in a subsequent step, it is necessary on the contact structures substrate of copline bottom,
Carry out surface self-organization treatment to source-drain electrode, formed self-assembled monolayer (self-assembly monolayers,
SAMs), so improve source and drain metal electrode work function, be to improve device performance.
The size of work function represents that electronics effusion semiconductor needs the minimum value of energy, also reflects to electronics constraint ability
It is strong and weak；It passes through to influence opto-electronic device carrier to inject, so as to influence the performance of device.
As shown in figure 12, Figure 12 is that the schematic diagram of surface self-organization is carried out to source-drain electrode in the embodiment of the present invention, and 1 is base
Plate, 31 is source electrode, and 32 is drain electrode, and 33 is SAMs.
In following step 103, organic semiconductor layer is formed in the contact structures of the copline bottom；
The thickness of the organic semiconductor layer of formation is 40nm~100nm, and the thickness of organic semiconductor layer is excellent in the present embodiment
Elect 80nm as.
Specifically, being to form organic semiconductor layer by modes such as evaporation, spin coating or printings.
Can also be doped with organic molecule in the organic semiconductor layer.
The doping of the organic molecule is the 0.0001%~1% of organic semiconductor layer gross mass.
Described organic semiconducting materials are the functional material with high carrier mobility：Polycyclic aromatic hydrocarbon, sulfur family are miscellaneous
Condensed ring, sulfur family heterocycle oligomer, tetrathiafulvalene, nitrogen-containing hetero condensed ring, triaryl amine, nitrogenous Conjugate macrocycle molecule, biphenyl, fragrance
One kind or many in amine, fluorochemical, condensed ring acid anhydrides, condensed ring acid imide, C60, C70, polythiophene, polyfluorene and its derivative
Kind.Described organic molecule is thick polycyclic aromatic hydrocarbon, the miscellaneous condensed ring of sulfur family, sulfur family heterocycle oligomer, tetrathiafulvalene, nitrogen-containing hetero
Ring, triaryl amine, nitrogenous Conjugate macrocycle molecule, biphenyl, aromatic amine, fluorochemical, condensed ring acid anhydrides, condensed ring acid imide, C60, C70
And its one or more in derivative.
By choosing suitable dopant, the stability of OTFT can be effectively improved, improve device and use
Life-span；It is the organic semiconductor layer of 40nm~100nm that the present invention forms thickness by wet processings such as evaporation or inkjet printings, just
In the making of large area, cost of manufacture is reduced.
At step 104, gate insulator is formed on the organic semiconductor layer；
The thickness of the gate insulator is 50~900nm.
The thickness of gate insulator is preferably 300nm in the present embodiment.
Specifically, depositing gate insulator by modes such as spin coating or printings.
The gate insulator is inorganic insulation layer or organic insulator, and inorganic insulation layer is silica, silicon nitride
It is polyvinylpyrrolidone, polyimides, propylene etc. Deng, organic insulator.
Specifically, corona treatment can also be carried out to gate insulator layer surface, to repair the gate insulator layer surface
Defect.
The plasma is chlorine based plasma, when carrying out corona treatment with chlorine based plasma, gas in cavity
It is 2.0~100mT to press, and firing frequency is 10~30000W；Low radio frequency is 10~20000W；Cooling air pressure is 10~10000mT；Gas
Body volume flow is 10~5000sccm；Process time is 1~150s.
The plasma can also be fluorine-based, epoxide, nitrogen base, phosphorus base or carbon-based plasma.
Specifically, when corona treatment is carried out with fluorine-based plasma, air pressure is 2.0~100mT in cavity, is shot high
Frequency is 10~30000W；Low radio frequency is 10~20000W；Cooling air pressure is 10~10000mT；Volumetric flow of gas be 10~
5000sccm；Process time is 1~150s.
In step 105, gate electrode layer is formed on the gate insulator；
Specifically, by PVD deposition metal gate electrode layer, the thickness of gate electrode layer is 100~500nm, in the present embodiment
The thickness of gate electrode layer is preferably 200nm.
Then spin coating or print photoresistance and form pattern on gate electrode layer, then using dry etching or wet etching etching not by
The metal gate electrode of photoresistance protection, then removes its photoresistance and ultimately forms metal gate electrode；
As shown in figure 13, Figure 13 be the embodiment of the present invention in the contact structures of copline bottom formed organic semiconductor layer,
The structural representation of gate insulator, metal gate electrode layer and photoresist layer, 1 is substrate, and 31 is source electrode, and 32 is drain electrode, and 4 are
Organic semiconductor layer, 5 is gate insulator, and 6 is metal gate electrode layer, and 61 is photoresist layer.
Next, the gate insulator and organic semiconductor layer do not protected by metal gate electrode are ashed by O2plasma,
It is finally completed organic semi-conductor patterning；
As shown in figure 14, Figure 14 is to show the structure that organic semiconductor layer and gate insulator are ashed in the embodiment of the present invention
It is intended to, 1 is substrate, and 31 is source electrode, and 32 is drain electrode, and 4 is organic semiconductor layer, and 5 is gate insulator, and 6 is metal gate electricity
Pole layer.
Specifically, PVD deposition method can be vacuum evaporation, sputter coating, ion film plating etc., PVD deposition is not changing
In the case of body material, case hardness, wearability, heat resistance, corrosion resistance, self lubricity etc. are effectively improved.Service life
3~5 times are improved than preceding.
Specifically, the material of the gate electrode layer can be metal, alloy, indium tin oxide (ITO), antimony tin oxide
(ATO), conductive silver glue, conducting polymer, metallic carbon nanotubes layer and carbon nano tube metal composite bed or its any combination
In one kind；
Specifically, the material of the gate electrode layer can be the conjunction of aluminium, copper, tungsten, molybdenum, gold, caesium, palladium or its any combination
Gold.
In step 106, organic planarization layer is formed on the gate electrode layer；
Specifically, depositing 1~2 μm of organic planarization layer (Planarization by modes such as spin coating or printings
Layer)。
In step 107, via is formed in organic planarizationization layer, the via extends to drain electrode surface；
Specifically, forming contact hole patterns in organic planarizationization layer, then etched by O2plasma organic
Insulating barrier is at metal leakage pole；
The material of organic planarization layer is fluorinated polymer, Parylene, methyl cyclopentenyl ketone, polyacrylate etc..
As shown in figure 15, Figure 15 is to be formed in the embodiment of the present invention organic planarization layer and to form via on gate electrode layer
Structural representation, 1 is substrate, and 31 is source electrode, and 32 is drain electrode, and 4 is organic semiconductor layer, and 5 is gate insulator, and 6 is grid
Electrode layer, 7 is organic planarization layer, and 71 is via.
In step 108, ito thin film layer, the lower surface side of the ito thin film layer are formed on organic planarizationization layer
A lug boss is protruded out downwards at edge, the lug boss is connected in being just contained in the via with the drain electrode.
Specifically, by the ito thin film within PVD deposition 100nm, and the photoetching process formation show electrode for passing through standard
Pattern；So far the preparation of OTFT is completed.
As shown in figure 16, Figure 16 shows to form the structure of ito thin film layer in the embodiment of the present invention on organic planarizationization layer
It is intended to, 1 is substrate, and 31 is source electrode, and 32 is drain electrode, and 4 is organic semiconductor layer, and 5 is gate insulator, and 6 is gate electrode layer,
7 is organic planarization layer, and 8 is ito thin film.
The present invention improves the electric property of device by improving the uniformity of active layer thin film deposition.
Although describing the present invention herein with reference to specific implementation method, it should be understood that, these realities
Apply the example of example only principles and applications.It should therefore be understood that can be carried out to exemplary embodiment
Many modifications, and other arrangements are can be designed that, without departing from the spirit of the invention that appended claims are limited
And scope.It should be understood that can be by way of different from described by original claim come with reference to different appurtenances
Profit is required and feature specifically described herein.It will also be appreciated that the feature with reference to described by separate embodiments can be used
In other described embodiments.
Claims (10)
1. OTFT, it is characterised in that it includes：
Substrate, sets fluted on the substrate；
Source-drain electrode layer on the substrate, source-drain electrode layer is located in the groove and source-drain electrode layer
Surface flushes setting with the substrate surface；
Organic semiconductor layer on source-drain electrode layer；
Gate insulator on the organic semiconductor layer；
Gate electrode layer on the gate insulator；
Organic planarization layer on the gate electrode layer, forms via in organic planarizationization layer, and the via extends
To drain electrode surface；
Indium and tin oxide film layer, the indium and tin oxide film layer is connected by the via with drain electrode.
2. OTFT as claimed in claim 1, it is characterised in that the organic semiconductor layer is coated on the grid
In the insulating barrier of pole；The gate electrode layer is coated in the organic planarization layer.
3. OTFT as claimed in claim 1, it is characterised in that the gate electrode layer, gate insulator and have
Machine semiconductor layer is coated in the organic planarization layer.
4. the OTFT as described in claim 1,2 or 3, it is characterised in that the organic semiconductor layer two ends point
Do not overlap on the source and drain electrodes, the thickness of the organic semiconductor layer is 40nm~100nm.
5. OTFT as claimed in claim 4, it is characterised in that the thickness of the gate insulator be 50nm~
900nm。
6. the OTFT as described in claim 1,2 or 3, it is characterised in that the thickness of the gate electrode layer is
100nm~500nm.
7. OTFT as claimed in claim 6, it is characterised in that the thickness of the organic planarization layer is 1 μm~2
μm。
8. the preparation method of OTFT as claimed in claim 1, it is characterised in that the method includes：
Step 101：Photoresistance pattern is formed on substrate, unprotected substrate portion is then etched, groove is formed；
Step 102：Removing photoresistance layer is removed, the source-drain electrode pattern flushed with substrate is formed in a groove, form the contact of copline bottom
Structure；
Step 103：Organic semiconductor layer is formed in the contact structures of the copline bottom；
Step 104：Gate insulator is formed on the organic semiconductor layer；
Step 105：Gate electrode layer is formed on the gate insulator；
Step 106：Organic planarization layer is formed on the gate electrode layer；
Step 107：Via is formed in organic planarizationization layer, the via extends to drain electrode surface；
Step 108：Indium and tin oxide film layer is formed on organic planarizationization layer, under the indium and tin oxide film layer
A lug boss is protruded out downwards at marginal surface, the lug boss is connected in being just contained in the via with the drain electrode.
9. the preparation method of OTFT as claimed in claim 8, it is characterised in that in the organic semiconductor layer
Before upper formation gate insulator, patterned process is carried out to the organic semiconductor layer；It is formed with the gate electrode layer
Before machine flatness layer, patterned process is carried out to the gate electrode layer.
10. the preparation method of OTFT as claimed in claim 8, it is characterised in that on the gate electrode layer
Before forming organic planarization layer, patterned process is carried out to the gate electrode layer, gate insulator and organic semiconductor layer.
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