CN106784015A - A kind of thin film transistor (TFT) and preparation method thereof, display base plate and display device - Google Patents
A kind of thin film transistor (TFT) and preparation method thereof, display base plate and display device Download PDFInfo
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- CN106784015A CN106784015A CN201710001470.3A CN201710001470A CN106784015A CN 106784015 A CN106784015 A CN 106784015A CN 201710001470 A CN201710001470 A CN 201710001470A CN 106784015 A CN106784015 A CN 106784015A
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- 229920002120 photoresistant polymer Polymers 0.000 claims description 80
- 239000010408 film Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 17
- 230000000717 retained effect Effects 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 claims description 2
- 239000003292 glue Substances 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 50
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000010276 construction Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
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- 229910052782 aluminium Inorganic materials 0.000 description 2
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- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
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- 239000000463 material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
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- 229910004205 SiNX Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
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- 229910001092 metal group alloy Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- Thin Film Transistor (AREA)
Abstract
The present invention relates to display technology field, a kind of thin film transistor (TFT) and preparation method thereof, display base plate and display device are disclosed.The thin film transistor (TFT) includes the conductive pattern set with the channel region contacts of active layer, the conductive pattern and source electrode, drain electrode insulation set.When thin film transistor (TFT) is turned on, channel region between source electrode and conductive pattern, and positioned at the channel region formation conducting channel of drain electrode and conductive pattern, conducting channel is formed rather than whole channel region, make the breadth length ratio of channel region less than the breadth length ratio of conducting channel, less channel region breadth length ratio is obtained in that small off-state current Ioff, the breadth length ratio of larger conducting channel is obtained in that big operating current Ion, the purpose for optimizing Ion and Ioff simultaneously has been reached, the performance of thin film transistor (TFT) has been improved.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of thin film transistor (TFT) and preparation method thereof, display base plate
And display device.
Background technology
In technical field of flat panel display, thin film transistor (TFT) (Thin Film Transistor, abbreviation TFT) has volume
It is small, low in energy consumption, the advantages of manufacturing cost is relatively low, be widely used in flat panel display as driving element.
Thin film transistor (TFT) includes gate electrode, active layer, source electrode and drain electrode, wherein, active layer includes being connect with source electrode
The drain region that tactile source region is contacted with drain electrode, and the channel region between source region and drain region, only lead in thin film transistor (TFT)
When logical, the channel region could form conducting channel.In traditional design, when thin film transistor (TFT) is turned on, positioned at source electrode and leakage
Whole described channel region between electrode forms conducting channel, i.e. thin film transistor (TFT) and is turning on and ending under two states, raceway groove
The effective length of area and conducting channel is the development length near source electrode side near drain electrode side, is the same
, it is impossible to while optimizing Ion and Ioff.Because in order to optimize the characteristic of thin film transistor (TFT), it is necessary to big Ion and small Ioff,
Conducting channel has cut-off state lower channel area tool the need for big breadth length ratio, small Ioff under big Ion needs conducting state
There is small channel width-over-length ratio, be between the two contradictory relation.
The content of the invention
The present invention provides a kind of thin film transistor (TFT) and preparation method thereof, display base plate and display device, be used to solve how
Optimize the problem of thin film transistor (TFT) Ion and Ioff simultaneously.
In order to solve the above technical problems, providing a kind of thin film transistor (TFT) in the embodiment of the present invention, including it is arranged on a substrate
On active layer, source electrode and drain electrode, the active layer includes that the source region contacted with the source electrode and the drain electrode connect
Tactile drain region, and the channel region between the source region and drain region, the thin film transistor (TFT) also include and the channel region
Surface contact conductive pattern, the conductive pattern and source electrode, drain electrode insulation set.
A kind of preparation method of thin film transistor (TFT) as described above is also provided in the embodiment of the present invention, including：
Active layer, source electrode and drain electrode are formed in a substrate, the active layer includes what is contacted with the source electrode
The drain region that source region is contacted with the drain electrode, and the channel region between the source region and drain region, it is characterised in that institute
Stating preparation method also includes：
The conductive pattern that formation is contacted with the surface of the channel region, the conductive pattern insulate with source electrode, drain electrode
Set.
A kind of display base plate, including thin film transistor (TFT) as described above are also provided in the embodiment of the present invention.
A kind of display device, including display base plate as described above are also provided in the embodiment of the present invention.
Above-mentioned technical proposal of the invention has the beneficial effect that：
In above-mentioned technical proposal, by setting the conductive pattern set with the channel region contacts of active layer, work as film crystal
When pipe is turned on, the channel region between source electrode and conductive pattern, and positioned at drain electrode and the channel region shape of conductive pattern
Into conducting channel, conducting channel is formed rather than whole channel region, makes the breadth length ratio of channel region less than the breadth length ratio of conducting channel,
Less channel region breadth length ratio is obtained in that small off-state current Ioff, and the breadth length ratio of larger conducting channel is obtained in that big
Operating current Ion, has reached the purpose for optimizing Ion and Ioff simultaneously, improves the performance of thin film transistor (TFT).
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, without having to pay creative labor, may be used also
Other accompanying drawings are obtained with according to these accompanying drawings.
Fig. 1 represents the structural representation one of thin film transistor (TFT) in the embodiment of the present invention；
Fig. 2 represents the partial structural diagram of active layer and conductive pattern in Fig. 1；
Fig. 3 represents the structural representation two of thin film transistor (TFT) in the embodiment of the present invention；
Fig. 4-Fig. 7 represents the manufacturing process schematic diagram of thin film transistor (TFT) in Fig. 1.
Specific embodiment
The active layer of thin film transistor (TFT) includes the drain region that the source region contacted with source electrode is contacted with drain electrode, and is located at
Channel region between source region and drain region, only when thin film transistor (TFT) is turned on, the channel region just forms conducting channel.Raceway groove
Breadth length ratio has important influence to tft characteristicses, and in the on-state, big conducting channel breadth length ratio can
Larger operating current Ion is obtained, in the off state, small channel region breadth length ratio is obtained in that less off-state current
Ioff。
In order to optimize the Ion and Ioff of thin film transistor (TFT) simultaneously, the present invention provides a kind of thin film transistor (TFT), its also include with
The conductive pattern of the surface contact of channel region, the conductive pattern and source electrode, drain electrode insulation set.Led by described in setting
Electrograph shape, makes the active layer also include the firstth area contacted with the conductive pattern, and firstth area is located at source region and drain region
Between.Then thin film transistor (TFT) in the on-state, the channel region between source region and the firstth area, and positioned at drain region and first
Channel region between area forms conducting channel, and whole channel region forms conducting channel, technology of the invention in relatively conventional design
Scheme reduces the length of conducting channel in the on-state, increased the breadth length ratio of conducting channel, is conducive to obtaining larger
Operating current Ion.At the same time it can also the appropriate length for increasing channel region, reduce the breadth length ratio of channel region to obtain less pass
State electric current Ioff, has reached the purpose for optimizing Ion and Ioff simultaneously, improves the performance of thin film transistor (TFT).
It should be noted that the length of channel region refer to channel region near the side of source electrode near the one of drain electrode
The development length of side, definition is first direction to the direction near the side of drain electrode near the side of source electrode from channel region,
Then the width of channel region refers to channel region bearing of trend in a second direction, wherein, the second direction is perpendicular to described
One direction.The length of conducting channel refers to conducting channel development length in a first direction, and the width of conducting channel is to instruct
Electric raceway groove development length in a second direction.
Below in conjunction with drawings and Examples, specific embodiment of the invention is described in further detail.Following reality
Example is applied for illustrating the present invention, but is not limited to the scope of the present invention.
Embodiment one
As shown in figure 1, providing a kind of thin film transistor (TFT) in the present embodiment, including it is arranged on the active layer in a substrate 100
1st, source electrode 2, drain electrode 3 and gate electrode 4.Active layer 1 includes the leakage that the source region contacted with source electrode 2 is contacted with drain electrode 3
Area, and the channel region between the source region and drain region.
The thin film transistor (TFT) also includes the conductive pattern 5 contacted with the surface of the channel region, conductive pattern 5 and source electricity
Pole 2, the insulation set of drain electrode 3.The channel region also includes the firstth area contacted with conductive pattern 5, and firstth area is located at source
Between area and drain region.
The active layer of above-mentioned thin film transistor (TFT) includes source region, drain region, and the channel region between source region and drain region, institute
Stating channel region includes the firstth area, when thin film transistor (TFT) is turned on, the channel region between source region and the firstth area, and positioned at leakage
Channel region between area and the firstth area forms conducting channel, and conducting channel is formed rather than whole channel region, reduces conductive ditch
The length in road, makes the breadth length ratio of channel region less than the breadth length ratio of conducting channel, and less channel region breadth length ratio is obtained in that small
Off-state current Ioff, the breadth length ratio of larger conducting channel is obtained in that big operating current Ion, has reached and has optimized Ion simultaneously
With the purpose of Ioff, the performance of thin film transistor (TFT) is improved.
Wherein, any signal can not be applied on conductive pattern 5, it is also possible to be grounded, or applies a fixed voltage.Conductive pattern
Shape 5 can be located at the same side of active layer 1 with source electrode 2, drain electrode 3.Optionally, conductive pattern 5 and source electrode 2, drain electrode 3
Set with layer, be obtained by same Source and drain metal level, simplify manufacture craft, reduce production cost.
In the present embodiment, the surface contacted with conductive pattern 5 for setting the channel region of active layer 1 has out-of-flatness structure,
To increase the effective length of channel region, reduce breadth length ratio, obtain smaller off-state current Ioff.Simultaneously as thin film transistor (TFT)
During conducting, the channel region between source electrode 2 and conductive pattern 5, and the ditch between drain electrode 3 and conductive pattern 5
Road area forms conducting channel, therefore, the setting of the out-of-flatness structure will not increase the length of conducting channel, not interfere with ON state
Electric current Ion.
In a specific embodiment, as shown in figure 1, conductive pattern 5 be arranged on active layer 1 away from substrate 100
Surface on, the surface contacted with conductive pattern 5 of the channel region of active layer 1 has at least one groove 10, by it is described at least
One groove 10 forms the out-of-flatness structure, to increase the effective length of channel region.Specifically principle is：As shown in Figure 2,
The side wall of groove 10 and the out of plumb of substrate 100, the length L of side wall>The length L ＇ of projection of the side wall in substrate 100, increased
The effective length of channel region.It should be noted that in the embodiment of the present invention length of a certain structure each mean from channel region be close to
The side of source electrode 2 near drain electrode 3 side direction on, the development length of the structure.
In another particular embodiment of the invention, as shown in figure 3, conductive pattern 5 be arranged on active layer 1 away from substrate
On 100 surface, the surface contacted with conductive pattern 5 of the channel region of active layer 1 has at least one projection 11, by least one
Individual raised 11 form the out-of-flatness structure, to increase the effective length of channel region.Its principle is similar to the above, no longer detailed herein
State.
It is contemplated that above-mentioned two specific embodiment can also be combined, by least one groove and at least one
The out-of-flatness structure is convexed to form, to increase the effective length of channel region.
As shown in figure 1, thin film transistor (TFT) is specifically included in the present embodiment：
Transparent substrate 100；
It is arranged on the gate electrode 4 in substrate 100；
The gate insulation layer 101 of covering grid electrode 4；
It is arranged on the active layer 1 on gate insulation layer 101；
It is arranged on source electrode 2 on active layer 1, drain electrode 3 and conductive pattern 5, source electrode 2, drain electrode 3 and conductive pattern
5 are set with layer, are obtained by same Source and drain metal level.
Wherein, active layer 1 includes the drain region that the source region contacted with source electrode 2 is contacted with drain electrode 3, and positioned at described
Channel region between source region and drain region, the channel region includes the firstth area contacted with conductive pattern 5, firstth area and conduction
The surface of the contact of figure 5 has at least one groove 10.
It should be noted that being only above specifically to introduce film crystal in the present invention by taking bottom gate thin film transistor as an example
The concrete structure of pipe, technical scheme is not limited to apply on bottom gate thin film transistor, can be applied in
On the other kinds of thin film transistor (TFT) such as top gate type thin film transistor.It is, of course, also possible to according to the actual requirements to thin film transistor (TFT)
Structure carry out Reasonable adjustment, for example：Active layer can also be arranged on source electrode, drain electrode and conductive pattern, and
The surface away from substrate of conductive pattern sets groove, and it belongs to protection scope of the present invention.
A kind of display base plate and display device are also provided in the present embodiment, the display base plate includes film as described above
Transistor.The display device includes display base plate as described above.Due to simultaneously optimize the thin film transistor (TFT) Ion and
Ioff, improves the performance of thin film transistor (TFT), so as to improve the display quality of product.
The display device can be liquid crystal display device, OLED display, Electronic Paper etc..
Embodiment two
As shown in figure 1, the preparation method that the thin film transistor (TFT) in a kind of embodiment one is provided in the present embodiment, including：
Active layer 1, source electrode 2, drain electrode 3 and gate electrode 4 are formed in a substrate 100, active layer 1 includes and source electrode
The drain region that the source region of 2 contacts is contacted with drain electrode 3, and the channel region between the source region and drain region, the making side
Method also includes：
The conductive pattern 5 that formation is contacted with the surface of the channel region, conductive pattern 5 insulate with source electrode 2, drain electrode 3
Set.
By thin film transistor (TFT) obtained in above-mentioned preparation method, during its conducting, only by positioned at source electrode 2 and conductive pattern 5
Between channel region, and channel region between drain electrode 3 and conductive pattern 5 forms conducting channel, makes to be formed during conducting
Conducting channel breadth length ratio more than cut-off when channel region breadth length ratio, reached simultaneously optimize Ion and Ioff purpose, lifting
The performance of thin film transistor (TFT).
Optionally, the conductive pattern, source electrode and electric leakage are formed simultaneously by the patterning processes to same conductive film
Pole reduces production cost to simplify manufacture craft.It is of course also possible to increasing independent patterning processes is manufactured separately conductive pattern.
Specifically, with reference to shown in Fig. 1 and Fig. 7, the conduction is formed simultaneously by the patterning processes to same conductive film
The step of figure, source electrode and drain electrode, can include：
A conductive film 103 is formed, as shown in Figure 7；
Photoresist is coated on conductive film；
The photoresist is exposed, photoresist reservation region and photoresist not reservation region are formed after development, wherein,
Region where the photoresist reservation region correspondence conductive pattern, source electrode and drain electrode, reservation region is not corresponding for photoresist
Other regions；
The conductive film of removal photoresist not reservation region；
Remaining photoresist is peeled off, conductive pattern 5, source electrode 2 and drain electrode 3 is formed, as shown in Figure 1.
Above-mentioned steps make conductive pattern 5, source electrode 2 and drain electrode 3 by the photoetching process to same conductive film.Institute
Stating conductive film can be by Cu, and the alloy of the metal such as Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and these metals is obtained,
The conductive film can be single layer structure or sandwich construction, sandwich construction such as Cu Mo, Ti Cu Ti, Mo Al Mo etc..
With reference to shown in Fig. 1 and Fig. 3, in the present embodiment, the preparation method also includes：
Out-of-flatness structure is formed on the surface contacted with conductive pattern 5 of the channel region of active layer 1.
Out-of-flatness structure is obtained by above-mentioned steps, the effective length of channel region can be increased, reduce breadth length ratio, obtain more
Small off-state current Ioff.Simultaneously as when thin film transistor (TFT) is turned on, the channel region between source electrode and conductive pattern,
And the channel region between drain electrode and conductive pattern forms conducting channel, therefore, the setting of the out-of-flatness structure is not
The length of conducting channel can be increased, ON state current Ion is not interfered with.
In a specific embodiment, as shown in figure 1, the surface contacted with conductive pattern 5 tool of the channel region
There is at least one groove 10, the out-of-flatness structure is formed by least one groove 10.Then combine shown in Fig. 4-Fig. 6, be formed with
The step of active layer 1, includes：
Semiconductive thin film 102 is formed, as shown in figure 4, semiconductive thin film 102 can be by HIZO, ZnO, TiO2、CdSnO、
The metal-oxide semiconductor (MOS)s such as MgZnO, IGO, IZO, ITO or IGZO are obtained, it is also possible to by silicon semiconductors such as non-crystalline silicon, polysilicons
It is obtained；
Photoresist 12 is coated on semiconductive thin film 102；
Photoresist 12 is exposed, after development formed photoresist be fully retained region, photoresist part reservation region and
Photoresist not reservation region, wherein, photoresist is fully retained where the part in addition to groove of the region correspondence active layer
Region, the region where the photoresist part reservation region correspondence groove, photoresist not other regions of reservation region correspondence,
As shown in Figure 5；
The semiconductive thin film of removal photoresist not reservation region；
The photoresist of photoresist part reservation region is removed by cineration technics；
The semiconductive thin film of the segment thickness of removal photoresist part reservation region；
Remaining photoresist is peeled off, forming surface has the active layer 1 of groove 10, as shown in Figure 6.
Above-mentioned steps have the active layer 1 of groove 10 using gray tone or intermediate tone mask plate shape into surface, by groove 10
The out-of-flatness structure is formed, to increase the effective length of channel region, specific principle is introduced in content above, herein not
Repeat again.
In another particular embodiment of the invention, as shown in figure 3, the surface contacted with conductive pattern 5 of the channel region
With at least one projection 11, the out-of-flatness structure is formed by least one raised 11.Then, the step of forming active layer is wrapped
Include：
Form semiconductive thin film；
Photoresist is coated on the semiconductive thin film；
The photoresist is exposed, photoresist is formed after development region, photoresist part reservation region is fully retained
With photoresist not reservation region, wherein, photoresist the region correspondence projection is fully retained where region, photoresist part is protected
Region where staying region to correspond to the part in addition to projection of the active layer, reservation region does not correspond to other areas to photoresist
Domain；
The semiconductive thin film of removal photoresist not reservation region；
The photoresist of photoresist part reservation region is removed by cineration technics；
The semiconductive thin film of the segment thickness of removal photoresist part reservation region；
Remaining photoresist is peeled off, forming surface has raised active layer.
Above-mentioned steps have raised active layer using gray tone or intermediate tone mask plate shape into surface, by convexing to form
Out-of-flatness structure is stated, to increase the effective length of channel region, its principle is similar to the above, will not be described in detail herein.
It is contemplated that above-mentioned two specific embodiment can also be combined, by least one groove and at least one
The out-of-flatness structure is convexed to form, to increase the effective length of channel region.
With reference to shown in Fig. 1, Fig. 4-Fig. 7, by taking bottom gate thin film transistor as an example, thin film transistor (TFT) is specific in the present embodiment
Manufacturing process is：
One transparent substrate 100 is provided；
Gate electrode 4 is formed in substrate 100, gate electrode 4 can be by Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W etc.
The alloy of metal and these metals is obtained, and gate electrode 4 can be single layer structure or sandwich construction, sandwich construction such as Cu
Mo, Ti Cu Ti, Mo Al Mo etc.；
Form the gate insulation layer 101 of covering grid electrode 4, the material of gate insulation layer 101 can from oxide, nitride or
Person's nitrogen oxides, can be individual layer, double-deck or sandwich construction.Specifically, the material of gate insulation layer 101 can be SiNx, SiOx
Or Si (ON) x；
Active layer 1 is formed on gate insulation layer 101.Specifically, as shown in figure 4, forming semiconductor on gate insulation layer 101
Film 102, coats photoresist 12 on semiconductive thin film 102, and photoresist 12 is carried out using gray tone or intermediate tone mask plate
Exposure, forms photoresist and region, photoresist part reservation region and photoresist not reservation region is fully retained after development, wherein,
Photoresist is fully retained the region where region corresponds to the part in addition to groove of the active layer, photoresist part reserved area
Domain region correspondingly where the groove, reservation region does not correspond to other regions to photoresist, as shown in Figure 5；Removal photoresist is not
The semiconductive thin film of reservation region；The photoresist of photoresist part reservation region is removed by cineration technics；Removal photoresist portion
Divide the semiconductive thin film of the segment thickness of reservation region；Remaining photoresist is peeled off, forming surface has the active layer of groove 10
1, as shown in Figure 6；
Conductive film 103 is formed on active layer 1, as shown in Figure 7；
Source electrode 2, drain electrode 3 and conductive pattern 5 are formed by the patterning processes to conductive film 103, conductive pattern 5 connects
Touch and be arranged on the groove 10 on the surface of active layer 1, source electrode 2 and drain electrode 3 are overlapped on active layer 1, as shown in Figure 1.
So far the making of thin film transistor (TFT) is completed.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, on the premise of the technology of the present invention principle is not departed from, some improvement and replacement can also be made, these improve and replace
Also should be regarded as protection scope of the present invention.
Claims (13)
1. a kind of thin film transistor (TFT), including active layer in a substrate, source electrode and drain electrode are arranged on, the active layer includes
The drain region that the source region contacted with the source electrode is contacted with the drain electrode, and the ditch between the source region and drain region
Road area, it is characterised in that the thin film transistor (TFT) also includes the conductive pattern contacted with the surface of the channel region, the conduction
Figure and source electrode, drain electrode insulation set.
2. thin film transistor (TFT) according to claim 1, it is characterised in that the channel region is contacted with the conductive pattern
Surface there is out-of-flatness structure.
3. thin film transistor (TFT) according to claim 2, it is characterised in that the conductive pattern is arranged on the active layer
On the surface of the substrate, the surface contacted with the conductive pattern of the channel region has at least one groove, by
At least one groove forms the out-of-flatness structure.
4. thin film transistor (TFT) according to claim 2, it is characterised in that the conductive pattern is arranged on the active layer
On the surface of the substrate, the surface contacted with the conductive pattern of the channel region has at least one projection, by
Described at least one convexes to form the out-of-flatness structure.
5. the thin film transistor (TFT) according to claim any one of 1-4, it is characterised in that the conductive pattern and source electricity
Pole, drain electrode are set with layer.
6. the preparation method of a kind of thin film transistor (TFT) as described in claim any one of 1-5, including：
Form active layer, source electrode and drain electrode in a substrate, source region that the active layer includes being contacted with the source electrode,
The drain region contacted with the drain electrode, and the channel region between the source region and drain region, it is characterised in that the making
Method also includes：
The conductive pattern that formation is contacted with the surface of the channel region, the conductive pattern and source electrode, drain electrode insulation set.
7. preparation method according to claim 6, it is characterised in that the preparation method also includes：
Out-of-flatness structure is formed on the surface contacted with the conductive pattern of the channel region.
8. preparation method according to claim 7, it is characterised in that the channel region is contacted with the conductive pattern
Surface has at least one groove, and the out-of-flatness structure is formed by least one groove, wraps the step of form active layer
Include：
Form semiconductive thin film；
Photoresist is coated on the semiconductive thin film；
The photoresist is exposed, photoresist is formed after development region, photoresist part reservation region and light is fully retained
Photoresist not reservation region, wherein, photoresist is fully retained where the part in addition to groove of the region correspondence active layer
Region, photoresist part reservation region region correspondingly where the groove, reservation region does not correspond to other regions to photoresist；
The semiconductive thin film of removal photoresist not reservation region；
The photoresist of photoresist part reservation region is removed by cineration technics；
The semiconductive thin film of the segment thickness of removal photoresist part reservation region；
Remaining photoresist is peeled off, surface is formed and is had reeded active layer.
9. preparation method according to claim 7, it is characterised in that the channel region is contacted with the conductive pattern
Surface has at least one raised, and the out-of-flatness structure is convexed to form by described at least one, wraps the step of form active layer
Include：
Form semiconductive thin film；
Photoresist is coated on the semiconductive thin film；
The photoresist is exposed, photoresist is formed after development region, photoresist part reservation region and light is fully retained
Photoresist not reservation region, wherein, photoresist the region correspondence projection is fully retained where region, photoresist part reserved area
Domain region correspondingly where the part in addition to projection of the active layer, reservation region does not correspond to other regions to photoresist；
The semiconductive thin film of removal photoresist not reservation region；
The photoresist of photoresist part reservation region is removed by cineration technics；
The semiconductive thin film of the segment thickness of removal photoresist part reservation region；
Remaining photoresist is peeled off, forming surface has raised active layer.
10. the preparation method according to claim any one of 6-9, it is characterised in that by the structure to same conductive film
Figure technique forms the conductive pattern, source electrode and drain electrode simultaneously.
11. preparation methods according to claim 10, it is characterised in that same by the patterning processes to same conductive film
When include the step of form the conductive pattern, source electrode and drain electrode：
Form conductive film；
Photoresist is coated on the conductive film；
The photoresist is exposed, photoresist reservation region and photoresist not reservation region are formed after development, wherein, photoetching
Glue reservation region region correspondingly where the conductive pattern, source electrode and drain electrode, reservation region does not correspond to other to photoresist
Region；
The conductive film of removal photoresist not reservation region；
Remaining photoresist is peeled off, the conductive pattern, source electrode and drain electrode is formed.
12. a kind of display base plates, it is characterised in that including the thin film transistor (TFT) described in claim any one of 1-5.
13. a kind of display devices, it is characterised in that including the display base plate described in claim 12.
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