CN106783879B - Array substrate, display panel, display device and array substrate preparation method - Google Patents
Array substrate, display panel, display device and array substrate preparation method Download PDFInfo
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- CN106783879B CN106783879B CN201611206273.7A CN201611206273A CN106783879B CN 106783879 B CN106783879 B CN 106783879B CN 201611206273 A CN201611206273 A CN 201611206273A CN 106783879 B CN106783879 B CN 106783879B
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- metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Abstract
The invention discloses the preparation methods of a kind of array substrate, display panel, display device and array substrate.The array substrate includes: first substrate；The first metal layer is set to the first substrate side；First insulating layer is set to the first metal layer back to the first substrate side；Semiconductor layer is set to first insulating layer back to the first metal layer side；Second metal layer is set to the semiconductor layer back to first insulating layer side；Second insulating layer is set to the second metal layer back to the semiconductor layer side；Pixel electrode is set to the second insulating layer back to the second metal layer side；Wherein, the second insulating layer is equipped with the first via hole, for being electrically connected the second metal layer and the pixel electrode, the first metal layer and the second metal layer constitute the first storage capacitance, and the first metal layer and the pixel electrode constitute the second storage capacitance.By the above-mentioned means, being capable of increasing aperture opening ratio.
Description
Technical field
The present invention relates to field of liquid crystal display, more particularly to a kind of array substrate, display panel, display device and array
The preparation method of substrate.
Background technique
Thin-film transistor array base-plate is in LCD (Liquid Crystal Display, LCD) and OLED (Organic
Light-Mmitting Diode, OLED) in be widely used, generally comprise glass substrate and be formed in thin on glass substrate
Film transistor and storage capacitance.
Storage capacitance performer in thin-film transistor array base-plate keeps current potential, reduces the important works such as coupled capacitor partial pressure
With when increasing storage capacitance, it is possible to increase the maintenance ability of pixel voltage, the coupling of reduction cabling is to pixel voltage size and uniformly
The influence of property, promotes the quality of panel.Storage capacitance is generally made with the sandwiched insulating layer of metal, metal be it is lighttight, when me
Increase two metal plates relative area increase storage capacitance when, aperture opening ratio can be lowered.
Summary of the invention
The invention mainly solves the technical problem of providing a kind of array substrate, display panel, display device and array bases
The preparation method of plate can be realized while with larger storage capacitance, aperture opening ratio with higher.
To solve the above problems, one technical scheme adopted by the invention is that: a kind of array substrate is provided, comprising:
First substrate；
The first metal layer is set to the first substrate side；
First insulating layer is set to the first metal layer back to the first substrate side；
Semiconductor layer is set to first insulating layer back to the first metal layer side；
Second metal layer is set to the semiconductor layer back to first insulating layer side；
Second insulating layer is set to the second metal layer back to the semiconductor layer side；
Pixel electrode is set to the second insulating layer back to the second metal layer side；
Wherein, the second insulating layer is equipped with the first via hole, for being electrically connected the second metal layer and the pixel
Electrode, the first metal layer and the second metal layer constitute the first storage capacitance, the first metal layer and the pixel
Electrode constitutes the second storage capacitance.
Wherein, the second insulating layer, the second metal layer and the semiconductor layer are equipped with the second via hole, the picture
Plain electrode extends to the hole wall and bottom hole of second via hole, so that constituting the second storage electricity with the first metal layer
Hold.
Wherein, first via hole and the second via hole same position or different location.
Wherein, first insulating layer and the second insulating layer are made of silicon nitride material, and the semiconductor layer is by non-
Crystal silicon material is made.
To solve the above problems, another technical solution used in the present invention is: providing a kind of display panel, including parallel
The array substrate and the second substrate of setting, the array substrate include:
First substrate；
The first metal layer is set to the first substrate side；
First insulating layer is set to the first metal layer back to the first substrate side；
Semiconductor layer is set to first insulating layer back to the first metal layer side；
Second metal layer is set to the semiconductor layer back to first insulating layer side；
Second insulating layer is set to the second metal layer back to the semiconductor layer side；
Pixel electrode is set to the second insulating layer back to the second metal layer side；
Wherein, the second insulating layer is equipped with the first via hole, for being electrically connected the second metal layer and the pixel
Electrode, the first metal layer and the second metal layer constitute the first storage capacitance, the first metal layer and the pixel
Electrode constitutes second storage capacitance.
Wherein, the second insulating layer, the second metal layer and the semiconductor layer are equipped with the second via hole, the picture
Plain electrode extends to the hole wall and bottom hole of second via hole, so that constituting the second storage capacitance with the first metal layer.
Wherein, first via hole and the second via hole same position or different location.
Wherein, first insulating layer and the second insulating layer are made of silicon nitride material, and the semiconductor layer is by non-
Crystal silicon material is made.
To solve the above problems, another technical solution that the present invention uses is: providing a kind of display device, including backlight
Mould group and display panel as described above.
To solve the above problems, another technical solution that the present invention uses is: providing a kind of preparation side of array substrate
Method, which comprises
First substrate is provided；
The first metal layer is formed in the first substrate side；
The side back to the first substrate of the first metal layer sequentially form the first insulating layer, semiconductor layer,
Second metal layer, second insulating layer and pixel electrode；
The first via hole is opened up on the second insulating layer, for being electrically connected the second metal layer and pixel electricity
Pole, the first metal layer and the second metal layer constitute the first storage capacitance, the first metal layer and pixel electricity
Pole constitutes the second storage capacitance.
The beneficial effects of the present invention are: the present invention is by subtracting the storage capacitance partial insulative layer thickness in array substrate
It is thin, while guaranteeing array substrate storage capacitance size, improve aperture opening ratio.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of one embodiment of array substrate of the present invention；
Fig. 2 is the structural schematic diagram of another embodiment of array substrate of the present invention；
Fig. 3 is that the invention shows the structural schematic diagrams of one embodiment of panel；
Fig. 4 is the structural schematic diagram of one embodiment of the display device of that present invention；
Fig. 5 is the flow diagram of one embodiment of preparation method of array substrate of the present invention.
Specific embodiment
Refering to fig. 1, Fig. 1 is the structural schematic diagram of one embodiment of array substrate of the present invention, and the array substrate 1 includes:
First substrate 10 has excellent optical property, and higher transparency and lower reflectivity are for example, can be used glass
Glass material is made.
The first metal layer 11, is set to 10 side of first substrate, the first metal layer 10 be molybdenum layer, aluminium layer, titanium layer or
Layers of copper or any two layers of stacking.
First insulating layer 12 is set to the first metal layer 11 back to 10 side of first substrate, the first insulating layer
12 at least partly cover the first metal layer 11, can be made of one or more layers insulating materials, such as silicon nitride or other insulating materials.
Semiconductor layer 13 is set to first insulating layer 12 back to 11 side of the first metal layer, the semiconductor
Layer 13 can be made of amorphous silicon material.
Second metal layer 14 is set to the semiconductor layer 13 back to 12 side of the first insulating layer, second gold medal
Belong to layer 14 to be made of aluminium layer, titanium layer, layers of copper or other metal materials.
Second insulating layer 15, is set to the second metal layer 14 back to 13 side of semiconductor layer, by silicon nitride or
Other insulating materials are made.
Pixel electrode 16 is set to the second insulating layer 15 back to 14 side of second metal layer, the pixel electricity
Pole 16 is transparency conducting layer made of indium tin oxide (ITO) material.
Wherein, the second insulating layer 15 is equipped with the first via hole 17, for being electrically connected the second metal layer 14 and institute
State pixel electrode 16.
The second metal layer 14 constitutes the first storage capacitance Cst1 with the first metal layer 11.
Please continue to refer to Fig. 1, second insulating layer 15 described in Fig. 1, the second metal layer 14 and the semiconductor layer
The second via hole 18 is additionally provided on 13, the pixel electrode 16 extends to the hole wall 181 and bottom hole 182 of second via hole 18, with
So that the pixel electrode 16 constitutes the second storage capacitance Cst2 with the first metal layer 11.The second storage capacitance Cst2
Thickness of insulating layer be less than the first storage capacitance Cst1 thickness of insulating layer.
In an application scenarios, as the second storage capacitance Cst2 and the first face having the same storage capacitance Cst1
When product, the second storage capacitance Cst2 is bigger than the first storage capacitance Cst1, and still, the embodiment of the present invention is not restricted to this.
The pixel electrode 16 is electrically connected by the first via hole 17 and the second metal layer 14, therefore second metal
Layer 14 and the pixel electrode 16 current potential having the same, the first storage capacitance Cst1 and the second storage capacitance Cst2 parallel connection connect
Connect, thus total storage capacitance Cst of the array substrate 1 be the first storage capacitance Cst1 and the second storage capacitance Cst2 size it
With.
In above-described embodiment, by the second via hole 18 of setting, the partial insulative layer thickness of the array substrate 1 is thinned,
So that increasing the size of storage capacitance Cst when the storage capacitance Cst relative area of array substrate 1 is constant or working as array substrate 1
When storage capacitance Cst size is constant, the relative area of storage capacitance Cst can be reduced, to improve aperture opening ratio.It is understood that
It is that in other embodiments, first via hole 17 and second via hole 18 can be the same via hole, i.e., the described pixel electricity
Pole 16 passes through the same via hole and the second insulating layer 15, second metal layer 14, semiconductor layer 13 and the first insulating layer 12
Connection.
Simultaneously it will also be appreciated that in other embodiments, the position of second via hole 18 can be with first via hole
17 position is different.
Referring to Fig. 2, Fig. 2 is the structural schematic diagram of another embodiment of array substrate of the present invention.
In the present embodiment, second via hole 18 is not identical as the position of the first via hole 17, and the array substrate 1 is deposited
Storage holds the sum of the size that Cst is still the first storage capacitance Cst1 and the second storage capacitance Cst2, second storage capacitance
Thickness of insulating layer of the thickness of insulating layer of Cst2 less than the first storage capacitance Cst1, when the storage capacitance Cst size of array substrate 1
When constant, the relative area of storage capacitance Cst can be reduced, improve aperture opening ratio.
It should be noted that any restrictions are not done to the shape of the first via hole 17 and the second via hole 18 in the present embodiment,
It can be step type, as shown in figure 1 shown in the second via hole 18, or inverted trapezoidal, such as the first via hole 17 and the second via hole in Fig. 2
Shown in 18 or other shapes.
Referring to Fig. 3, Fig. 3 is the structural schematic diagram of one embodiment of liquid crystal display panel of the present invention, including disposed in parallel
Array substrate 1 and the second substrate 2.
The array substrate 1 is that the array base-plate structure in above-described embodiment is same or similar, and details are not described herein.
The material of the second substrate 2 requires identical as the material requirement of first substrate 10, that is, needs excellent optical
Can, higher transparency and lower reflectivity.
The liquid crystal display panel further includes the liquid crystal layer being arranged between the array substrate 10 and the second substrate 2
(not shown).
Display panel described in the present embodiment can not reduced due to using the array substrate in above-described embodiment
In the case where the display panel aperture opening ratio, increases total storage capacitance Cst of the array substrate, improve the product of display panel
Matter, or total storage capacitance Cst can be reduced in the case where the total storage capacitance Cst size of the array substrate is constant
Area, improve the aperture opening ratio of display panel.
Referring to Fig. 4, Fig. 4 is the structural schematic diagram of one embodiment of liquid crystal display device of the present invention, liquid crystal display device packet
The liquid crystal display panel in backlight module 3 and above-described embodiment is included, the liquid crystal display device further includes the optics such as polaroid member
Part is not illustrated in Fig. 4.
Referring to Fig. 5, Fig. 5 is the flow diagram of one embodiment of array substrate preparation method of the present invention, it is main as follows
Step includes:
S51: first substrate is provided.
S52: the first metal layer is formed in the first substrate side.
S53: semiconductor layer, the second metal are sequentially formed in the side back to the first substrate of the first metal layer
Layer, second insulating layer.
S54: opening up the first via hole on the second insulating layer, for being electrically connected the second metal layer and the picture
Plain electrode, the first metal layer and the second metal layer constitute the first storage capacitance, the first metal layer and the picture
Plain electrode constitutes the second storage capacitance.
The position of each element and requirement are identical as in above-described embodiment in above-mentioned steps, and details are not described herein.On
Stating technique used by step includes: the patterning processes such as the film-forming process such as deposition, sputtering, etching.In addition, in above-mentioned steps S54
Later, by transparent substrate, parallel over being formed in array substrate, the invention shows panels；Further by above-mentioned display panel
It is combined with backlight module and forms inventive display.
It is different from the prior art, the present invention is protected by the way that the storage capacitance partial insulative layer thickness in array substrate to be thinned
While demonstrate,proving array substrate storage capacitance size, aperture opening ratio is improved.
It should be pointed out that in the accompanying drawings, for the size that clearly may be exaggerated layer and region of diagram.And it can be with
Understand, it can be a variety of that each layer, which is not limited to a kind of element,；Furthermore, it is to be appreciated that when element or layer be referred to
When another element or layer " side ", it can be directly in other elements, or there may be intermediate layers.
The above description is only an embodiment of the present invention, is not intended to limit the scope of the invention, bored to utilize this hair
Equivalent structure or equivalent flow shift made by bright specification and accompanying drawing content is applied directly or indirectly in other relevant skills
Art field, is included within the scope of the present invention.
Claims (8)
1. a kind of array substrate characterized by comprising
First substrate；
The first metal layer is set to the first substrate side；
First insulating layer is set to the first metal layer back to the first substrate side；
Semiconductor layer is set to first insulating layer back to the first metal layer side；
Second metal layer is set to the semiconductor layer back to first insulating layer side；
Second insulating layer is set to the second metal layer back to the semiconductor layer side；
Pixel electrode is set to the second insulating layer back to the second metal layer side；
Wherein, the second insulating layer is equipped with the first via hole, for being electrically connected the second metal layer and the pixel electrode,
The first metal layer and the second metal layer constitute the first storage capacitance, the first metal layer and the pixel electrode structure
At the second storage capacitance, and simultaneously, the second insulating layer, the second metal layer and the semiconductor layer are equipped with the second mistake
Hole, the pixel electrode extend to the hole wall and bottom hole of second via hole, so that with described in the first metal layer composition
Second storage capacitance.
2. substrate as described in claim 1, which is characterized in that
First via hole and the second via hole same position or different location.
3. such as the described in any item substrates of claim 1 to 2, which is characterized in that
First insulating layer and the second insulating layer are made of silicon nitride material, and the semiconductor layer is by amorphous silicon material system
At.
4. a kind of display panel, which is characterized in that including array substrate disposed in parallel and the second substrate, the array substrate packet
It includes:
First substrate；
The first metal layer is set to the first substrate side；
First insulating layer is set to the first metal layer back to the first substrate side；
Semiconductor layer is set to first insulating layer back to the first metal layer side；
Second metal layer is set to the semiconductor layer back to first insulating layer side；
Second insulating layer is set to the second metal layer back to the semiconductor layer side；
Pixel electrode is set to the second insulating layer back to the second metal layer side；
Wherein, the second insulating layer is equipped with the first via hole, for being electrically connected the second metal layer and the pixel electrode,
The first metal layer and the second metal layer constitute the first storage capacitance, the first metal layer and the pixel electrode structure
At the second storage capacitance, and simultaneously, the second insulating layer, the second metal layer and the semiconductor layer are equipped with the second mistake
Hole, the pixel electrode extend to the hole wall and bottom hole of second via hole, so that constituting second with the first metal layer
Storage capacitance.
5. display panel as claimed in claim 4, which is characterized in that
First via hole and the second via hole same position or different location.
6. such as the described in any item display panels of claim 4 to 5, which is characterized in that
First insulating layer and the second insulating layer are made of silicon nitride material, and the semiconductor layer is by amorphous silicon material system
At.
7. a kind of display device, which is characterized in that including backlight module and such as the described in any item display surfaces of claim 4 to 6
Plate.
8. a kind of preparation method of array substrate, which is characterized in that the described method includes:
First substrate is provided；
The first metal layer is formed in the first substrate side；
The first insulating layer, semiconductor layer, second are sequentially formed in the side back to the first substrate of the first metal layer
Metal layer, second insulating layer and pixel electrode；
The first via hole is opened up on the second insulating layer, for being electrically connected the second metal layer and the pixel electrode,
The first metal layer and the second metal layer constitute the first storage capacitance, the first metal layer and the pixel electrode structure
At the second storage capacitance,
Wherein, while opening up the first via hole on the second insulating layer, in the second insulating layer, the second metal layer
And the semiconductor layer opens up the second via hole so that the pixel electrode extend to second via hole hole wall and bottom hole and
Second storage capacitance is constituted with the first metal layer.
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| CN201611206273.7A CN106783879B (en) | 2016-12-23 | 2016-12-23 | Array substrate, display panel, display device and array substrate preparation method |
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| CN201611206273.7A CN106783879B (en) | 2016-12-23 | 2016-12-23 | Array substrate, display panel, display device and array substrate preparation method |
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| CN106783879A CN106783879A (en) | 2017-05-31 |
| CN106783879B true CN106783879B (en) | 2019-09-20 |
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| CN108614317B (en) * | 2018-05-09 | 2021-05-18 | 京东方科技集团股份有限公司 | Preparation method of polaroid, display substrate and display device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101109881A (en) * | 2007-07-06 | 2008-01-23 | 昆山龙腾光电有限公司 | LCD panel and its manufacturing method |
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| KR101086478B1 (en) * | 2004-05-27 | 2011-11-25 | 엘지디스플레이 주식회사 | Thin Film Transistor Substrate for Display Device And Method For Fabricating The Same |
| TWI423195B (en) * | 2010-10-18 | 2014-01-11 | Au Optronics Corp | Pixel structure |
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| CN101109881A (en) * | 2007-07-06 | 2008-01-23 | 昆山龙腾光电有限公司 | LCD panel and its manufacturing method |
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Address after: No.9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: No.9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |