CN110082973A - The display panel and its manufacturing method that parasitic capacitance reduces - Google Patents
The display panel and its manufacturing method that parasitic capacitance reduces Download PDFInfo
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- CN110082973A CN110082973A CN201910068446.0A CN201910068446A CN110082973A CN 110082973 A CN110082973 A CN 110082973A CN 201910068446 A CN201910068446 A CN 201910068446A CN 110082973 A CN110082973 A CN 110082973A
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- line
- gating line
- gating
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- data lines
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Abstract
The display panel and its manufacturing method that parasitic capacitance reduces.Present disclose provides a kind of display panel for reducing the parasitic capacitance occurred in the cross part of gating line and data line and the methods for manufacturing the display panel.Display panel according to illustrative embodiments includes: a plurality of gating line, and a plurality of gating line is formed on substrate；Insulating layer, the insulating layer are formed on a plurality of gating line；And multiple data lines, the multiple data lines are formed on the insulating layer to cross a plurality of gating line, so as to cause overlapping region is generated, in the overlapping region, the multiple data lines are horizontally intersected with a plurality of gating line but are vertically spaced from a plurality of gating line.The a plurality of gating line and the multiple data lines are formed the width in the overlapping region is narrower than the width in non-overlapping region according to a plurality of gating line and the multiple data lines.
Description
Technical field
This disclosure relates to more specifically display panel is related to the parasitism occurred in the cross part of gating line and data line
The display panel that capacitor reduces.Moreover, it relates to the parasitism electricity for will occur in the cross part of gating line and data line
Hold the method for the manufacture display panel reduced.
Background technique
Due to the various portable electrics to such as mobile phone, personal digital assistant (PDA) and notebook computer etc
The demand of small-sized display device needed for sub- equipment increases together with the demand to large-scale high-quality display equipment, therefore to plate
Show that the demand of equipment is more and more.The example of flat panel display equipment includes liquid crystal display (LCD) equipment, Organic Light Emitting Diode
(OLED) show that equipment, plasma display equipment, Field emission displays (FED) equipment and vacuum fluorescence show (VFD) equipment.
In these flat panel display equipments, liquid crystal display is because mass production techniques are horizontal, device drives are easy and energy
It enough realizes high quality graphic and people is being attracted to pay attention to and be used widely.
The operating principle of liquid crystal display utilizes the physical characteristic of the liquid crystal molecule including optical anisotropy and polarization.
Liquid crystal molecule is thin and grows, and directionality is shown in molecules align.The direction of molecules align in liquid crystal can pass through to
Liquid crystal applies electric field and changes.If suitably adjusting the direction of the molecules align in liquid crystal, the molecules align of liquid crystal can be with
Change, and the light for passing through liquid crystal can be refracted due to optical anisotropy on the direction of molecules align,
Image information can be expressed by liquid crystal display.Currently, it the unit pixel that is formed by thin film transistor (TFT) (TFT) and is connected to
Unit pixel with transmit signal gating line and the active matrix liquid crystal display device that is arranged in matrix of data line due to it
Excellent resolution ratio and video display capability and attracted most attentions.
However, as the size of liquid crystal display becomes increasing and device resolution becomes higher and higher, to
The gating line of pixel transmission signal and the cross part of data line increase, this causes the parasitic capacitance occurred in cross part to increase.
[prior art reference]
[patent document]
Korean Unexamined Patent discloses No.2004-0044588 (on May 31st, 2004)
Summary of the invention
According to the disclosure, providing a kind of reduces the parasitic capacitance occurred in the cross part of gating line and data line
Display panel and the method for manufacturing the display panel.
Additional aspect will partially elaborate in the description that follows, and will partly become apparent from the description, or
It can be known by practicing provided illustrative embodiments.
One aspect according to illustrative embodiments, a kind of display panel include: a plurality of gating line, a plurality of gating
Line is formed on substrate；Insulating layer, the insulating layer are formed on a plurality of gating line；And multiple data lines, it is described more
Data line is formed on the insulating layer to cross a plurality of gating line, so as to cause overlapping region is generated, in the friendship
In folded region, the multiple data lines intersect in the horizontal direction with a plurality of gating line but exist with a plurality of gating line
It is spaced apart on vertical direction.Compare in the overlapping region according to a plurality of gating line and the width of the multiple data lines
Narrow mode forms a plurality of gating line and the multiple data lines in non-overlapping region.
The display panel may further include: environment division, and each environment division is arranged in by a plurality of gating line
In a gating line and the multiple data lines in a data line limit space in and be connected to a plurality of choosing
The data line in a gating line and the multiple data lines in logical line.
The display panel may further include: auxiliary gating line, the auxiliary gating line is from a plurality of gating line
In a gating line extend the gating line in a plurality of gating line is connected to the environment division；
And auxiliary data line, the auxiliary data line extend from the data line in the multiple data lines with will be described more
The data line in data line is connected to the environment division.
Each environment division can include: grid, and the grid extends from the auxiliary gating line；It is apparatus insulated
Layer, the apparatus insulated layer cover the top of the grid and are formed integrally as single structure with the insulating layer；Equipment
Semiconductor layer, the equipment semiconductor layer in each overlapping region be formed in the multiple data lines described one
The semiconductor layer between a gating line in data line and a plurality of gating line is formed together exhausted in the equipment
In edge layer；And data electrode, the data electrode extend on the equipment semiconductor layer from the auxiliary data line.
The display panel may further include protective layer, and the protective layer covers multiple data lines, described auxiliary
Help data line and the environment division.
According to the one aspect of another illustrative embodiments, a method of manufacture display panel, this method include
Following steps: a plurality of gating line is formed on substrate；Insulating layer is formed on a plurality of gating line；And in the insulating layer
On multiple data lines are formed as to cross a plurality of gating line, so as to cause generate overlapping region, in the overlapping region,
The multiple data lines are intersected with a plurality of gating line in the horizontal direction but with a plurality of gating line in vertical direction
It is upper to be spaced apart.When forming a plurality of gating line and the multiple data lines, a plurality of gating line and a plurality of data
The width of line is formed narrower than in non-overlapping region in the overlapping region.
In the display panel according to the disclosure, the width of a plurality of gating line and the multiple data lines is formed as
It is narrower than in non-overlapping region in the overlapping region, to reduce the area of each overlapping region, so as to reduce
The parasitic capacitance occurred in the overlapping region.
Detailed description of the invention
The disclosure in order to better understand is now described with reference to the drawings the various shapes of the disclosure provided by way of example
Formula, in the accompanying drawings:
Fig. 1 is to show the plan view of the display panel according to embodiment of the present disclosure；
Fig. 2 is to show the gating line in the display panel according to embodiment of the present disclosure to overlap with what data line intersected
The sectional view in region；
Fig. 3 is to show the sectional view of the environment division of the display panel according to embodiment of the present disclosure；
Fig. 4 is to show manufacture according to the flow chart of the method for the display panel of embodiment of the present disclosure；And
Fig. 5 is to show the plan view of the display panel of another embodiment according to the disclosure.
Attached drawing described herein is only used for the purpose of illustration, and not in order to limit the disclosure in any way
Range.
[appended drawing reference description]
10: substrate 21,121: gating line
22: auxiliary gating line 23: grid
31: insulating layer 32: apparatus insulated layer
41: semiconductor layer 42: equipment semiconductor layer
51,151: data line 52: auxiliary data line
53: data electrode 61,62: protective layer
100,200: display panel
Specific embodiment
In following description and drawings, part necessary to understanding embodiment of the present disclosure will only be described, for letter
For the sake of list, it would be possible to omit the description of the ambiguous known function of the subject content of the disclosure or construction.
The term used in described below and appended claims and wording may not with common meaning or dictionary meanings into
Row is explained, but can suitably be limited herein for use as the term of the disclosure is described with possible best mode.These terms
It should be interpreted and the consistent meaning and concept of the technical concept of the disclosure with wording.The embodiment party described in the present specification
Formula and construction shown in the drawings are only the preferred embodiment of the disclosure, and not in order to limit the technology structure of the disclosure
Think.It should therefore be understood that there may be the various equivalents for replacing the illustrative embodiments when the application submits and repairing
Change.
Particularly, term " horizontally intersect " or " with ... horizontally intersects " be used herein refer to generation work as it is seen from above
When two components positional relationship intersected with each other.
Term " being vertically spaced from " or " with ... be vertically spaced from " be used herein refer to the side Dai Dangcong or front
Two components positional relationship spaced apart when viewing.
Describe the illustrative embodiments of the disclosure in detail below with reference to accompanying drawings.
Fig. 1 is to show the plan view of the display panel according to embodiment of the present disclosure, and Fig. 2 is shown according to this
The sectional view for the overlapping region that gating line intersects with data line in the display panel of disclosed embodiment, and Fig. 3 is to show
According to the sectional view of the environment division of the display panel of embodiment of the present disclosure.
It include a plurality of gating line 21, insulating layer according to the display panel 100 of embodiment of the present disclosure referring to figs. 1 to 3
31, semiconductor layer 41 and multiple data lines 51.Display panel 100 further comprises environment division 50, each environment division 50
It is arranged in the space limited by a gating line in a plurality of gating line 21 and the data line in multiple data lines 51 simultaneously
And it is connected to corresponding gating line 21 and corresponding data line 51.
A plurality of gating line 21 can be formed on the substrate 10.That is, a plurality of gating line 21 can be patterned into interval
Preset distance is opened to multiple rows parallel to each other.
The display scanning signal that gate driver (not shown) exports can sequentially be delivered to and set by a plurality of gating line 21
Standby part 50.
Insulating layer 31 can be formed on a plurality of gating line 21 so that multiple data lines 51 and a plurality of gating line 21 to insulate.It should
Insulating layer 31 can form along every gating line 21 or can be in the state of a plurality of 21 composition on the substrate 10 of gating line
It is formed in the whole surface of substrate 10.
Semiconductor layer 41 can be formed on insulating layer 31.Here, semiconductor layer 41 can be formed in a plurality of gating line 21
On to be spaced apart specific range in the vertical direction with gating line 21, and be used as the position reference for forming multiple data lines 51,
This allows to arrange multiple data lines 51 perpendicular to a plurality of gating line 21.In other words, semiconductor layer 41 can be formed in a plurality of choosing
In each overlapping region A of logical line 21 and 51 horizontal cross of multiple data lines.
It is formed in the overlapping region A that a plurality of gating line 21 intersects with multiple data lines 51 every in a plurality of gating line 21
Semiconductor layer 41 bar between gating line and the corresponding data line in multiple data lines 51 can be widened in overlapping region A
Gap between every gating line 21 and respective data lines 51.
Since semiconductor layer 41 increases every gating line 21 in a plurality of gating line 21 and between respective data lines 51
Distance, therefore semiconductor layer 41 reduces the parasitic capacitance occurred in overlapping region A.
In other words, semiconductor layer 41 increases between a plurality of gating line 21 in overlapping region A and multiple data lines 51
Distance flows to multiple data lines 51 from a plurality of gating line 21 and flows to a plurality of gating line 21 from multiple data lines 51 to reduce
Leakage current.
Semiconductor layer 41 can be formed together in the environment division 50 being described below with equipment semiconductor layer 42.Also
It is to say, when forming equipment semiconductor layer 42 in environment division 50, semiconductor layer 41 can be with equipment semiconductor layer 42 together
It is formed.Thus, semiconductor layer 41 can be readily formed without using individual additional masking.
Multiple data lines 51 can be formed on insulating layer 31 to cross semiconductor layer 41.In addition, multiple data lines 51 can be with
Be formed as perpendicular to a plurality of gating line 21.
Here, every two adjacent gating lines 21 and every two adjacent data perpendicular to this two adjacent gating lines 21
Line 51 can define or limit rectangular space.Environment division 50 can be formed in the rectangular space.
It may further include according to the display panel 100 of embodiment of the present disclosure from gating line 21 and extend will gate
Line 21 is connected to the auxiliary gating line 22 of environment division 50 and extends from data line 51 data line 51 is connected to environment division
50 auxiliary data line 52.
Each environment division 50, which can be arranged in, to be formed by two adjacent gating lines 21 and two adjacent data lines 51
In rectangular space, and it can connect to gating line 21 and data line 51.
Environment division 50 may include grid 23, apparatus insulated layer 32, equipment semiconductor layer 42 and data electrode 53.
Grid 23 extends from the auxiliary gating line 22 for being connected to gating line 21.Data electrode 53 is from being connected to data line 51
Auxiliary data line 52 extends, overlapping with grid 23, and including source electrode and drain electrode.Equipment semiconductor layer 42 is formed in data electrode
Between 53 source electrode and drain electrode.Apparatus insulated layer 32 can be formed between grid 23 and data electrode 53.Here, grid 10 can
With with gating line 21 together composition, and data electrode 53 can be with data line 51 together composition.In addition, equipment semiconductor layer 42
It can be with semiconductor layer 41 together composition.
In addition, a plurality of gating line 21, more can be further formed at according to the display panel 100 of embodiment of the present disclosure
Protective layer 61 and 62 on data line 51 or environment division 50.
Manufacture will be described in further detail now according to the method for the display panel of embodiment of the present disclosure.
Fig. 4 is to show manufacture according to the flow chart of the method for the display panel of embodiment of the present disclosure.
It can operated first referring to Fig. 4 according to manufacture according to the method for the display panel of embodiment of the present disclosure
A plurality of gating line is formed in S10 on substrate.The gating line of the shape of multiple rows with the preset distance that is separated from each other can be with
It is formed and depositing gating line on substrate and being optionally removed gating line source pattern.A plurality of gating line can will be by selecting
The display scanning signal of logical driver output is delivered to environment division.
While forming grid in the operation s 10, the grid that can be formed together with gating line in environment division.
In operation S20, insulating layer is formed on the substrate for being formed with a plurality of gating line.The insulating layer can be by a plurality of number
It insulate according to line and a plurality of gating line.
In operation S30, (the overlapping region specifically, intersected in a plurality of gating line with multiple data lines on the insulating layer
On) form semiconductor layer.That is, semiconductor source (semiconductor source) be deposited on the insulating layer and by
It is selectively patterned and goes the overlapping region intersected divided by a plurality of gating line is formed with multiple data lines.
At this point it is possible to be formed together equipment semiconductor layer with semiconductor layer in operation S30.That is, semiconductor layer
It can be formed simultaneously by using same mask with equipment semiconductor layer.
A plurality of gating line and multiple data lines are formed in the overlapping region that a plurality of gating line intersects with multiple data lines
Between semiconductor layer can play the role of the distance between the gating line widened in each overlapping region and respective data lines.
Increase the distance between every gating line in a plurality of gating line and every data line in multiple data lines
Semiconductor layer reduces the parasitic capacitance occurred in overlapping region.
In other words, since semiconductor layer increases the distance between a plurality of gating line and multiple data lines in overlapping region,
Therefore the leakage current for flowing to multiple data lines 51 from a plurality of gating line and flowing to a plurality of gating line from multiple data lines is reduced.
When forming equipment semiconductor layer in environment division, semiconductor layer can be formed together with equipment semiconductor layer
In environment division.Thus, semiconductor layer can be readily formed without using individual additional masking.
Next, multiple data lines can be formed on the insulating layer in operation S40.Here, multiple data lines can be with shape
As crossing semiconductor layer and perpendicular to a plurality of gating line.The multiple data lines for crossing the semiconductor layer on insulating layer can lead to
It crosses and selects data line source (data line source) deposition on the insulating layer and on semiconductor layer and by data line source
Property composition and removal and formed.
At this point it is possible to while forming multiple data lines by the data electrode of environment division together with multiple data lines shape
At.
In operation S50, protective layer is formed on a plurality of gating line, multiple data lines or environment division.
It is now described with reference to the drawings the display panel of another embodiment according to the present invention.
Fig. 5 is to show the plan view of the display panel of another embodiment according to the disclosure.
Referring to Fig. 5, other than a plurality of gating line and multiple data lines, according to the display of another embodiment of the disclosure
Panel 200 have with according to embodiment of the present disclosure in figs. 1 to 3 shown in the essentially identical structure of display panel 100
It makes.Therefore, identical appended drawing reference is specified to corresponding component, and for simplicity by the descriptions thereof are omitted.
Display panel 200 according to current embodiment may include forming a plurality of gating line 121 on the substrate 10, absolutely
Edge layer 31, semiconductor layer 41 and multiple data lines 151.
In the display panel 200 according to current embodiment, a plurality of gating line 121 and multiple data lines 151 are formed as
So that the width of gating line 121 and data line 151 is narrower than in non-overlapping region in overlapping region.
It can be during to 151 composition of gating line 121 and data line by the gating line 121 and data in overlapping region
The line width of line 151 and the line width of gating line 121 and data line 151 in non-overlapping region distinguish.Due to overlapping region
In line width reduce, therefore in the display panel 200 according to the current embodiment of the disclosure, what is occurred in overlapping region is posted
Raw capacitor can further decrease.
The description of the disclosure is only exemplary in itself, thus, do not depart from the variation of those of purport of the disclosure
It is also intended in the scope of the present disclosure.These variations should not be considered as deviation spirit and scope of the present disclosure.Thus, this field skill
Art personnel will be understood that, can be carried out in the case where not departing from the spirit and scope limited by appended claims various forms and
Modification in details.
Cross reference to related applications
The South Korea patent application No.10-2018- submitted this application claims on January 26th, 2018 in Korean Intellectual Property Office
0009800 priority, the patent application are fully incorporated in herein by reference.
Claims (6)
1. a kind of display panel, the display panel include:
A plurality of gating line, a plurality of gating line are formed on substrate；
Insulating layer, the insulating layer are formed on a plurality of gating line；And
Multiple data lines, the multiple data lines are formed on the insulating layer to cross a plurality of gating line, so as to cause
Overlapping region is generated, in the overlapping region, the multiple data lines are intersected in the horizontal direction with a plurality of gating line
But be spaced apart in the vertical direction with a plurality of gating line,
Wherein, according to a plurality of gating line and the width of the multiple data lines in the overlapping region than in non-overlapping area
Narrow mode forms a plurality of gating line and the multiple data lines in domain.
2. display panel according to claim 1, the display panel further include:
Environment division, each environment division be arranged in by a plurality of gating line a gating line and the multiple data lines
In the space that limits of a data line in and be connected to the gating line in a plurality of gating line and described more
The data line in data line.
3. display panel according to claim 2, the display panel further include:
Gating line is assisted, the auxiliary gating line extends from the gating line in a plurality of gating line with will be described more
A gating line in gating line is connected to the environment division；And
Auxiliary data line, the auxiliary data line extend from the data line in the multiple data lines with will be described more
The data line in data line is connected to the environment division.
4. display panel according to claim 3, wherein each environment division includes:
Grid, the grid extend from the auxiliary gating line；
Apparatus insulated layer, the apparatus insulated layer cover the top of the grid and are formed integrally as list with the insulating layer
A structure；
Equipment semiconductor layer, the equipment semiconductor layer is in each overlapping region and is formed in the multiple data lines
The data line and a plurality of gating line in a gating line between semiconductor layer be formed together in institute
It states on apparatus insulated layer；And
Data electrode, the data electrode extend on the equipment semiconductor layer from the auxiliary data line.
5. display panel according to claim 4, the display panel further include:
Protective layer, the protective layer cover the multiple data lines, the auxiliary data line and the environment division.
6. a kind of method for manufacturing display panel, method includes the following steps:
A plurality of gating line is formed on substrate；
Insulating layer is formed on a plurality of gating line；And
Multiple data lines are formed as on the insulating layer to cross a plurality of gating line, so as to cause overlapping region is generated,
In the overlapping region, the multiple data lines and a plurality of gating line intersect in the horizontal direction but with it is described a plurality of
Gating line is spaced apart in the vertical direction,
Wherein, when forming a plurality of gating line and the multiple data lines, a plurality of gating line and a plurality of data
The width of line is formed narrower than in non-overlapping region in the overlapping region.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020180009800A KR102054254B1 (en) | 2018-01-26 | 2018-01-26 | Display panel for reducing locked capacitance and manufacturing method |
| KR10-2018-0009800 | 2018-01-26 |
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| Publication Number | Publication Date |
|---|---|
| CN110082973A true CN110082973A (en) | 2019-08-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910068446.0A Pending CN110082973A (en) | 2018-01-26 | 2019-01-24 | The display panel and its manufacturing method that parasitic capacitance reduces |
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| Country | Link |
|---|---|
| KR (1) | KR102054254B1 (en) |
| CN (1) | CN110082973A (en) |
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| CN112185891A (en) * | 2020-09-28 | 2021-01-05 | 成都中电熊猫显示科技有限公司 | Manufacturing method of array substrate, array substrate and display panel |
| WO2021077491A1 (en) * | 2019-10-22 | 2021-04-29 | Tcl华星光电技术有限公司 | Wiring structure of display panel, wiring method of display panel, and display panel |
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| CN114967256A (en) * | 2022-04-13 | 2022-08-30 | 滁州惠科光电科技有限公司 | Array substrate, display panel and display device |
| CN114815421B (en) * | 2022-04-21 | 2024-04-19 | 南京京东方显示技术有限公司 | Array substrate, display panel and display device |
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|---|---|---|---|---|
| WO2021077491A1 (en) * | 2019-10-22 | 2021-04-29 | Tcl华星光电技术有限公司 | Wiring structure of display panel, wiring method of display panel, and display panel |
| CN112185891A (en) * | 2020-09-28 | 2021-01-05 | 成都中电熊猫显示科技有限公司 | Manufacturing method of array substrate, array substrate and display panel |
| CN114967256A (en) * | 2022-04-13 | 2022-08-30 | 滁州惠科光电科技有限公司 | Array substrate, display panel and display device |
| CN114815421A (en) * | 2022-04-21 | 2022-07-29 | 南京京东方显示技术有限公司 | Array substrate, display panel and display device |
| CN114815421B (en) * | 2022-04-21 | 2024-04-19 | 南京京东方显示技术有限公司 | Array substrate, display panel and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR102054254B1 (en) | 2019-12-10 |
| KR20190090961A (en) | 2019-08-05 |
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