CN106782650A - Random address data erasing protection circuit based on SRAM - Google Patents
Random address data erasing protection circuit based on SRAM Download PDFInfo
- Publication number
- CN106782650A CN106782650A CN201710052125.2A CN201710052125A CN106782650A CN 106782650 A CN106782650 A CN 106782650A CN 201710052125 A CN201710052125 A CN 201710052125A CN 106782650 A CN106782650 A CN 106782650A
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- Prior art keywords
- sram
- data
- sequence
- address
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/20—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]
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- Storage Device Security (AREA)
Abstract
The present invention relates to static RAM SRAM, to enable effectively to destroy data when chip is under attack, it is ensured that original cannot be recovered, it is ensured that memory chip data safety.The present invention, random address data erasing protection circuit based on SRAM, including static RAM SRAM, longest linear feedback shift register sequence abbreviation m-sequence, counter is constituted, SRAM pins include writing enable WEN, chip slapper choosing enables CEN, chip output enables OEN, address is input into A, data input D and data output Q, SRAM starts to perform normal function after reset, outer input clk is the clock for destroying circuit, when destroying enable signal and being effective, the counter is started counting up, if detecting destruction enables the signal significant level duration higher than several clock cycle, show that destruction signal is effective.Present invention is mainly applied to manufacturing and designing for static RAM.
Description
Technical field
It is the present invention relates to static RAM SRAM (Static Random Access Memory), i.e., static
The safety storage of random access memory, data during circuit can eliminate SRAM at random when detecting chip and being under attack make
Obtaining data recovery difficulty increases, and belongs to field of information security technology.The random address data based on SRAM are concretely related to wipe
Protection circuit.
Background technology
Since the nineties in 20th century, information technology is developed rapidly at an unprecedented rate, and information industry is vigorously upward, can
Information technology is all be unable to do without with the every field for saying economic society.Into after 21 century, substantial amounts of information Store, propagation and friendship
Stream fully changes our mode of production and life.However, information technology is while developing rapidly, but bring very
Multi information safety problem.Current social development is increasingly dependent on information, and privacy of the information security not only with our individuals is close
Correlation, more to Company Confidential or even national security important.
Memory is widely used in storage key etc., is the important component of security system.Memory includes arbitrary access
Memory, read-only storage and flash memory etc..Among these, SRAM is widely used.SRAM is a kind of with still function
Deposit, it is not necessary to which refresh circuit can just preserve the data of its storage inside.SRAM is unlike in DRAM (dynamic random access memory)
Deposit needs refresh circuit like that, and DRAM wants refresh charge once at regular intervals, and otherwise internal data can disappear, therefore
SRAM has superior performance, and power consumption is smaller.Turn into semiconductor memory due to the low-power consumption of its own and the advantage of high speed
In an indispensable class staple product.SRAM memory is now widely used for data storage, is thus susceptible to turn into and is attacked
Object.
The alarm signal that the function of the circuit realiration designed by the present invention sends when being detection chip under attack, receives
High level represent chip it is under attack need destroy SRAM data, receive low level then represent be not affected by attack.When detection is high
Level just thinks high level effectively more than 128 cycles, not only realizes the influence of elimination burr in detection alarm signal, Er Qiexiao
Ruin circuit.Pseudo random address and pseudo-random data will be produced when detecting chip and being under attack carries out data destroying to SRAM,
Because the address and data that produce have randomness, the difficulty of data recovery is increased.
Pseudo-random sequence is that one kind can predefine and can repeatedly produce and replicate, and with random statistical characteristic
Binary code sequence.In today's society, pseudo-random signal is in communication, navigation, radar and secret communication, communication system performance
Had a wide range of applications in the fields such as measurement.M-sequence is used as the one kind in pseudo-random sequence, extensive application, in the present invention
Random address and random data when destroying data are produced by m-sequence.
Bibliography
1. king can be magnificent, design and realization [J] the BJ Electronic Science ＆ Tech Inst journal of the precious flat .m sequencers of Lee, and 2007,
15(2):58-61.
2. Xu Min resistance against physical attacks safety chip key technology research [D] University Of Tianjin, 2012.
3. the beautiful of Liu Wen are based on attack resistance key technology research [D] the University Of Tianjin of safety storage, 2014.
4.Liu C,Zhao P,Bian K,et al.The detection of physical attacks against
iBeacon transmitters[C]//Ieee/acm,International Symposium on Quality of
Service.2016。
The content of the invention
To overcome the deficiencies in the prior art, the present invention is directed to propose a kind of data destroying circuit for SRAM, by short
The integrality of destruction data file in time so that data can be effectively destroyed when chip is under attack, it is ensured that original without
Method is recovered, it is ensured that memory chip data safety.The technical solution adopted by the present invention is that the random address data based on SRAM are wiped
Except protection circuit, including static RAM SRAM, longest linear feedback shift register sequence abbreviation m-sequence, meter
Number device is constituted, and SRAM pins enable CEN, chip output enable OEN, address input A, data including writing enable WEN, chip slapper choosing
Input D and data output Q, SRAM starts to perform normal function after reset, and outer input clk is the clock for destroying circuit, works as pin
Ruin enable signal it is effective when, the counter is started counting up, if detect destruction enable the signal significant level duration it is high
In several clock cycle, show to destroy signal effectively, the interference of burr is prevented with this, now described CEN, OEN, WEN become
It is low level to guarantee to carry out SRAM write operation, and address signal and data-signal produce address according to m-sequence, work as institute
Meeting output signal represents that destruction is completed after the completion of having address all to destroy.
M-sequence is the cycle a kind of sequence most long produced by the shift register with linear feedback, and D is shifted using n grade
It is 2 that trigger produces the most long period that is producedn- 1, all it is afterwards previous stage per the input of one-level trigger in addition to the first order
The input of output, the i.e. second level is the output of the first order, and by that analogy, and first order input is arbitrarily selected in being exported by every one-level
An XOR is selected to constitute.
In one instantiation, a width of 13 of SRAM address bits, it is necessary to 13 d type flip flops produce the OPADDs of m-sequence,
Simultaneously in order to ensure that, by all address searchings, the input of first order register is exported by the nine, the ten, the 12nd, the tenth three-level
Q9, Q10, Q12, Q13 XOR are formed, this 13bit number of Q1 to Q13 as output 13bit addresses, because SRAM data address is
32bit, so needing 32 d type flip flops to produce the output data of m-sequence.
The features of the present invention and beneficial effect are：
Data quick selective erasing process of the present invention suitable for SRAM memory when under attack, and with preventing burr
The function of interference, to reach the integrality of random disruptions data, prevents data from effectively being recovered, so as to ensure the number of memory
According to safety.
Brief description of the drawings：
Fig. 1 integrated circuit figures.
Fig. 2 SRAM circuit figures.
Fig. 3 m-sequence schematic diagrams.
Fig. 4 circuit simulation figures.
Fig. 5 circuit simulation figures.
Fig. 6 SRAM input data address change figures.
Specific embodiment
Circuit designed by the present invention is made up of automatic detection module and information destroying module two parts, specific structure chart
Such as the alarm signal that Fig. 1, the One function of the circuit realiration designed by the present invention send when being detection chip under attack, make
Circuit can be destroyed.When electric circuit inspection is destroyed to enable signal, show that chip is under attack, hair occur in order to prevent enable signal
Pierce and open destruction operating mistake, detect after enable signal uprises, destroy circuit and start counting up, when writing for 128 week all over
Think strictly to carry out destruction operation after phase, circuit starts second function and produces random address and random data afterwards
To destroy data in SRAM.
SRAM used in the present invention as shown in Fig. 2 its size be 32KB, bit wide is 32bit.Single port synchronization used
SRAM is to optimize by high-performance.Memory make use of 0.18 micrometre CMOS process of SMIC.Storage array is by six
The full static circuit composition of transistor unit.Its pin includes that writing enable (WEN), chip slapper choosing enables CEN, chip output enable
OEN, address input (A), data input (D) and data output (Q).All synchronism outputs are latched by the rising edge of clock signal.
When CEN is low and WEN is high, memory carries out read operation.When CEN and WEN are low, D will be written into memory, while
It appears in output Q.When CEN is high, memory is cancelled and chooses, and is forced into low-power consumption standby pattern.The data of storage
It is fully retained, but is prohibited for digital independent or write-in, existing data output is continued to press on its last value.When
The data of the value of Q outputs are effective during OEN virtual values (low level).When OEN is invalid (high level), the value of Q outputs
Data are without driving (configuration Z high).
From the foregoing, it will be observed that starting that CEN, WEN and OEN of SRAM are changed into low level when destroying, at this moment could start to write behaviour
Make, and memory input address and write-in data generate pseudo random number using m-sequence.M-sequence is longest linear feedback shift
The abbreviation of register series, it is the cycle a kind of sequence most long produced by the shift register with linear feedback.M-sequence can
It is (2 to produce the issuable most long periods of using n grades of displacement d type flip flopn-1).Its principle is as shown in Figure 3, except the first order
All it is afterwards the output of previous stage per the input of one-level trigger beyond D1, i.e. the input of D2 is the output Q1 of D1, by that analogy,
And first D1 input is made up of any options XOR in every one-level output Q.
Due to a width of 13 of SRAM address bits used by the present invention, so needing 13 d type flip flops to produce the outputs ground of m-sequence
Location, while in order to ensure that, by all address searchings, the input of first order register is defeated by the nine, the ten, the 12nd, the tenth three-level
Go out Q9, Q10, Q12, Q13 XOR to be formed, this 13bit number of Q1 to Q13 is used as the 13bit addresses for exporting in figure 3.Due to SRAM
Data address is 32bit, so needing 32 d type flip flops to produce the output data of m-sequence.
Destroying module rst signals is used to reset, and starts to perform normal function after reset, and clk is the clock for destroying circuit.
The destruction for destroying signal detection input enables signal, and after enabling signal and uprising, the counter destroyed in circuit is started counting up,
If detecting erase_en high level lasting times higher than 128 clock cycle, show to destroy signal effectively, prevented with this
The interference of burr, CEN, OEN, WEN for now destroying circuit is changed into low level to guarantee to carry out SRAM write operation, and ground
Location signal addr [12：0] and data-signal data [31：0] according to m-sequence produce address, when destroy electric circuit inspection to will own
Address can uprise erase_end signals after the completion of all destroying, and represent and destroy completion.
As shown in Figure 4 and Figure 5, enable signal is too short in Fig. 4 for circuit simulation figure, so destroying circuit will not enter marketing
Ruin, it can be seen that SRAM addresses and data do not change.Signal long enough is enabled in Fig. 5, circuit is destroyed and is started to destroy, can be with
See the address input end of SRAM all in change.SRAM input specific address data variations are as shown in fig. 6, Fig. 6 is Fig. 5 destructions
Partial enlarged drawing when just starting is operated, as can be seen from the figure it meets m-sequence.In data erasing, by randomly
Location carries out the manifolding of random data so that data cannot completely be recovered in SRAM, reaches the effect for ensureing memory data safety.
The present invention from information security, devise it is a receive chip it is under attack need destroy SRAM memory
The circuit of random address data erasing can be carried out during data to SRAM.The circuit is received to destroy and enables signal, is destroyed and is enabled signal
M-sequence is started with after continuous and effective certain hour and produces random address and data destroying SRAM data.Protection model of the invention
Enclose and be not limited with above-mentioned implementation method, the equivalent modification that those of ordinary skill in the art are made according to disclosed content
Or change, should all include protection domain.
Claims (3)
1. a kind of random address data based on SRAM wipe protection circuit, it is characterized in that, including static RAM
SRAM, longest linear feedback shift register sequence abbreviation m-sequence, counter are constituted, and SRAM pins include writing enable WEN, core
The choosing of piece piece enables CEN, chip output and enables OEN, address input A, data input D and data output Q, and SRAM starts after reset
Normal function is performed, outer input clk is the clock for destroying circuit, when destroying enable signal and being effective, the counter starts meter
Number, if detecting destruction enables the signal significant level duration higher than several clock cycle, shows to destroy signal effectively,
The interference of burr is prevented with this, now described CEN, OEN, WEN are changed into low level to guarantee to carry out SRAM write operation, and
And address signal and data-signal produce address according to m-sequence, meeting output signal represents pin after the completion of all addresses are all destroyed
Ruin completion.
2. the random address data erasing protection circuit based on SRAM as claimed in claim 1, it is characterized in that, m-sequence be by
A kind of cycle that shift register with linear feedback is produced sequence most long, generations are produced using n grade displacement d type flip flop
Most long period is 2n- 1, all it is afterwards the output of previous stage, the i.e. second level per the input of one-level trigger in addition to the first order
The output for the first order is input into, by that analogy, and arbitrarily options XOR is constituted during first order input is exported by every one-level.
3. the random address data based on SRAM as claimed in claim 1 wipe protection circuit, it is characterized in that, one is specific real
In example, a width of 13 of SRAM address bits, it is necessary to 13 d type flip flops produce the OPADDs of m-sequence, while in order to ensure will be all
Address searching, the input of first order register exports Q9, Q10, Q12, Q13 XOR by the nine, the ten, the 12nd, the tenth three-level
Formed, this 13bit number of Q1 to Q13 as output 13bit addresses, due to SRAM data address be 32bit, so need 32
D type flip flop produces the output data of m-sequence.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710052125.2A CN106782650A (en) | 2017-01-20 | 2017-01-20 | Random address data erasing protection circuit based on SRAM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710052125.2A CN106782650A (en) | 2017-01-20 | 2017-01-20 | Random address data erasing protection circuit based on SRAM |
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| Publication Number | Publication Date |
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| CN106782650A true CN106782650A (en) | 2017-05-31 |
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| CN201710052125.2A Pending CN106782650A (en) | 2017-01-20 | 2017-01-20 | Random address data erasing protection circuit based on SRAM |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001147860A (en) * | 1999-10-01 | 2001-05-29 | Giesecke & Devrient Gmbh | Method for protecting data memory |
| CN1963832A (en) * | 2006-12-07 | 2007-05-16 | 上海普芯达电子有限公司 | Data processing apparatus capable of preventing inbreak and embedded system |
| CN101036155A (en) * | 2004-04-30 | 2007-09-12 | 迈克纳斯公司 | Chip with a power supply device |
| CN101183433A (en) * | 2007-11-19 | 2008-05-21 | 华为技术有限公司 | Data protection method and client identification module card |
| CN201654762U (en) * | 2009-11-30 | 2010-11-24 | 上海第二工业大学 | Pseudorandom code sequencer |
-
2017
- 2017-01-20 CN CN201710052125.2A patent/CN106782650A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001147860A (en) * | 1999-10-01 | 2001-05-29 | Giesecke & Devrient Gmbh | Method for protecting data memory |
| US7039815B1 (en) * | 1999-10-01 | 2006-05-02 | Giesecke & Devrient Gmbh | Method for protecting a data memory |
| CN101036155A (en) * | 2004-04-30 | 2007-09-12 | 迈克纳斯公司 | Chip with a power supply device |
| CN1963832A (en) * | 2006-12-07 | 2007-05-16 | 上海普芯达电子有限公司 | Data processing apparatus capable of preventing inbreak and embedded system |
| CN101183433A (en) * | 2007-11-19 | 2008-05-21 | 华为技术有限公司 | Data protection method and client identification module card |
| CN201654762U (en) * | 2009-11-30 | 2010-11-24 | 上海第二工业大学 | Pseudorandom code sequencer |
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Application publication date: 20170531 |