CN106782638A - Word line decoding circuit and memory - Google Patents
Word line decoding circuit and memory Download PDFInfo
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- CN106782638A CN106782638A CN201710011838.4A CN201710011838A CN106782638A CN 106782638 A CN106782638 A CN 106782638A CN 201710011838 A CN201710011838 A CN 201710011838A CN 106782638 A CN106782638 A CN 106782638A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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Abstract
A kind of word line decoding circuit and memory, word line decoding circuit include：Voltage detecting circuit, is suitable to compare erasing voltage with threshold value to export detection voltage；Decoding bias-voltage generating circuit, is suitable to produce decoding bias voltage according to detection voltage；Wordline bias-voltage generating circuit, is suitable to produce wordline bias voltage according to detection voltage；When erasing voltage is more than or equal to threshold value, decoding bias voltage and wordline bias voltage are pulled up to the first supply voltage, when erasing voltage is less than threshold value, decoding bias voltage and wordline bias voltage are pulled down to ground wire voltage, and the first supply voltage is more than ground wire voltage；Decoding circuit, is suitable to receive erasing voltage and decoding bias voltage, and row decoding is entered to data-signal to export decoding result；Selection circuit, is suitable to, according to decoding result, one of them be selected as word-line signal in erasing voltage and wordline bias voltage.The present invention program has saved power consumption while decoding accuracy is ensured.
Description
Technical field
The present invention relates to reservoir designs field, more particularly to a kind of word line decoding circuit and memory.
Background technology
Memory (Memory) is the memory device in computer system, for storage program and data.In general, depositing
Reservoir can be divided into random access memory (Random Access Memory, RAM), read-only storage (Read-Only
Memory, ROM) and can arbitrarily read and write and can the constant mixing memory of data in holding equipment after a loss of power.Wherein, mixing is deposited
Reservoir can include such as EEPROM (Electrically Erasable Programmable Read-
Only Memory, EEPROM), nonvolatile random access memory (Non-Volatile Random Access Memory,
) and flash memory (Flash) etc. NVRAM.The characteristics of Flash is wiped because it is quick, receives and is widely applied.
The reading and writing of memory, erasing are several storage operations the most conventional.Erasing operation is being carried out to memory
When, it is necessary to design word line decoding circuit, according to data-signal (such as address signal) generation decoding result indicating in memory
Which or which memory cell wiped, and erasing voltage is transmitted to the wordline of the memory cell being wiped free of,
Namely cause that the amplitude that the memory cell being wiped free of receives word-line signal is equal to the erasing voltage.
General erasing voltage is up to about 12V, and the metal-oxide-semiconductor in memory chip needs to bear from 12V to ground wire voltage 0V
High Pressure Difference, this breakdown voltage to metal-oxide-semiconductor has certain challenge, when the breakdown voltage of metal-oxide-semiconductor is relatively low, bears High Pressure Difference
Will cause that the leakage current of metal-oxide-semiconductor is larger, and then influence metal-oxide-semiconductor performance.Therefore, it is general in the word line decoding circuit of prior art
The supply voltage higher than ground wire voltage is chosen, such as 2.5V, substitution ground wire voltage is powered for word line decoding circuit, can cause word
The pressure difference reduction that metal-oxide-semiconductor in line decoding circuit bears.
However, while above improvement is made, prior art is difficult to take into account the power consumption of word line decoding circuit and decoding is accurate
True property.
The content of the invention
Present invention solves the technical problem that when being that metal-oxide-semiconductor bears pressure difference inside reduction word line decoding circuit, how to take into account
The decoding accuracy of memory word line decoding and low-power consumption.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of word line decoding circuit, including：Voltage detecting electricity
Road, is suitable to compare erasing voltage with threshold value to export detection voltage；Decoding bias-voltage generating circuit, is suitable to according to the detection
Voltage produces decoding bias voltage, and when the erasing voltage is more than or equal to the threshold value, the decoding bias voltage is pulled up
To the first supply voltage, when the erasing voltage is less than the threshold value, the decoding bias voltage is pulled down to ground wire voltage,
First supply voltage is more than the ground wire voltage；Wordline bias-voltage generating circuit, is suitable to be produced according to the detection voltage
New word line bias voltage, when the erasing voltage is more than or equal to the threshold value, the wordline bias voltage is pulled to described
First supply voltage, when the erasing voltage is less than the threshold value, the wordline bias voltage is pulled down to the ground wire electricity
Pressure；Decoding circuit, is suitable to receive the erasing voltage and decoding bias voltage, and row decoding is entered to data-signal to export decoding knot
Really；Selection circuit, is suitable to according to the decoding result, and one of work is selected in the erasing voltage and wordline bias voltage
It is word-line signal.
Alternatively, the decoding bias-voltage generating circuit is better than the word to the pull-down capability of the decoding bias voltage
Line bias voltage produces the pull-down capability to the wordline bias voltage.
Alternatively, the decoding bias-voltage generating circuit includes：First phase inverter, its input receives the detection electricity
Pressure, its output end exports the decoding bias voltage, and its first power end receives first supply voltage, its second source end
Receive the ground wire voltage.
Alternatively, the wordline bias-voltage generating circuit includes：Second phase inverter, its input receives the detection electricity
Pressure, its output end exports the wordline bias voltage, and its first power end receives first supply voltage, its second source end
Coupling pull-down circuit；The pull-down circuit, its control end receives bias voltage, when the erasing voltage is less than the threshold value,
It is suitable to produce the drop-down wordline bias voltage to the electric current of the ground wire voltage according to the bias voltage.
Alternatively, second phase inverter includes：First PMOS, its source electrode receives first supply voltage；First
NMOS tube, its grid couples the grid of first PMOS and receives the detection voltage, its drain electrode coupling described first
The drain electrode of PMOS simultaneously exports the wordline bias voltage, and its source electrode couples the pull-down circuit；The pull-down circuit includes：The
Two NMOS tubes, its grid receives the bias voltage, the source electrode of its drain electrode coupling first NMOS tube, its source ground.
Alternatively, the data-signal includes the first data-signal and the second data-signal；When first data-signal
It is the first logic level, when second data-signal is the second logic level different from the first logic level, the selection
Erasing voltage described in circuit output is used as the word-line signal；When first data-signal is second logic level, institute
When stating the second data-signal for first logic level, the selection circuit exports the wordline bias voltage as the word
Line signal.
Alternatively, the decoding circuit includes：First switch circuit, its control end receives first data-signal；The
Two on-off circuits, its control end receives second data-signal, and its first end couples the first end of the first switch circuit
And receive the decoding bias voltage；Latch cicuit, its first power end receives the erasing voltage, and its second source end receives
First supply voltage, with the first latch point and the second latch point, first latch point couples the first switch electricity
Second end on road, second latch point couples the second end of the second switch circuit, first latch point and the second lock
The logic level deposited a little indicates the decoding result.
Alternatively, the first switch circuit includes：3rd NMOS tube, its grid couples the control of the first switch circuit
End processed, its source electrode couples the first end of the first switch circuit, the second end of its drain electrode coupling first switch circuit；Institute
Stating second switch circuit includes：4th NMOS tube, its grid couples the control end of the second switch circuit, its source electrode coupling institute
The first end of second switch circuit is stated, the second end of its drain electrode coupling second switch circuit.
Alternatively, the word line decoding circuit also includes：Level adjusting circuit, is suitable to enter line level to the detection voltage
Conversion.
In order to solve the above technical problems, the embodiment of the present invention also provides a kind of memory, including above-described wordline is translated
Code circuit.
Alternatively, the memory is flash memory.
Compared with prior art, the technical scheme of the embodiment of the present invention has the advantages that：
The embodiment of the present invention provides a kind of word line decoding circuit, can include：Voltage detecting circuit, decoding bias voltage are produced
Raw circuit, wordline bias-voltage generating circuit, decoding circuit and selection circuit.Wherein, the voltage detecting circuit is suitable to compare
Erasing voltage and threshold value are exporting detection voltage；The decoding bias-voltage generating circuit is suitable to be produced according to the detection voltage
Decoding bias voltage, when the erasing voltage is more than or equal to the threshold value, the decoding bias voltage is pulled to the first electricity
Source voltage, when the erasing voltage is less than the threshold value, the decoding bias voltage is pulled down to ground wire voltage, described first
Supply voltage is more than the ground wire voltage；The wordline bias-voltage generating circuit is suitable to produce wordline according to the detection voltage
Bias voltage, when the erasing voltage is more than or equal to the threshold value, the wordline bias voltage is pulled to first electricity
Source voltage, when the erasing voltage is less than the threshold value, the wordline bias voltage is pulled down to the ground wire voltage；It is described
Decoding circuit is suitable to receive the erasing voltage and decoding bias voltage, and row decoding is entered to data-signal to export decoding result；
The selection circuit is suitable to according to the decoding result, and one of work is selected in the erasing voltage and wordline bias voltage
It is word-line signal.In the present embodiment, different electricity are respectively provided with to the bias voltage required for decoding circuit and selection circuit
Pressure produces circuit, during causing to need to carry out drop-down to the bias voltage required for the two, the drop-down of the two can be adjusted flexibly
Ability so that ensure that the low power consumption characteristic of circuit is possibly realized while decoding accuracy is ensured.Can for example set described
Decoding bias-voltage generating circuit is better than the wordline bias-voltage generating circuit to the pull-down capability of the decoding bias voltage
To the pull-down capability of the wordline bias voltage.
Furthermore, the wordline bias-voltage generating circuit includes：Second phase inverter and pull-down circuit.Wherein, institute
The control end for stating pull-down circuit receives bias voltage, when the erasing voltage is less than the threshold value, is suitable to according to the biasing
Voltage produces the drop-down wordline bias voltage to the electric current of the ground wire voltage, and the pull-down capability of the pull-down circuit is controllable
So that the power consumption of embodiment of the present invention word line decoding circuit is flexibly controllable, for example, can be by reducing the pull-down circuit
Pull-down capability is ensureing the low-power consumption of the word line decoding circuit.
Brief description of the drawings
Fig. 1 is a kind of schematic block diagram of word line decoding circuit.
Fig. 2 is a kind of schematic block diagram of word line decoding circuit of the embodiment of the present invention.
Fig. 3 is the schematic block diagram of embodiment of the present invention another kind word line decoding circuit.
Fig. 4 is the schematic block diagram of another word line decoding circuit of the embodiment of the present invention.
Specific embodiment
As described in the background section, in the prior art, in order to reduce the pressure that the metal-oxide-semiconductor in word line decoding circuit bears
Difference, the supply voltage of ground wire voltage is set above by one of supply voltage of word line decoding circuit, to replace ground wire electricity
Pressure.However, while above improvement is made, prior art is difficult to take into account the power consumption of word line decoding circuit and decoding accuracy.
Present inventor is analyzed a kind of word line decoding circuit.As shown in figure 1, a kind of word line decoding circuit
100 can include：Voltage detecting circuit 101, bias-voltage generating circuit 102, decoding circuit 103 and selection circuit 104.
In order that the pressure difference that bears of metal-oxide-semiconductor in the decoding circuit 103 and selection circuit 104 is lowered, wordline is translated
Code circuit 100 is provided with the bias-voltage generating circuit 102.When the voltage detecting circuit 101 is by comparing erasing voltage
Vee and the relation of threshold value, export detection voltage Vdet, for example, when erasing voltage Vee is detected more than or equal to 5V, the inspection
It can be logic low to survey voltage Vdet, and when less than 5V, the detection voltage Vdet upsets are logic high.It is described inclined
Voltage generation circuit 102 is put to be suitable to produce bias voltage Bias_Dec, the bias voltage according to the detection voltage Vdet
Bias_Dec is used in the decoding circuit 103 and selection circuit 104.The decoding circuit 103 is carried out to data-signal a and b
To export decoding result, specifically, the decoding circuit 103 can include latch cicuit 1031 and first switch pipe for decoding
N1 and second switch pipe N2.The decoding result can be expressed as selection signal SEL and SELb.The selection circuit 104 is suitable to
According to the decoding result, namely selection signal SEL and SELb, in the erasing voltage Vee and bias voltage Bias_Dec
One of them is selected as word-line signal.Wherein, the bias voltage Bias_Dec acts on the He of the decoding circuit 103 simultaneously
Selection circuit 104, the level for advantageously allowing the selection signal SEL and SELb of the generation of the decoding circuit 103 can be very
It is applied to the selection circuit 104 well.
When the erasing voltage Vee (being greater than being equal to the threshold value) higher, the bias voltage Bias_Dec quilts
It is pulled to the first supply voltage VSS, the first supply voltage VSS and is more than the ground wire voltage, such as 2.5V is described to protect
Metal-oxide-semiconductor in decoding circuit 103 and selection circuit 104；And it (is, for example, less than institute to work as the controlled quick reductions of the erasing voltage Vee
State threshold value) when, in order to ensure the decoding accuracy of the decoding circuit 103, it is necessary to so that the bias voltage Bias_Dec quilts
It is drop-down, zero potential is preferably pulled down to, therefore, the bias-voltage generating circuit 102 causes the bias voltage Bias_Dec
It is pulled down to ground wire voltage.
However, it is contemplated that when the erasing voltage Vee is in controlled decline, decrease speed is very fast, in order to ensure that decoding is accurate
True property, needs stronger pull-down current to complete quick pull-down when the bias voltage Bias_Dec is pulled down, and simultaneously, institute
State bias voltage Bias_Dec and also act on the selection circuit 104, to the pull-down current of the bias voltage Bias_Dec compared with
The big high power consumption for meaning word line decoding circuit 100.Therefore, word line decoding circuit 100 bears pressure difference in the internal metal-oxide-semiconductor of reduction
When, it is impossible to take into account the decoding accuracy and low power consumption characteristic of memory word line decoding.
For techniques discussed above problem, the embodiment of the present invention proposes a kind of word line decoding circuit, is reducing internal MOS
When pipe bears pressure difference, different voltage generation circuits are respectively provided with to the bias voltage required for decoding circuit and selection circuit,
During causing to need to carry out drop-down to the bias voltage required for the two, the pull-down capability of the two can be adjusted flexibly so that
Ensure to ensure that the low power consumption characteristic of circuit is possibly realized while decoding accuracy.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, below in conjunction with the accompanying drawings to this
The specific embodiment of invention is described in detail.
Fig. 2 is a kind of schematic block diagram of word line decoding circuit of the embodiment of the present invention.
As shown in Fig. 2 the embodiment of the present invention provides a kind of word line decoding circuit 200, the word line decoding circuit 200 can be with
Including：Voltage detecting circuit 201, decoding bias-voltage generating circuit 202, wordline bias-voltage generating circuit 203, decoding circuit
204 and selection circuit 205.
Wherein, the voltage detecting circuit 201 is suitable to compare erasing voltage Vee with threshold value to export detection voltage Vdet.
In general, the erasing voltage Vee is at least 10 to 12V, the threshold value can be 5V；The detection voltage Vdet can be
Digital logic signal, is made a distinction with digital high or low level, and its level magnitudes depends on the voltage detecting circuit
201 supply voltage.
The decoding bias-voltage generating circuit 202 is suitable to produce decoding bias voltage according to the detection voltage Vdet
DECO_Bias, when the erasing voltage Vee is more than or equal to the threshold value, the decoding bias voltage DECO_Bias is pulled up
To the first supply voltage VSS, when the erasing voltage Vee is less than the threshold value, the decoding bias voltage DECO_Bias quilts
Ground wire voltage is pulled down to, the first supply voltage VSS is more than the ground wire voltage, for example, can be 2.5V.
The wordline bias-voltage generating circuit 203 is suitable to produce wordline bias voltage according to the detection voltage Vdet
WL_Bias, when the erasing voltage Vee is more than or equal to the threshold value, the wordline bias voltage WL_Bias is pulled to institute
The first supply voltage VSS is stated, when the erasing voltage Vee is less than the threshold value, the wordline bias voltage WL_Bias is by under
It is pulled to the ground wire voltage.
The decoding circuit 204 is suitable to receive the erasing voltage Vee and decoding bias voltage DECO_Bias, to data
Signal AData enters row decoding to export decoding result DEC.Wherein, the erasing voltage Vee and decoding bias voltage DECO_
Bias can be respectively as supply voltage for the decoding circuit 204 is powered.
The selection circuit 205 is suitable to according to the decoding result DEC, in the erasing voltage Vee and wordline biased electrical
One of them is selected as word-line signal WL in pressure WL_Bias.When the decoding result DEC indicates to receive the word-line signal WL
The data that are stored of memory cell when should be wiped free of, the amplitude of the word-line signal WL is equal to the erasing voltage Vee,
Such as 12V；The data for indicating the memory cell for receiving the word-line signal WL to be stored as the decoding result DEC should not be by
During erasing, the amplitude of the word-line signal WL is equal to the wordline bias voltage WL_Bias, such as 2.5V.
In the present embodiment, due to the first supply voltage VSS be more than the ground wire voltage, such as 2.5V, now, when
When the erasing voltage Vee is more than or equal to the threshold value, the decoding bias voltage DECO_Bias and the wordline bias voltage
WL_Bias is pulled up to 2.5V, if the erasing voltage Vee is 12V, now, the decoding circuit 204 and selection circuit
The maximum differential pressure that metal-oxide-semiconductor inside 205 is born is 9.5V, and the maximum differential pressure born compared to metal-oxide-semiconductor in the prior art is
For the erasing voltage Vee to the pressure difference 12V of ground wire voltage, significantly reduce device bears pressure.Meanwhile, for producing
The decoding bias-voltage generating circuit 202 of the decoding bias voltage DECO_Bias and for producing the wordline bias voltage
The voltage swing variation tendency one that the wordline bias-voltage generating circuit 203 of WL_Bias is exported according to the erasing voltage Vee
Cause, can well meet the level compatibility of the decoding circuit 204 and the decoding result DEC of selection circuit 205 pairs.
Meanwhile, different voltages are respectively provided with to the bias voltage required for decoding circuit 204 and selection circuit 205 and are produced
Circuit, during causing to need to carry out drop-down to the bias voltage required for the two, can be adjusted flexibly the pull-down capability of the two, make
Obtain and ensure that the low power consumption characteristic of circuit is possibly realized while decoding accuracy is ensured.In specific implementation, for example, can set
The pull-down capability for putting the decoding bias-voltage generating circuit 202 pairs decoding bias voltage DECO_Bias is better than the word
The pull-down capability of the wordline bias voltage WL_Bias of line bias-voltage generating circuit 203 pairs.
Fig. 3 is the schematic block diagram of embodiment of the present invention another kind word line decoding circuit 200.The He of complex chart 2 below
Fig. 3 is described in detail to the specific embodiment of the word line decoding circuit 200.
In specific implementation, the decoding bias-voltage generating circuit 202 can include：First phase inverter (is not marked in figure
Show), its input receives the detection voltage Vdet, and its output end exports the decoding bias voltage DECO_Bias, and it first
Power end receives the first supply voltage VSS, and its second source end receives the ground wire voltage.
In specific implementation, the wordline bias-voltage generating circuit 203 can include：Second phase inverter (is not marked in figure
Show) and pull-down circuit (not indicated in figure).
Wherein, the input of second phase inverter receives the detection voltage Vdet, the output of second phase inverter
The end output wordline bias voltage WL_Bias, the first power end of second phase inverter receives first supply voltage
VSS, the second source end coupling pull-down circuit of second phase inverter.
The control end of the pull-down circuit receives bias voltage, when the erasing voltage Vee is less than the threshold value, is suitable to
The drop-down wordline bias voltage WL_Bias to the electric current of the ground wire voltage is produced according to the bias voltage Bias.
In specific implementation, second phase inverter can include：First PMOS P1, its source electrode receives first electricity
Source voltage VSS；First NMOS tube N1, its grid couples the grid of the first PMOS P1 and receives the detection voltage
Vdet, the drain electrode of its drain electrode coupling the first PMOS P1 simultaneously exports the wordline bias voltage WL_Bias, the coupling of its source electrode
The pull-down circuit.
In specific implementation, the pull-down circuit can include：Second NMOS tube N2, its grid receives the bias voltage
Bias, the source electrode of its drain electrode coupling the first NMOS tube N1, its source ground.
It should be noted that the decoding bias-voltage generating circuit 202 and wordline bias-voltage generating circuit 203 can be with
Realized using phase inverter, but not limited to this, other voltage selecting circuits, such as switch switching circuit etc. can also be used, this
Place no longer illustrates one by one.
It should be noted that in specific implementation, first phase inverter can include the second PMOS P2 shown in Fig. 3
With the 5th NMOS tube N5.Because the circuit structure of phase inverter is well-known to those skilled in the art, therefore, herein not to described
The annexation of the second PMOS P2 and the 5th NMOS tube N5 launches description.
Furthermore, in the wordline bias-voltage generating circuit 203, the control end of the pull-down circuit receives inclined
Put voltage so that the pull-down capability of the pull-down circuit be it is controllable, in a particular application, can be by reducing the drop-down electricity
The pull-down capability on road is ensureing the low-power consumption of the word line decoding circuit 200；Simultaneously can be by adjusting first phase inverter
In NMOS tube size improving the decoding bias-voltage generating circuit 202 pairs decoding bias voltage DECO_Bias
Pull-down capability, to ensure the decoding accuracy of the decoding circuit 204.
In specific implementation, the data-signal AData can include the first data-signal a and the second data-signal b；Institute
It can be address signal to state the first data-signal a and the second data-signal b.
For example, when the first data-signal a is the first logic level (such as logic high), second data-signal
When b is the second logic level (such as logic low) different from the first logic level, the selection circuit 205 exports the wiping
Except voltage Vee is used as the word-line signal WL.
When the first data-signal a is second logic level (such as logic low), the second data-signal b
During for first logic level (such as logic high), the selection circuit 205 exports the wordline bias voltage WL_Bias
As the word-line signal WL.
In specific implementation, the decoding circuit 204 can include：First switch circuit (not indicated in figure), second open
Powered-down road (not indicated in figure) and latch cicuit 2041.
Wherein, the control end of the first switch circuit receives the first data-signal a.
The control end of the second switch circuit receives the second data-signal b, the first of the second switch circuit
The first end of the end coupling first switch circuit simultaneously receives the decoding bias voltage DECO_Bias.
First power end of the latch cicuit 2041 receives the erasing voltage Vee, and the of the latch cicuit 2041
Two power ends receive the first supply voltage VSS, with the first latch point (not indicated in figure) and the second latch point (in figure not
Sign), first latch point couples the second end of the first switch circuit, and the second latch point coupling described second is opened
The logic level of second end on powered-down road, first latch point and the second latch point indicates the decoding result DEC.For example,
The decoding result DEC can be first choice signal SEL anti-phase each other and the second selection signal SELb.
In specific implementation, the first switch circuit can include：3rd NMOS tube N3, its grid coupling described first
The control end of on-off circuit, its source electrode couples the first end of the first switch circuit, its drain electrode coupling first switch electricity
Second end on road.
In specific implementation, the second switch circuit can include：4th NMOS tube N4, its grid coupling described second
The control end of on-off circuit, its source electrode couples the first end of the second switch circuit, its drain electrode coupling second switch electricity
Second end on road.
In the case that the decoding bias voltage DECO_Bias is pulled down to ground wire voltage, when first data letter
Number a is logic high, when the second data-signal b is logic low, the first switch unit conducting, described second
Switch element is turned off, and in the presence of the latch cicuit 2041, the first choice signal SEL is logic high, second
Selection signal SELb is logic low.The selection circuit 205 receives first choice signal SEL and the second selection signal
SELb, and the erasing voltage Vee is exported as the word-line signal WL.When the first data-signal a is logic low,
When the second data-signal b is logic high, the first switch unit shut-off, the second switch unit conducting,
In the presence of the latch cicuit 2041, the first choice signal SEL is logic low, and the second selection signal SELb is to patrol
Collect high level.The selection circuit 205 receives first choice signal SEL and the second selection signal SELb, and exports the wordline
Bias voltage WL_Bias is used as the word-line signal WL.When the decoding bias voltage DECO_Bias is pulled to described first
During supply voltage VSS, the decoding circuit 204 stops decoding.
It should be noted that the selection circuit 205 can be entered using selection circuit well-known to those skilled in the art
Row is implemented, not reinflated citing herein.
Fig. 4 is the schematic block diagram of another word line decoding circuit of the embodiment of the present invention.
As shown in figure 4, in another specific embodiment of the invention, word line decoding circuit 300 can include：Voltage detecting
Circuit 201, decoding bias-voltage generating circuit 202, wordline bias-voltage generating circuit 203, decoding circuit 204, selection circuit
205 and level adjusting circuit 206.
Wherein, the voltage detecting circuit 201, decoding bias-voltage generating circuit 202, wordline bias-voltage generating circuit
203rd, the more information of decoding circuit 204 and selection circuit 205 refer to the associated description of above example, no longer go to live in the household of one's in-laws on getting married herein
State.
The level adjusting circuit 206 is suitable to carry out level conversion to the detection voltage Vdet, can be by institute with generation
State the detection after the adjustment recognized described in wordline bias-voltage generating circuit 203 and the decoding bias-voltage generating circuit 202
Voltage VdetAdj.For example, the supply voltage of the voltage detecting circuit 201 is 1.5V and 0V, then, the detection voltage
Vdet changes between 1.5V and 0V, and when first supply voltage is 2.5V, then, the level adjusting circuit 206
Need to be adjusted to 2.5V with adaptive circuit needs by 1.5V to the logic high of the detection voltage Vdet.
It should be noted that " logic high " herein refers to being identified as the level model of data signal " 1 "
Enclose, " logic low " refers to being identified as the level range of data signal " 0 ", the two is relative concept, and its is specific
Level range is simultaneously not particularly limited.
The embodiment of the present invention is also disclosed a kind of memory, including above-described word line decoding circuit 200 or word line decoding
Circuit 300.
In specific implementation, the memory can be flash memory, but not limited to this, the memory can also be
Other memories such as EEPROM, NVRAM.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (11)
1. a kind of word line decoding circuit, it is characterised in that including：
Voltage detecting circuit, is suitable to compare erasing voltage with threshold value to export detection voltage；
Decoding bias-voltage generating circuit, is suitable to produce decoding bias voltage according to the detection voltage, when the erasing voltage
During more than or equal to the threshold value, the decoding bias voltage is pulled to the first supply voltage, when the erasing voltage is less than institute
When stating threshold value, the decoding bias voltage is pulled down to ground wire voltage, and first supply voltage is more than the ground wire voltage；
Wordline bias-voltage generating circuit, is suitable to produce wordline bias voltage according to the detection voltage, when the erasing voltage
During more than or equal to the threshold value, the wordline bias voltage is pulled to first supply voltage, when the erasing voltage is small
When the threshold value, the wordline bias voltage is pulled down to the ground wire voltage；
Decoding circuit, is suitable to receive the erasing voltage and decoding bias voltage, and row decoding is entered to data-signal to export decoding
As a result；
Selection circuit, is suitable to, according to the decoding result, one of them be selected in the erasing voltage and wordline bias voltage
As word-line signal.
2. word line decoding circuit according to claim 1, it is characterised in that the decoding bias-voltage generating circuit is to institute
The pull-down capability for stating decoding bias voltage is better than pull-down capability of the wordline bias voltage generation to the wordline bias voltage.
3. word line decoding circuit according to claim 1 and 2, it is characterised in that the decoding bias-voltage generating circuit
Including：
First phase inverter, its input receives the detection voltage, and its output end exports the decoding bias voltage, its first electricity
Source receives first supply voltage, and its second source end receives the ground wire voltage.
4. word line decoding circuit according to claim 1 and 2, it is characterised in that the wordline bias-voltage generating circuit
Including：
Second phase inverter, its input receives the detection voltage, and its output end exports the wordline bias voltage, its first electricity
Source receives first supply voltage, its second source end coupling pull-down circuit；
The pull-down circuit, its control end receives bias voltage, when the erasing voltage is less than the threshold value, is suitable to according to institute
State the electric current that bias voltage produces the drop-down wordline bias voltage to the ground wire voltage.
5. word line decoding circuit according to claim 4, it is characterised in that second phase inverter includes：
First PMOS, its source electrode receives first supply voltage；
First NMOS tube, its grid couples the grid of first PMOS and receives the detection voltage, its drain electrode coupling institute
State the drain electrode of the first PMOS and export the wordline bias voltage, its source electrode couples the pull-down circuit；
The pull-down circuit includes：
Second NMOS tube, its grid receives the bias voltage, and the source electrode of its drain electrode coupling first NMOS tube, its source electrode connects
Ground.
6. word line decoding circuit according to claim 1, it is characterised in that the data-signal includes the first data-signal
With the second data-signal；
When first data-signal is the first logic level, second data-signal is the different from the first logic level
During two logic levels, the selection circuit exports the erasing voltage as the word-line signal；
When first data-signal is second logic level, second data-signal is first logic level
When, the selection circuit exports the wordline bias voltage as the word-line signal.
7. word line decoding circuit according to claim 6, it is characterised in that the decoding circuit includes：
First switch circuit, its control end receives first data-signal；
Second switch circuit, its control end receives second data-signal, and its first end couples the first switch circuit
First end simultaneously receives the decoding bias voltage；
Latch cicuit, its first power end receives the erasing voltage, and its second source end receives first supply voltage, tool
There are the first latch point and the second latch point, first latch point couples the second end of the first switch circuit, described second
Latch point couples the logic level instruction institute at the second end of the second switch circuit, first latch point and the second latch point
State decoding result.
8. word line decoding circuit according to claim 7, it is characterised in that
The first switch circuit includes：
3rd NMOS tube, its grid couples the control end of the first switch circuit, and its source electrode couples the first switch circuit
First end, the second end of its drain electrode coupling first switch circuit；
The second switch circuit includes：
4th NMOS tube, its grid couples the control end of the second switch circuit, and its source electrode couples the second switch circuit
First end, the second end of its drain electrode coupling second switch circuit.
9. the word line decoding circuit according to claim 1,2,6,7 or 8, it is characterised in that also include：
Level adjusting circuit, is suitable to carry out level conversion to the detection voltage.
10. a kind of memory, it is characterised in that including the word line decoding circuit described in any one of claim 1 to 9.
11. memories according to claim 10, it is characterised in that the memory is flash memory.
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| CN201710011838.4A CN106782638B (en) | 2017-01-06 | 2017-01-06 | Word line decoding circuit and memory |
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| CN106782638B CN106782638B (en) | 2019-04-16 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107680630A (en) * | 2017-09-26 | 2018-02-09 | 上海华虹宏力半导体制造有限公司 | A kind of word line decoding circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5907510A (en) * | 1997-01-03 | 1999-05-25 | Texas Instruments Incorporated | Write bias generator for column multiplexed static random access memory |
| CN103093819A (en) * | 2013-02-01 | 2013-05-08 | 上海宏力半导体制造有限公司 | Data erase circuit of nonvolatile memory |
| CN103117085A (en) * | 2013-01-25 | 2013-05-22 | 上海宏力半导体制造有限公司 | Bias voltage generating circuit and memory of line decoder |
| CN103345934A (en) * | 2013-06-03 | 2013-10-09 | 上海宏力半导体制造有限公司 | Decoding circuit for voltage of control grid |
-
2017
- 2017-01-06 CN CN201710011838.4A patent/CN106782638B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5907510A (en) * | 1997-01-03 | 1999-05-25 | Texas Instruments Incorporated | Write bias generator for column multiplexed static random access memory |
| CN103117085A (en) * | 2013-01-25 | 2013-05-22 | 上海宏力半导体制造有限公司 | Bias voltage generating circuit and memory of line decoder |
| CN103093819A (en) * | 2013-02-01 | 2013-05-08 | 上海宏力半导体制造有限公司 | Data erase circuit of nonvolatile memory |
| CN103345934A (en) * | 2013-06-03 | 2013-10-09 | 上海宏力半导体制造有限公司 | Decoding circuit for voltage of control grid |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107680630A (en) * | 2017-09-26 | 2018-02-09 | 上海华虹宏力半导体制造有限公司 | A kind of word line decoding circuit |
| CN107680630B (en) * | 2017-09-26 | 2020-07-17 | 上海华虹宏力半导体制造有限公司 | Word line decoding circuit |
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| Publication number | Publication date |
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| CN106782638B (en) | 2019-04-16 |
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