CN106776412B - Interface compatibility circuit - Google Patents
Interface compatibility circuit Download PDFInfo
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- CN106776412B CN106776412B CN201611190730.8A CN201611190730A CN106776412B CN 106776412 B CN106776412 B CN 106776412B CN 201611190730 A CN201611190730 A CN 201611190730A CN 106776412 B CN106776412 B CN 106776412B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3802—Harddisk connected to a computer port
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Debugging And Monitoring (AREA)
Abstract
The present invention relates to a kind of interface compatibility circuits, access device type including SATA connector circuit, mSATA connector circuits, governor circuit logic interfacing and identification governor circuit logic interfacing and the governor circuit for being arranged to corresponding read-write mode, wherein, access device type includes the mechanical hard disk of SATA interface, the mechanical solid-state hybrid hard disk of SATA interface, the solid state disk of SATA interface and the solid state disk of mSATA interfaces；SATA connector circuit and mSATA connector circuits are connect respectively with governor circuit logic interfacing, and governor circuit logic interfacing is connect with governor circuit；When access device type is the mechanical hard disk of SATA interface, the corresponding read-write mode of setting reads for sequence, caches write-in；When access device type is the mechanical solid-state hybrid hard disk of SATA interface, the corresponding read-write mode of setting is read for sequence, load balancing is written；When the solid state disk of solid state disk or mSATA interfaces that access device type is SATA interface, the corresponding read-write mode of setting is random read take, load balancing is written.
Description
Technical field
The present invention relates to Computer Interface Technology field, more particularly to a kind of interface compatibility circuit.
Background technology
SATA (Serial Advanced Technology Attachment, serial hard disk interface technology) is a kind of electricity
Brain bus, the data transmission being mainly used as between mainboard and a large amount of storage devices (such as hard disk and CD drive) are one to finish
The full novel hard disk interface class for being different from Parallel ATA (Advanced Technology Attachment, hard-disk interface technology)
Type, due to being gained the name using serial mode transmission data.SATA buses use embedded clock signal, have stronger error correction
Ability, its maximum compared with the past is difference lies in can check transmission instruction (being not only data), if it find that wrong
Automatic straightening is misunderstood, something which increases the reliability of data transmission, also with simple in structure, support hot plug
Advantage.MSATA interfaces (mini-SATA, miniversion SATA interface) are that one kind of SATA worlds interface standard tissue publication is new
The interface standard of type, the fields such as box and printer on tablet computer, mobile phone, machine of the solid state disk with mSATA interfaces have
It and is widely applied.
At least there are the following problems for the prior art：The access that one logic interfacing cannot be compatible with identifying processing SATA interface is set
Standby and mSATA interfaces access device, the access device of access device and mSATA interfaces for SATA interface separately design,
Occupied space is big in this way, and occupying system resources, and cost is also high.
Invention content
Based on this, it is necessary to cannot be compatible with the access of identifying processing SATA interface for a logic interfacing in the prior art
The access device of equipment and mSATA interfaces, the access device of SATA interface and the access device of mSATA interfaces separately design, and account for
It is big with space, and occupying system resources, the problem of cost is also high, provide a kind of access that can be compatible with identifying processing SATA interface
The interface compatibility circuit of the access device of equipment and mSATA interfaces.
A kind of interface compatibility circuit, including SATA connector circuit, mSATA connector circuits, governor circuit logic interfacing
And identify the access device type of governor circuit logic interfacing and be arranged to the governor circuit of corresponding read-write mode, wherein,
Access device type includes the solid-state of the mechanical hard disk of SATA interface, the mechanical solid-state hybrid hard disk of SATA interface, SATA interface
The solid state disk of hard disk and mSATA interfaces；
SATA connector circuit and mSATA connector circuits are connect respectively with governor circuit logic interfacing, and governor circuit is patrolled
Interface is collected to connect with governor circuit；
When access device type is the mechanical hard disk of SATA interface, the corresponding read-write mode of setting reads for sequence,
Caching write-in；When access device type is the mechanical solid-state hybrid hard disk of SATA interface, the corresponding read-write mode of setting is
Sequence is read, load balancing write-in；When access device type is the solid state disk of SATA interface or the solid state disk of mSATA interfaces
When, the corresponding read-write mode of setting is random read take, load balancing is written.
Above-mentioned interface compatibility circuit, including SATA connector circuit, mSATA connector circuits, governor circuit logic interfacing
And it identifies the access device type of governor circuit logic interfacing and is arranged to the governor circuit of corresponding read-write mode；SATA connects
It connects device circuit and mSATA connector circuits is connect respectively with governor circuit logic interfacing, governor circuit logic interfacing and master control electricity
Road connects, and when access device type is the mechanical hard disk of SATA interface, the corresponding read-write mode of setting reads for sequence, is slow
Deposit write-in；When access device type is the mechanical solid-state hybrid hard disk of SATA interface, the corresponding read-write mode sequence of setting
It reads, load balancing write-in；When the solid state disk of solid state disk or mSATA interfaces that access device type is SATA interface,
The corresponding read-write mode of setting is random read take, load balancing is written, the compatible identification SATA interface of the interface compatibility circuit
Access device and mSATA interfaces access device, and corresponding read-write mode is set according to the type of access device, without point
It opens independent design and is used for the access device for identifying SATA interface and the governor circuit for identifying the access device of mSATA interfaces
Logic interfacing occupies little space in this way, and saves system resource, reduces cost.
Description of the drawings
Fig. 1 is the structure diagram of interface compatibility circuit in one embodiment；
Fig. 2 is the circuit diagram of the SATA connector circuit in interface compatibility circuit in one embodiment；
Fig. 3 is the circuit diagram of the mSATA connector circuits in interface compatibility circuit in one embodiment.
Specific embodiment
Hard-disk interface is the connecting component between hard disk and host system, and effect is passed between hard disk cache and host memory
Transmission of data.From whole angle, hard-disk interface is divided into IDE, and (Integrated Drive Electronics, i.e. electronics integrate
Driver), SATA (Serial Advanced Technology Attachment, serial hard disk interface technology), SCSI
(Small Computer System Interface, small computer system interface), optical-fibre channel and SAS (Serial
Attached SCSI, Serial Attached SCSI (SAS)) five kinds.Ide interface hard disk is chiefly used in household products, and also certain applications are in service
Device；The hard disk of scsi interface is then mainly used in server market, and optical-fibre channel is in high-end server, expensive；
SATA is a kind of hard-disk interface type of new life, is in the market stage of popularization, there is extensive prospect in household application market.
MSATA interfaces (mini-SATA, miniversion SATA interface) are a kind of novel the connecing of SATA worlds interface standard tissue publication
Mouth standard, the fields such as box and printer on tablet computer, mobile phone, machine of the solid state disk with mSATA interfaces have extensively
Application.
Mechanical hard disk is traditional common hard disc, mainly including disc, magnetic head, disc shaft and control motor, magnetic head control
Device, data converter, interface, caching etc..Magnetic head can be moved along the radial direction of disc, in addition the height of thousands of turns per minute of disc
Speed rotation, magnetic head can be located in the read-write operation that data are carried out on the designated position of disc.Information passes through from magnetic surface
Close magnetic head is write by electromagnetic current on disk by electromagnetic current to change polarity mode, and information can be read by opposite mode
It takes, as precision equipment, dust is its formidable enemy, it is necessary to is fully sealed.All discs are incorporated into a rotation in mechanical hard disk
Be on axis, between each disc piece it is parallel, mechanical hard disk on the storage face of each disc there are one magnetic head, magnetic head and disc it
Between distance it is also smaller than the diameter of hairline, all magnetic heads are connected on a magnetic head control device, are responsible for respectively by magnetic head control device
The movement of a magnetic head.
Solid state disk referred to as consolidate disk, and the solid state disk manufactured hard disk of solid-state electronic storage chip array, including control
Unit and storage unit (FLASH chip and dram chip).SSD (Solid State Drives, solid state disk) solid state disk
Inside is there is no any mechanical part, accordingly even when will not be influenced in the case where high-speed mobile is even with tip tilt
Normal use, and the possibility of loss of data can be minimized when colliding and shaking.The storage of solid state disk
Medium is divided into two kinds, and one kind is as storage medium using flash memory (FLASH chip), another is as storage using DRAM
Medium.Solid state disk based on flash memory is the primary categories of solid state disk, internal structure very simple, solid state disk interior main body
It is exactly one piece of PCB (Printed Circuit Board, printed wiring board) plate in fact, and accessory most basic on this block pcb board
Exactly control chip, cache chip (part low side hard disk is without cache chip) and the flash chip for storing data.Master control core
Piece is the brain of solid state disk, and effect one is load of the rational allocation data on each flash chip, is second assumed responsibility for
Entire data relay, connection flash chip and external SATA interface.Ability difference is very big between different master controls, at data
Reason ability, algorithm to having very big difference in the reading write-in control of flash chip, can directly lead to solid-state hard disc product
Gap is up to decades of times in performance.
Hybrid hard disk is regarded as solid state disk and is used in mixed way with general mechanical hard disk by many users, in fact hybrid hard disk
It is not the address for being used in mixed way solid state disk and traditional mechanical hard disk.Hybrid hard disk is one piece based on traditional mechanical hard disk
Be born new hard disk out, and in addition to disk, motor, magnetic head of mechanical hard disk indispensability etc., also built-in nand flash memory particle is somebody's turn to do
Particle stores the data that user often accesses, and can reach such as the reading performance of SSD solid state disk effects.SSHD
(Solid State Hybrid Drive, solid-state hybrid hard disk) is that one kind that magnetic hard-disk and flash memory are integrated together is hard
Disk is a solution among magnetic hard-disk and solid state disk.
In one embodiment, as shown in Figure 1, a kind of interface compatibility circuit, including SATA connector circuit 100, mSATA
The access device type of connector circuit 200, governor circuit logic interfacing 300 and identification governor circuit logic interfacing 300 is simultaneously
It is arranged to the governor circuit 400 of corresponding read-write mode, wherein, the machinery that the access device type includes SATA interface is hard
Disk, the mechanical solid-state hybrid hard disk of SATA interface, the solid state disk of SATA interface and the solid state disk of mSATA interfaces；
SATA connector circuit 100 and mSATA connector circuits 200 are connect respectively with governor circuit logic interfacing 300, main
Control circuit logic interface 300 is connect with governor circuit 400；
When access device type is the mechanical hard disk of SATA interface, the corresponding read-write mode of setting reads for sequence,
Caching write-in；When access device type is the mechanical solid-state hybrid hard disk of SATA interface, the corresponding read-write mode of setting is
Sequence is read, load balancing write-in；When access device type is the solid state disk of SATA interface or the solid state disk of mSATA interfaces
When, the corresponding read-write mode of setting is random read take, load balancing is written.
Specifically, governor circuit can judge that governor circuit is patrolled by setting the parameter of an identification access device type
The type of interface access device is collected, such as mechanical hard disk of the access device type as SATA interface is represented with 1,2 represent access
Device type is the mechanical solid-state hybrid hard disk of SATA interface, and 3 represent solid state disk of the access device type as SATA interface, 4
Solid state disk of the access device type as mSATA interfaces is represented, when governor circuit detects the parameter of identification access device type
When being 1, it is the mechanical hard disk of SATA interface to illustrate current input equipment.From the read-write efficiency of access device and service life two
Aspect considers, and with reference to the characteristic of different types of access device in itself, to make the read-write efficiency higher to access device, makes
With longer life expectancy, when access device type is the mechanical hard disk of SATA interface, the corresponding read-write mode of setting is read for sequence
It takes, cache write-in；When access device type is the mechanical solid-state hybrid hard disk of SATA interface, the corresponding read-write mode of setting
It is read for sequence, load balancing write-in；When access device type is hard for the solid state disk of SATA interface or the solid-state of mSATA interfaces
During disk, the corresponding read-write mode of setting is random read take, load balancing is written.
SATA connector circuit 100, including SATA connector, the first capacitance, the second capacitance, third capacitance and the 4th electricity
Hold, the first differential received pin of one end connection SATA connector of the first capacitance, the other end connection master control electricity of the first capacitance
The first differential received pin on road；Second differential received pin of one end connection SATA connector of the second capacitance, the second capacitance
The other end connection governor circuit the second differential received pin；First difference of one end connection SATA connector of third capacitance
Pin is sent, the first difference of the other end connection governor circuit of third capacitance sends pin；One end connection of 4th capacitance
Second difference of SATA connector sends pin, and the second difference of the other end connection governor circuit of the 4th capacitance sends pin.
Interface compatibility circuit further includes first circuit board, SATA connector, the first capacitance, the second capacitance, third capacitance and the 4th electricity
Appearance is set in turn in first circuit board.Specifically, the first capacitance, second capacitance, third capacitance and the 4th capacitance are
The capacitance of 10nF.More specifically, Fig. 2 is the circuit diagram of SATA connector, wherein, the first capacitance is C315, and second is electric
Hold for C316, third capacitance is C317, and the 4th capacitance is C318.
MSATA connector circuits 200, including mSATA connectors, the 5th capacitance, the 6th capacitance, the 7th capacitance and the 8th
Capacitance, one end of the 5th capacitance connect the first differential received pin of the mSATA connectors, the other end connection of the 5th capacitance
First differential received pin of governor circuit；Second differential received pin of one end connection mSATA connectors of the 6th capacitance, the
Second differential received pin of the other end connection governor circuit of six capacitances；One end connection mSATA connectors of 7th capacitance
First difference sends pin, and the first difference of the other end connection governor circuit of the 7th capacitance sends pin；The one of 8th capacitance
Second difference of end connection mSATA connectors sends pin, the second difference hair of the other end connection governor circuit of the 8th capacitance
Send pin.Interface compatibility circuit further includes second circuit board, mSATA connectors, the 5th capacitance, the 6th capacitance, the 7th capacitance with
And the 8th capacitance be set in turn in second circuit board.Specifically, the 5th capacitance, the 6th capacitance, the 7th capacitance and the 8th capacitance
It is the capacitance of 10nF.More specifically, Fig. 3 is the circuit diagram of mSATA connectors, wherein, the 5th capacitance is C323, the
Six capacitances are C325, and the 7th capacitance is C326, and the 8th capacitance is C327.
Governor circuit 400 includes GL830 main control chips, and GL830 is a high-compatibility, inexpensive USB
(Universal Serial Bus, universal serial bus) 2.0 pairs of SATA bridges connect controller.
Above-mentioned interface compatibility circuit, including SATA connector circuit, mSATA connector circuits, governor circuit logic interfacing
And it identifies the access device type of governor circuit logic interfacing and is arranged to the governor circuit of corresponding read-write mode；SATA connects
It connects device circuit and mSATA connector circuits is connect respectively with governor circuit logic interfacing, governor circuit logic interfacing and master control electricity
Road connects, and when access device type is the mechanical hard disk of SATA interface, the corresponding read-write mode of setting reads for sequence, is slow
Deposit write-in；When access device type is the mechanical solid-state hybrid hard disk of SATA interface, the corresponding read-write mode of setting is suitable
Sequence is read, load balancing write-in；When access device type is the solid state disk of SATA interface or the solid state disk of mSATA interfaces
When, the corresponding read-write mode of setting is random read take, load balancing is written, and the compatible identification SATA of the interface compatibility circuit connects
The access device of mouth and the access device of mSATA interfaces, and corresponding read-write mode is set according to the type of access device, without
It separates independent design and is used to identify the access device of SATA interface and for identifying the master control of the access device of mSATA interfaces electricity
Road logic interfacing, occupies little space in this way, and saves system resource, reduces cost.
In one embodiment, in interface compatibility circuit, when access device type for SATA interface solid state disk or
It, will be to SATA interface based on solid state disk without the limited characteristic of mechanical structure, read-write number during the solid state disk of mSATA interfaces
Solid state disk or mSATA interfaces solid state disk it is adjacent twice read-write data time interval be set as 0, access is improved with this
The reading-writing life-span of equipment.Specifically, this is because when that need to read again data, mechanical hard disk is needed the motor stopped
It rotates and can just carry out reading and writing data after reaching specified rotating speed, accelerating to specified rotating speed from 0 needs the time, and here it is described
Delay time, and solid state disk does not have rotating speed, can perform read-write operation at once.In addition, the master control in interface compatibility circuit
Circuit obtains the capacity and cache size of the access device of governor circuit logic interfacing, according to amount of capacity and the size of cache size,
Determine read-write operation frequent degree, capacity is big, and read-write operation is more frequent；Cache size is smaller, and read-write operation is more frequent, to ensure
Higher read-write efficiency.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, it is all considered to be the range of this specification record.
Embodiment described above only expresses the several embodiments of the present invention, and description is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that those of ordinary skill in the art are come
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Range.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (8)
1. a kind of interface compatibility circuit, which is characterized in that including SATA connector circuit, mSATA connector circuits, governor circuit
The access device type of logic interfacing and the identification governor circuit logic interfacing and the master for being arranged to corresponding read-write mode
Circuit is controlled, wherein, the access device type includes the mechanical hard disk of SATA interface, the mechanical solid-state of SATA interface mixes firmly
The solid state disk of disk, the solid state disk of SATA interface and mSATA interfaces；
The SATA connector circuit and the mSATA connector circuits are connect respectively with the governor circuit logic interfacing, institute
Governor circuit logic interfacing is stated to connect with the governor circuit；
When the access device type is the mechanical hard disk of SATA interface, the corresponding read-write mode of setting is read for sequence
It takes, cache write-in；When the access device type be SATA interface mechanical solid-state hybrid hard disk when, setting it is corresponding
Read-write mode is read for sequence, load balancing write-in；When the solid state disk or mSATA that the access device type is SATA interface
During the solid state disk of interface, the corresponding read-write mode of setting is random read take, load balancing is written；
When the solid state disk of solid state disk or mSATA interfaces that the access device type is SATA interface, the SATA connects
The time interval of the solid state disk of mouth or the adjacent data of read-write twice of the solid state disk of the mSATA interfaces is 0；The master control electricity
Road obtains the capacity and cache size of the access device of the governor circuit logic interfacing.
2. interface compatibility circuit according to claim 1, which is characterized in that the SATA connector circuit connects including SATA
Device, the first capacitance, the second capacitance, third capacitance and the 4th capacitance are connect, one end of first capacitance connects the SATA and connects
The first differential received pin of device is connect, the first differential received of the other end connection governor circuit of first capacitance is drawn
Foot；One end of second capacitance connects the second differential received pin of the SATA connector, second capacitance it is another
End connects the second differential received pin of the governor circuit；One end of the third capacitance connects the of the SATA connector
One difference sends pin, and the other end of the third capacitance connects the first difference transmission pin of the governor circuit；Described
The second difference that one end of four capacitances connects the SATA connector sends pin, described in the other end connection of the 4th capacitance
Second difference of governor circuit sends pin.
3. interface compatibility circuit according to claim 2, which is characterized in that further include first circuit board, the SATA connects
It connects device, first capacitance, second capacitance, the third capacitance and the 4th capacitance and is set in turn in described first
Circuit board.
4. interface compatibility circuit according to claim 2, which is characterized in that first capacitance, second capacitance, institute
State third capacitance and the 4th capacitance be 10nF capacitance.
5. interface compatibility circuit according to claim 1, which is characterized in that the mSATA connector circuits include mSATA
Connector, the 5th capacitance, the 6th capacitance, the 7th capacitance and the 8th capacitance, one end of the 5th capacitance connect the mSATA
First differential received pin of connector, the first differential received of the other end connection governor circuit of the 5th capacitance are drawn
Foot；One end of 6th capacitance connects the second differential received pin of the mSATA connectors, the 6th capacitance it is another
End connects the second differential received pin of the governor circuit；One end of 7th capacitance connects the mSATA connectors
First difference sends pin, and the other end of the 7th capacitance connects the first difference transmission pin of the governor circuit；It is described
The second difference that one end of 8th capacitance connects the mSATA connectors sends pin, the other end connection of the 8th capacitance
Second difference of the governor circuit sends pin.
6. interface compatibility circuit according to claim 5, which is characterized in that further include second circuit board, the mSATA connects
It connects device, the 5th capacitance, the 6th capacitance, the 7th capacitance and the 8th capacitance and is set in turn in described second
Circuit board.
7. interface compatibility circuit according to claim 5, which is characterized in that the 5th capacitance, the 6th capacitance, institute
State the 7th capacitance and the 8th capacitance be 10nF capacitance.
8. the interface compatibility circuit according to any one in claim 1-7, which is characterized in that the governor circuit includes
GL830 main control chips.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611190730.8A CN106776412B (en) | 2016-12-21 | 2016-12-21 | Interface compatibility circuit |
| PCT/CN2016/113538 WO2018113026A1 (en) | 2016-12-21 | 2016-12-30 | Interface compatible circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611190730.8A CN106776412B (en) | 2016-12-21 | 2016-12-21 | Interface compatibility circuit |
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| CN106776412A CN106776412A (en) | 2017-05-31 |
| CN106776412B true CN106776412B (en) | 2018-07-03 |
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| CN201611190730.8A Active CN106776412B (en) | 2016-12-21 | 2016-12-21 | Interface compatibility circuit |
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| CN (1) | CN106776412B (en) |
| WO (1) | WO2018113026A1 (en) |
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|---|---|---|---|---|
| CN206370051U (en) * | 2016-12-21 | 2017-08-01 | 广州炒米信息科技有限公司 | Interface compatibility circuit |
| CN107229428A (en) * | 2017-06-26 | 2017-10-03 | 长沙开雅电子科技有限公司 | A kind of new mSATA memory buffers accelerated method |
| CN110568905A (en) * | 2019-08-09 | 2019-12-13 | 苏州浪潮智能科技有限公司 | Hard disk backboard, signal processing method and medium |
| CN111010357B (en) * | 2020-03-09 | 2020-06-16 | 中国人民解放军国防科技大学 | Data ferrying method and device based on HDD hard disk |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101751338A (en) * | 2008-12-15 | 2010-06-23 | 中芯国际集成电路制造(上海)有限公司 | Data access control device and data access method |
| CN204463822U (en) * | 2015-01-09 | 2015-07-08 | 特科芯有限公司 | SATA and mSATA double nip the solid state hard disc deposited |
| CN205176831U (en) * | 2015-11-02 | 2016-04-20 | 深圳华北工控股份有限公司 | Automatic SATA storage facilities listens switching circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9081908B2 (en) * | 2012-11-15 | 2015-07-14 | Qualcomm Incorporated | Operating M-PHY based communications over serial advanced technology attachment (SATA)-based interface, and related cables, connectors, systems and methods |
| CN206370051U (en) * | 2016-12-21 | 2017-08-01 | 广州炒米信息科技有限公司 | Interface compatibility circuit |
-
2016
- 2016-12-21 CN CN201611190730.8A patent/CN106776412B/en active Active
- 2016-12-30 WO PCT/CN2016/113538 patent/WO2018113026A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101751338A (en) * | 2008-12-15 | 2010-06-23 | 中芯国际集成电路制造(上海)有限公司 | Data access control device and data access method |
| CN204463822U (en) * | 2015-01-09 | 2015-07-08 | 特科芯有限公司 | SATA and mSATA double nip the solid state hard disc deposited |
| CN205176831U (en) * | 2015-11-02 | 2016-04-20 | 深圳华北工控股份有限公司 | Automatic SATA storage facilities listens switching circuit |
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| Publication number | Publication date |
|---|---|
| CN106776412A (en) | 2017-05-31 |
| WO2018113026A1 (en) | 2018-06-28 |
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