CN106775596A - A kind of infrared image linear interpolation expands hardware processing method - Google Patents
A kind of infrared image linear interpolation expands hardware processing method Download PDFInfo
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Abstract
The invention discloses a kind of infrared image linear interpolation expansion hardware processing method, first, set up expansion after between image and original image pixels point between coordinate mapping relations；Then, calculated using coordinate, gray scale is read, expansion is calculated, gray scale stores four level production lines and realizes that algorithm is designed.The location method that quickly taken without loss of significance is wherein employed in design process of hardware, fifo controller realizes that quickly the method such as reading ensures streamline efficient operation to gray scale, greatly improves algorithm arithmetic speed, reduces hardware resource cost, improves computational accuracy.Present invention realization under Xilinx virtex5 XC5VFX100T, operates in 100M.To original image 160*128,1.2 times, i.e. 192*153 are expanded, then the image that original template Fig. 1 .1 times sizes are 176*140 is intercepted in expanding image, completing algorithm computing only needs 0.25ms.
Description
Technical field
The present invention relates to a kind of infrared image linear interpolation expansion hardware processing method, belong to tailor-made algorithm hardware circuit and set
Meter field.
Background technology
The information processing technology based on images match has begun to widely apply in space flight model of new generation, image procossing
Real-time directly affect guidance precision.Image processing algorithm was realized using software based on general processor (such as DSP) in the past
It is increasingly difficult to meet the requirement of real-time of space flight model.At present, come through frequently with the mode for simplifying algorithm sacrifice arithmetic accuracy
Reduce algorithm operation time.Realize that algorithm acceleration is the most effective means of reduction algorithm operation time by hardware algorithm.
Current image procossing uses the matching process based on half-tone information, but this method matching precision computing high
Amount is than larger.By to capture, tracking etc. terminal guidance target seeker information process be analyzed, will wherein expend the time it is long,
Processing structure is complicated, the big image algorithm that takes up room carries out Hardware Design, and image expansion algorithm is wherein to need at acceleration
One of algorithm of reason.
The content of the invention
Technology solve problem of the invention is：Overcome the deficiencies in the prior art, there is provided a kind of infrared image linear interpolation
Expansion hardware processing method, by the pipeline design, the quickly design such as reading of location, gray scale is quickly taken without loss of significance, is greatly carried
Algorithm arithmetic speed high, improves computational accuracy, rationally control hardware resource cost, and in Xilinx virtex5-
Realized under XC5VFX100T, work operates in 100M.
Technical solution of the invention is：A kind of infrared image linear interpolation expands hardware processing method, and the method is adopted
Realized with hardware, accelerate image expansion processing speed, artwork is carried out into expansion first amplifies the image after being expanded, then right
Each pixel p' performs following steps in image after expansion：
(1), coordinate is calculated, the coordinate p'(m in p' upon inflation image coordinate system, and n) the anti-point that pushes away is sat in artwork
Mark the coordinate p (i of system0,j0), to p (i0,j0) coordinate value carry out rounding operation, obtain nearest apart from p points upper left in artwork
Point coordinates (im,jn)；The origin of coordinates of image coordinate system is the image upper left corner after expansion after the expansion, and the upper left corner is to the right
Image coordinate system transverse axis X-axis positive direction after expansion, the upper left corner is downwards image coordinate system longitudinal axis Y positive directions, the original after expansion
The origin of coordinates of figure coordinate system is the upper left corner of artwork, and the upper left corner is to the right artwork coordinate system transverse axis X-axis positive direction, and upper left is angular
It is down artwork coordinate system longitudinal axis Y-axis positive direction.
(2), gray scale is read, and p (i in artwork are obtained from artwork memory0,j0) point four gray values of point of surrounding：f
(im,jn)、f(im+1,jn)、f(im,jn+1)、f(im+1,jn+ 1) continuous two groups of gradation datas, will be stored two is stored in respectively
In internal FIFO, the f (x, y) is the gradation data at coordinate (x, y) place in original image；
(3), expansion is calculated, and p (i are read out from two FIFO0,j0) point four gray values of point of surrounding：f(im,jn)、f
(im+1,jn)、f(im,jn+1)、f(im+1,jn+ 1), using p'(i in the image after bilinear interpolation algorithm calculating expansion, j)
Image intensity value；
(4), gray scale storage, the image intensity value that step (3) is calculated is saved in the corresponding storage of image after expanding
In device, p'(i, image intensity value j) in image are updated after expansion.
Methods described is realized in FPGA.
The coordinate of the step (1)~step (4) is calculated, gray scale reads, expansion is calculated, gray scale storage uses level Four flowing water
Line Parallel Implementation.
Size in the step (1) when artwork is width_src × height_src, and the size of image is after expansion
During width_exp × height_exp, according to coordinate p'(m in image after expansion, n) the anti-corresponding position for pushing away this in artwork
Put p (i0,j0), obtain nearest apart from p points top left pixel point coordinates (i in artworkm,jn) use the method for iteration recursion for：
Work as m=0, during n=0, make i0=0, j0=0, make intermediate variable R0=0, T0=0；
When m >=1, intermediate variable R is calculatedm=Rm-1+ width_src, m ∈ { 1 ..., width_exp-1 }, if Rm<
Width_exp, then im=im-1；If Rm>=width_exp, then im=im-1+ 1, Rm=Rm-1-width_exp；
When n >=1, intermediate variable T is calculatedn=Tn-1+ height_src, n ∈ { 1 ..., height_exp-1 }, if Tn<
Height_exp, then jn=jn-1；If Tn>=height_exp, then jn=jn-1+ 1, Tn=Tn-1-height_exp。
Artwork memory bit wide is 4 times of pixel gray value width, every four pixel gray values correspondence, one address
Memory space, its storage address is：(ordinate x × original image width width_src+ abscissas y)>>2, two FIFO's
Width is the width of pixel gray value, and depth is more than or equal to 16.
Gray scale read the process that implements be：
In first pipeline cycle of every row, following steps are performed：
(2.1a), calculate gray value f (im,jn) absolute address in memory, it is designated as row address addrOn；Calculate f
(im+1,jn) absolute address in memory, it is designated as descending address addrUnder：
addrOn=im×width_src+jm
addrUnder=(im+1)×width_src+jm
(2.2a), by upper row address addrOnWith descending address addrUnderIt is converted into binary form, and by binary form
Upper row address addrOnWith the descending address addr of binary formUnderCarry out low two truncations and obtain the up reading address of memory
addr_readOnWith descending reading address addr_readUnder；
(2.3a), according to up read pointer addr_readOnContinuous 4 gradation datas are deposited into FIFO_ in extracting memory
In 0, up reading address addr_readOnPlus 1, FIFO_0 write addresses add 4；According to descending read pointer addr_readUnderExtract storage
Continuous 4 gradation datas are deposited into FIFO_1 in device, descending reading address addr_readUnderPlus 1, FIFO_1 write addresses add 4；
(2.4a), work as addrOnLow 2 for 2 ' b11 when, by addr_readOnOne address of recursion, obtains new backward
addr_readOn, step (2.3a) is re-executed, then, step is calculated into next level production line dilatometer；Otherwise, it is directly entered
Next level production line dilatometer calculates step；
In the subsequent pipeline cycle of every row, following steps are performed：
(2.1b), judge to whether there is at least 4 free spaces in FIFO_0, if it is present up reading address addr_
readOnPlus 1, continuous 4 gradation datas are read from memory and is sequentially stored into in FIFO_0；FIFO_0 write addresses add 4；It is no
Then, wait；
(2.2b), judge to whether there is at least 4 free spaces in FIFO_1, if it is present descending reading address addr_
readUnderPlus 1, continuous 4 gradation datas are read from memory, be sequentially stored into FIFO_1；FIFO_1 write addresses add 4；It is no
Then, wait；
The FIFO_0 and FIFO_1 are cyclic buffer, when FIFO_0 and FIFO_1 have expired, circulation storage.
What expansion was calculated is implemented as：
In first pipeline cycle of every row, following steps are performed：
(3.1a), according to row address addr on binary formOnAddress addr descending with binary formUnderIt is low two work
It is the initial read address in FIFO_0 and FIFO_1；
(3.2a), read taking-up f (i address since FIFO_0m,jn)、f(im,jn+1)；Read address from FIFO_1 to open
Begin to take out f (im+1,jn)、f(im+1,jn+1)；
(3.3a), four gray values read in step (3.2a) are added after move to right 2 expanded after figure
P'(i, image intensity value j) as in：
F ' (m, n)=(f (im,jn)+f(im+1,jn)+f(im,jn+1)+f(im+1,jn+1))>>2；
Within the subsequent pipeline cycle of every row, following steps are performed：
(3.1b), according to result of calculation in coordinate transform in step (2), work as Rm<Width_exp, i.e. im=im-1, and Tn<
Height_exp, i.e. jn=jn-1When, it is constant that FIFO_0 and FIFO_1 reads address；Work as TnDuring >=height_exp, jn=jn-1+ 1,
FIFO_0 and FIFO_1 reads address and adds 1；
(3.2b), read taking-up f (i address since FIFO_0m,jn)、f(im,jn+1)；Read address from FIFO_1 to open
Begin to take out f (im+1,jn)、f(im+1,jn+1)；
(3.3b), four gray values read in step (3.2b) are added after move to right 2 expanded after figure
P'(i, image intensity value j) as in：
F ' (m, n)=(f (im,jn)+f(im+1,jn)+f(im,jn+1)+f(im+1,jn+1))>>2。
Compared with the prior art, the invention has the advantages that：
(1), designed present invention employs 4 level production lines, calculated by efficient parallel and improve arithmetic speed.
(2), present invention employs location method is quickly taken without loss of significance, the method can obtain gray scale and take location ground with the monocycle
Location, and calculating process is only with simple addition and compares operation, without loss of significance.
(3) the quick reading of gray scale, is realized present invention employs two internal fifo controllers.Due to each dilatometer
Gray scale address is read needed for calculating discontinuous, employ two independent small FIFO and preserve memory read data, and by FIFO
Read-write Catrol ensures that the monocycle provides 4 gradation datas and participates in expansion calculating, maintains the efficiency of streamline.
(4), the present invention is analyzed by image bilinear interpolation expansion algorithm, and algorithm is needed first to being originally inputted figure
As carrying out linear interpolation expansion, the sized image that then interception placed in the middle needs on the image of expansion again.By streamline, quickly
The quickly design such as reading of location, gray scale is taken, Hardware Design is optimized, algorithm speed is greatly improved.And entirely designed
Dexterously reduce and consume resource and loss of significance using operation and translation replacement multiplication and division arithmetic is compared in journey.
(5), this algorithm realizes under Xilinx virtex5-XC5VFX100T, operates in 100M, it is this under the conditions of to original
Beginning image 160*128, expands 1.2 times, i.e. 192*153, then it is 176* that original template Fig. 1 .1 times sizes are intercepted in expanding image
140 image, completing algorithm computing only needs 0.25ms.
Brief description of the drawings
Fig. 1 is schematic diagram before and after image expansion of the present invention；
Fig. 2 is bilinear interpolation expansion algorithm gray count schematic diagram；
Fig. 3 is that infrared image linear interpolation of the present invention expands hardware-accelerated general frame；
Fig. 4 is to calculate the method schematic diagram that original image participates in coordinates computed scope according to interception size；
Fig. 5 is the pipeline design schematic diagram；
Fig. 6 is image expansion coordinate calculating process schematic diagram；
Fig. 7 is image expansion algorithm FIFO schematic diagrames.
Specific embodiment
The content not being described in detail in description of the invention belongs to the known technology of professional and technical personnel in the field.Below
Specific embodiment of the invention is further described in detail with reference to accompanying drawing.
Image bilinear interpolation expansion algorithm is the most frequently used image expansion algorithm, for pretreatment image resolution ratio to be adjusted
It is whole extremely identical with real-time figure resolution ratio.
Fig. 1 is schematic diagram before and after image expansion, and left figure is artwork, and right figure is image after expansion.P ' is image after expansion
A pixel in data, image coordinate system middle position is set to p'(m after a ' × b ' expansions, and n), p is corresponding points in artwork
Point, position in artwork coordinate system is p (i0,j0).The origin of coordinates of image coordinate system is the figure after expansion after the expansion
As the upper left corner, the upper left corner is to the right image coordinate system X-axis positive direction after expansion, and the upper left corner is downwards image coordinate system Y after expansion
Axle positive direction, the origin of coordinates of the artwork coordinate system is the upper left corner of artwork, and the upper left corner is to the right for artwork coordinate system X-axis is square
To the upper left corner is downwards artwork coordinate system Y-axis positive direction.
The general principle of bilinear interpolation expansion algorithm is：
Coordinate p'(m in p' upon inflation image coordinate system, n) the anti-coordinate p for pushing away this in artwork coordinate system
(i0,j0).It can be seen from relation of the p points in Fig. 1 with p ', r is made for the coefficient of expansion, then Obtaining the seat of p points
After mark, it is clear that the coordinate of p points is not necessarily integer, in order to describe the gray value of p' points exactly, to (i0,j0) carry out rounding fortune
Calculate, obtain nearest apart from p points in artwork upper left point coordinates (im,jn), (im,jn)、(im,jn+1)、(im+1,jn)、(im+1,jn
+ 1) it is (i0,j0) around four pixel point coordinates.If f (x, y) is original image gradation data, f (im,jn)、f(im+1,
jn)、f(im,jn+1)、f(im+1,jn+ 1) it is p0Four gray values of point around point, as shown in Figure 2.Calculated using bilinear interpolation
Method calculate expansion after image in p'(m, image intensity value n), then the gray value of p ' be represented by：F ' (m, n)=(f
(im,jn)+f(im+1,jn)+f(im,jn+1)+f(im+1,jn+1))/4。
Fig. 3 is that infrared image linear interpolation proposed by the present invention expands hardware-accelerated general frame.Algorithm input has original
Picture size：Width_src × height_src, width_src are original graph image width, and height_src is original graph image height,
Picture size width_exp × height_exp and interception image size width_icpt × height_icpt after expansion,
Width_exp is that image is wide after expanding, and height_exp is that image is high after expanding, and width_icpt is that image is wide after intercepting,
Height_icpt is that image is high after intercepting.
The position range of interception image i.e. output image image upon inflation can be calculated according to these parameters first, is only needed
Calculating the pixel in the range of this carries out Coordinate Conversion and calculates gray value.
Fig. 4 is to calculate the method schematic diagram that original image participates in coordinates computed scope according to interception size.As shown in figure 4,
Image is intercepted in exporting image upon inflation from center, and interception scope is：
Matrix wide scope：(width_exp-width_icpt)/2, (width_exp+width_icpt)/2
Matrix high scope:(height_exp-height_icpt)/2, (height_exp+height_icpt)/2
After obtaining output image scope, carrying out the expansion calculating of Coordinate Conversion backwards calculation output image needs original image ash
Degree coordinate, gray value address in memory, the receive data from memory 1 are calculated according to original image gray scale coordinate
According to, then carry out gray-level interpolation expansion and calculate, memory 2 is write after the completion of calculating.
To improve data throughout and treatment effeciency, algorithm is used according to infrared image dilation operation IP kernel implementation process
Hardware realization, accelerates expansion process speed.First, by artwork carry out expansion amplify expanded after image, then, line by line according to
It is secondary to each pixel p' treatment in image after expansion, each pixel p' implementation process be decomposed into coordinate calculate, gray scale
Read, expansion is calculated, gray scale stores four level production lines.As shown in Figure 5.Each operation time in stage is analyzed, is rationally evenly distributed on
In each level production line, can be completed the monocycle per level production line task, realize that level Four pipeline parallel method works.
It is introduced below to implement process:
1st, coordinate is calculated
It is to calculate pretreatment image position in memory that first order coordinate is calculated in four level production lines.Coefficient of expansion r
It is width_exp/width_src, i* (1/r)=i* (width_src/width_exp) rounds wide in pretreatment image
Degree takes location coordinate, and wherein i is sequentially increased.Hardware divider expends resource greatly, and operation time is (needing multiple cycles) long.Take every time
Location all carries out i* (width_src/width_exp) calculating and will greatly reduce pipeline efficiency；And take every time location according to
Width_src/width_exp adds up to round to bring and takes location error, and this is, because divider bit wide is limited, repeatedly to add up and make
Into the accumulation of error, it is likely that cause to take location mistake.This algorithm realizes that location is quickly taken without loss of significance to be calculated using coordinate comparison method,
Only need to simple plus-minus compare operation just can be with, consume that resource is few, speed is fast, and completely without loss of significance.
Coordinate calculates calculating process schematic diagram as shown in fig. 6, needing to obtain the original of interception image gray count needs
Gradation of image coordinate, whether next gray scale expansion will take location coordinate according to the decision of Coordinate Conversion result in original image right
Move/move down.
Image expansion coefficient r be width_exp/width_src (or height_exp/height_src, it is horizontal and vertical
Image expansion coefficient can be inconsistent), i (1/r) rounds the coordinate after expansion.In turn, gradation of image calculating is needed after expansion
The original image gray scale coordinate as i* (1/r) wanted is rounded.
The present invention devises one kind and location method is quickly taken without loss of significance, takes location calculating and does not use multiplication and division computing, only uses
Simple addition and comparison operation, it is ensured that the monocycle completes the level production line.
Such as the image expansion Formula of Coordinate System Transformation for above improving：So, after expansion image often row lateral coordinates i with
Coordinates of original image coordinates i0Mapping relations beDenominator is unanimously in the formula
Width_exp, image coordinate is mobile each time after expansion represents that molecule adds width_src, and molecule denominator is compared to
Judge whether abscissa moves.
During i=0, molecule initial value is 0, [i0]=0；
During i=1, molecule is width_src+0, due to width_src<Width_exp, then [i0] it is constant still be 0；
During i=2, molecule is width_src+width_src, if width_src+width_src<Width_exp, then
[i0] it is constant still be 0；If width_src+width_src >=width_exp, [i0] Jia 1 and molecule subtracts width_exp and is
It is next time the numerator value of i=3 comparison operations；
……
During i=n, compare molecule and width_src sums and width_exp, if molecule is less than with width_src sums
Width_exp then [i0] constant；If molecule is more than width_exp, [i with width_src sums0] Jia 1 and molecule is subtracted
Width_exp is used as the numerator value for being next time i=n+1 comparison operations；
Ordinate similarly, image often row longitudinal coordinate j and coordinates of original image coordinates j after expansion0Mapping relations beIn the same manner by vertical to compare the judgement of molecule denominator
Whether coordinate moves, mapping of the image to original image ordinate after being expanded.
After image is to the mapping of original image abscissa and ordinate after being expanded, you can obtain to original image address
Location is taken, location address=ordinate × width_src+ abscissas are taken.This method does not use divide operations, only simple to add
Method and compare operation, therefore without loss of significance, it is possible to achieve location quickly is taken to coordinates of original image coordinates.
2nd, gray scale reads
For reduction process time improves treatment effeciency, the dilation operation of final interception image is only carried out.Dilation operation
Reading needs four gradation datas.If only reading a gradation data every time, each dilation operation needs to read 4 times, that is, need
Four clock cycle.Using high-order wide memory, the bus bit wide of memory 1 is 4 times of gray scale bit wide to this algorithm in Fig. 3, this
Sample can once read 4 gradation datas.By taking gray scale bit wide 8bit as an example, memory bus bit wide is taken as 32bit.Every four pictures
Gray value one storage address of correspondence of vegetarian refreshments.Further, since expansion calculates the four gradation data addresses for needing discontinuously, its
In one group of continuous, two groups of data break width_src two-by-two.It is 16 that the design employs two depth, and width is gray scale bit wide
Inside FIFO (FIFO_0 and FIFO_1).The gray scale read from memory is stored in FIFO, and expansion is calculated from FIFO and reads ash
Degree, completes the FIFO space release after expansion is calculated.FIFO automatic can read when there is 4 or more free spaces from memory
Gray scale is taken, as shown in Figure 6.If a width of 8bit of gray level bit, two FIFO sizes are the FIFO of 16*8bit, i.e., can store 16
Individual gradation data.When reading external address, upper and lower two rows data are read by turns, be respectively written into two FIFO.So, storage is being read
Address needs not move through the computing of complexity during the data that device is often gone, and order Jia 1 just can be with.
In view of the randomness of interception image, need to consider to read the effective of gray scale in the data in reading memory
Property.Due to image alignment influence, often row first count gray scale need to consider to offset significance bit original image, effectively grey to the first beat of data
Degree judges.Be actually that low two truncations have been carried out to storage address due to taking location address, thus low two of storage address just
It is the significance bit for reading data.4 gradation datas read when being 2 ' b00 for low two are all effective.When being 2 ' b01 for low two
Rear 3 gradation datas for reading are effective.Rear 2 gradation datas read when being 2 ' b10 for low two are effective.It is 2 ' when low two
Last 1 gradation data read during b11 is all effective.When low two is 2 ' b00,2 ' b01, during 2 ' b10, first time gray scale reads
2 cycles are needed, afterwards streamline normal work.When being 2 ' b11 for low two, first time gray scale reads needs 4 cycles.Often
Secondary FIFO write operations write 4 FIFO gray scale memory spaces, and FIFO read operations read 2 data fifos, sentence according to location skew is taken
It is disconnected whether to discharge FIFO gray scale memory spaces.By FIFO Read-write Catrols, when data completion calculating release resource has 4 in FIFO
Individual or more available gray scale memory space reading memory data write-in FIFO, iterative cycles.Read more than FIFO because FIFO writes
Hurry up, it is ensured that subsequent pipeline each clk can read data and carry out expansion calculating from FIFO, it is ensured that streamline smoothly enters
OK.
The process of implementing is：
In first pipeline cycle of every row, following steps are performed：
(2.1a), calculate gray value f (im,jn) absolute address in memory, it is designated as row address addrOn；Calculate f
(im+1,jn) absolute address in memory, it is designated as descending address addrUnder：
addrOn=im×width_src+jm
addrUnder=(im+1)×width_src+jm
(2.2a), by upper row address addrOnWith descending address addrUnderIt is converted into binary form, and by binary form
Upper row address addrOnWith the descending address addr of binary formUnderCarry out low two truncations and obtain the up reading address of memory
addr_readOnWith descending reading address addr_readUnder；
(2.3a), according to up read pointer addr_readOnExtract a data (continuous 4 gradation datas) in memory
It is deposited into FIFO_0, up reading address addr_readOnPlus 1, FIFO_0 write addresses add 4；According to descending read pointer addr_
readUnderA data (continuous 4 gradation datas) is deposited into FIFO_1, descending reading address addr_read in extracting memoryUnder
Plus 1, FIFO_1 write addresses add 4；
(2.4a), work as addrOnLow 2 for 2 ' b11 when, by addr_readOnOne address of recursion, obtains new backward
addr_readOn, step (2.3a) is re-executed, then, step is calculated into next level production line dilatometer；Otherwise, it is directly entered
Next level production line dilatometer calculates step；
That is, as the upper row address addr of binary formOnIt is low 2, it is complete when 2 ' b00,2 ' b01 or 2 ' b10
Next level production line dilatometer can be started into above-mentioned steps (2.3a) to calculate；Work as addrOnLow 2 for 2 ' b11 when, it is necessary to from depositing
Reservoir reads data could start next level production line dilatometer calculation, it is necessary to wait 1 cycle, by above-mentioned steps (2.3a) twice
Carry out twice；
In the subsequent pipeline cycle of every row, following steps are performed：
(2.1b), by whether there is at least 4 free spaces in FIFO_0 read/write address multilevel iudges FIFO_0, if
In the presence of then up reading address addr_readOnPlus 1, a data (continuous 4 gradation datas) is read from memory and is deposited successively
Enter in FIFO_0；FIFO_0 write addresses add 4；Otherwise, wait；
(2.2b), by whether there is at least 4 free spaces in FIFO_1 read/write address multilevel iudges FIFO_1, if
In the presence of then descending reading address addr_readUnderPlus 1, a data (continuous 4 gradation datas) is read from memory and is deposited successively
Enter in FIFO_1；FIFO_1 write addresses add 4；Otherwise, wait；
The FIFO_0 and FIFO_1 are cyclic buffer, when FIFO_0 and FIFO_1 have expired, circulation storage.
3rd, expansion is calculated
Expansion is calculated according to p (i0,j0) point four gray values of point of surrounding：f(im,jn)、f(im+1,jn)、f(im,jn+1)、
f(im+1,jn+ 1), using p'(i, image intensity value j), its specific reality in the image after bilinear interpolation algorithm calculating expansion
It is now：
In first pipeline cycle of every row, following steps are performed：
(3.1a) is extracted according to row address addr on binary formOnAddress addr descending with binary formUnderIt is low by two
Position is used as the initial read address in FIFO_0 and FIFO_1；
(3.2a), read taking-up f (i address since FIFO_0m,jn)、f(im,jn+1)；Read address from FIFO_1 to open
Begin to take out f (im+1,jn)、f(im+1,jn+1)；
(3.3a), four gray values read in step (3.2a) are added after move to right 2 expanded after figure
P'(i, image intensity value j) as in：
F ' (m, n)=(f (im,jn)+f(im+1,jn)+f(im,jn+1)+f(im+1,jn+1))>>2；
Within the subsequent pipeline cycle of every row, following steps are performed：
(3.1b) works as R according to result of calculation in coordinate transformm<Width_exp, i.e. im=im-1, and Tn<Height_exp,
That is jn=jn-1When, it is constant that FIFO_0 and FIFO_1 reads address；Work as TnDuring >=height_exp, jn=jn-1+ 1, FIFO_0 and
FIFO_1 reads address and adds 1；
(3.2b), read taking-up f (i address since FIFO_0m,jn)、f(im,jn+1)；Read address from FIFO_1 to open
Begin to take out f (im+1,jn)、f(im+1,jn+1)；
(3.3b), four gray values read in step (3.2b) are added after move to right 2 expanded after figure
P'(i, image intensity value j) as in：
F ' (m, n)=(f (im,jn)+f(im+1,jn)+f(im,jn+1)+f(im+1,jn+1))>>2；
It is above-mentioned to remove 2 operations also by moving to right 1 to realize during this hardware algorithmization.
4th, gray scale storage
The p'(m obtained by calculating will be expanded, image intensity value f ' (m, n) n) is preserved into specified memory, that is, scheme
Memory 2 in 3.
When after expanding image being interception image, typically intercepted between two parties on image upon inflation, for adjusting image resolution
Rate.Interception image size is width_icpt × height_icpt.Interception area matrix coordinate range wide:(width_exp-
Width_icpt)/2, (width_exp+width_icpt)/2；Matrix coordinate range high:(height_exp-height_
Icpt)/2, (height_exp+height_icpt)/2.Only need to calculate the expanding image gray scale of the interception area.Sit
Mark conversion first pixel mapping point in artwork of the first row since interception image is calculated the number of row first, interception figure
As often first pixel of row maps ordinate unanimously in artwork, expanding image ash is calculated according to above-mentioned pipeline system afterwards
Degree.
Embodiment
Present invention FPGA realizations under Xilinx virtex5-XC5VFX100T, are operated in 100M.To original image 160*
128,1.2 times, i.e. 192*153 are expanded, then the image that original template Fig. 1 .1 times sizes are 176*140 is intercepted in expanding image, it is complete
0.25ms is only needed into algorithm computing.
The above, optimal specific embodiment only of the invention, but protection scope of the present invention is not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can be readily occurred in,
Should all be included within the scope of the present invention.
The content not being described in detail in description of the invention belongs to the known technology of professional and technical personnel in the field.
Claims (7)
1. a kind of infrared image linear interpolation expands hardware processing method, and the method is realized using hardware, is accelerated at image expansion
Reason speed, it is characterised in that：Artwork is carried out into expansion first and amplifies the image after being expanded, then to every in image after expansion
Individual pixel p' performs following steps：
(1), coordinate is calculated, the coordinate p'(m in p' upon inflation image coordinate system, and n) the anti-point that pushes away is in artwork coordinate system
Coordinate p (i0,j0), to p (i0,j0) coordinate value carry out rounding operation, obtain nearest apart from p points upper left point in artwork and sit
Mark (im,jn)；The origin of coordinates of image coordinate system is the image upper left corner after expansion after the expansion, and the upper left corner is to the right expansion
Image coordinate system transverse axis X-axis positive direction afterwards, the upper left corner is downwards image coordinate system longitudinal axis Y positive directions after expansion, and the artwork is sat
The origin of coordinates for marking system is the upper left corner of artwork, and the upper left corner is to the right artwork coordinate system transverse axis X-axis positive direction, and the upper left corner is downwards
Artwork coordinate system longitudinal axis Y-axis positive direction.
(2), gray scale is read, and p (i in artwork are obtained from artwork memory0,j0) point four gray values of point of surrounding：f(im,jn)、
f(im+1,jn)、f(im,jn+1)、f(im+1,jn+ 1) continuous two groups of gradation datas, will be stored and is stored in two internal FIFO respectively
In, the f (x, y) is the gradation data at coordinate (x, y) place in original image；
(3), expansion is calculated, and p (i are read out from two FIFO0,j0) point four gray values of point of surrounding：f(im,jn)、f(im+
1,jn)、f(im,jn+1)、f(im+1,jn+ 1), using p'(i, image j) in the image after bilinear interpolation algorithm calculating expansion
Gray value；
(4), gray scale storage, the image intensity value that step (3) is calculated is saved in after expanding in the corresponding memory of image,
Update after expansion p'(i, image intensity value j) in image.
2. hardware processing method is expanded according to a kind of infrared image linear interpolation in claim 1, it is characterised in that：The side
Method is realized in FPGA.
3. hardware processing method is expanded according to a kind of infrared image linear interpolation in claim 1, it is characterised in that：The step
Suddenly the coordinate of (1)~step (4) is calculated, gray scale is read, expansion is calculated, gray scale storage is realized using level Four pipeline parallel method.
4. hardware processing method is expanded according to a kind of infrared image linear interpolation in claim 1, it is characterised in that：The step
Suddenly in (1) when artwork size be width_src × height_src, after expansion the size of image be width_exp ×
During height_exp, according to coordinate p'(m in image after expansion, n) the anti-corresponding position p (i for pushing away this in artwork0,j0),
Obtain nearest apart from p points top left pixel point coordinates (i in artworkm,jn) use the method for iteration recursion for：
Work as m=0, during n=0, make i0=0, j0=0, make intermediate variable R0=0, T0=0；
When m >=1, intermediate variable R is calculatedm=Rm-1+ width_src, m ∈ { 1 ..., width_exp-1 }, if Rm<width_
Exp, then im=im-1；If Rm>=width_exp, then im=im-1+ 1, Rm=Rm-1-width_exp；
When n >=1, intermediate variable T is calculatedn=Tn-1+ height_src, n ∈ { 1 ..., height_exp-1 }, if Tn<
Height_exp, then jn=jn-1；If Tn>=height_exp, then jn=jn-1+ 1, Tn=Tn-1-height_exp。
5. hardware processing method is expanded according to a kind of infrared image linear interpolation in claim 1, it is characterised in that：Artwork is deposited
Reservoir bit wide is 4 times of pixel gray value width, one address memory space of every four pixel gray values correspondence, its storage
Address is：(ordinate x × original image width width_src+ abscissas y)>>The width of 2, two FIFO is pixel ash
The width of angle value, depth is more than or equal to 16.
6. a kind of infrared image linear interpolation according to claim 5 expands hardware processing method, it is characterised in that gray scale
Read the process that implements be：
In first pipeline cycle of every row, following steps are performed：
(2.1a), calculate gray value f (im,jn) absolute address in memory, it is designated as row address addrOn；Calculate f (im+
1,jn) absolute address in memory, it is designated as descending address addrUnder：
addrOn=im×width_src+jm
addrUnder=(im+1)×width_src+jm
(2.2a), by upper row address addrOnWith descending address addrUnderIt is converted into binary form, and by the upper of binary form
Row address addrOnWith the descending address addr of binary formUnderCarry out low two truncations and obtain the up reading address addr_ of memory
readOnWith descending reading address addr_readUnder；
(2.3a), according to up read pointer addr_readOnContinuous 4 gradation datas are deposited into FIFO_0 in extracting memory,
Up reading address addr_readOnPlus 1, FIFO_0 write addresses add 4；According to descending read pointer addr_readUnderIn extraction memory
Continuous 4 gradation datas are deposited into FIFO_1, descending reading address addr_readUnderPlus 1, FIFO_1 write addresses add 4；
(2.4a), work as addrOnLow 2 for 2 ' b11 when, by addr_readOnOne address of recursion, obtains new addr_ backward
readOn, step (2.3a) is re-executed, then, step is calculated into next level production line dilatometer；Otherwise, it is directly entered next
Level production line expands calculation procedure；
In the subsequent pipeline cycle of every row, following steps are performed：
(2.1b), judge to whether there is at least 4 free spaces in FIFO_0, if it is present up reading address addr_
readOnPlus 1, continuous 4 gradation datas are read from memory and is sequentially stored into in FIFO_0；FIFO_0 write addresses add 4；It is no
Then, wait；
(2.2b), judge to whether there is at least 4 free spaces in FIFO_1, if it is present descending reading address addr_
readUnderPlus 1, continuous 4 gradation datas are read from memory, be sequentially stored into FIFO_1；FIFO_1 write addresses add 4；It is no
Then, wait；
The FIFO_0 and FIFO_1 are cyclic buffer, when FIFO_0 and FIFO_1 have expired, circulation storage.
7. hardware processing method is expanded according to a kind of infrared image linear interpolation in claim 6, it is characterised in that dilatometer
That calculates is implemented as：
In first pipeline cycle of every row, following steps are performed：
(3.1a), according to row address addr on binary formOnAddress addr descending with binary formUnderLow two conducts
Initial read address in FIFO_0 and FIFO_1；
(3.2a), read taking-up f (i address since FIFO_0m,jn)、f(im,jn+1)；Taken out reading address since FIFO_1
f(im+1,jn)、f(im+1,jn+1)；
(3.3a), four gray values read in step (3.2a) are added after move to right 2 expanded after image in
P'(i, image intensity value j)：
F ' (m, n)=(f (im,jn)+f(im+1,jn)+f(im,jn+1)+f(im+1,jn+1))>>2；
Within the subsequent pipeline cycle of every row, following steps are performed：
(3.1b), according to result of calculation in coordinate transform in step (2), work as Rm<Width_exp, i.e. im=im-1, and Tn<
Height_exp, i.e. jn=jn-1When, it is constant that FIFO_0 and FIFO_1 reads address；Work as TnDuring >=height_exp, jn=jn-1+ 1,
FIFO_0 and FIFO_1 reads address and adds 1；
(3.2b), read taking-up f (i address since FIFO_0m,jn)、f(im,jn+1)；Taken out reading address since FIFO_1
f(im+1,jn)、f(im+1,jn+1)；
(3.3b), four gray values read in step (3.2b) are added after move to right 2 expanded after image in
P'(i, image intensity value j)：
F ' (m, n)=(f (im,jn)+f(im+1,jn)+f(im,jn+1)+f(im+1,jn+1))>>2。
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| CN109146804A (en) * | 2018-07-26 | 2019-01-04 | 南京航空航天大学 | A kind of SAR image correction method for geometric distortion based on FPGA |
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