CN106767921B - A kind of implementation method for fibre optic gyroscope test circuit FPGA - Google Patents
A kind of implementation method for fibre optic gyroscope test circuit FPGA Download PDFInfo
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- CN106767921B CN106767921B CN201611179366.5A CN201611179366A CN106767921B CN 106767921 B CN106767921 B CN 106767921B CN 201611179366 A CN201611179366 A CN 201611179366A CN 106767921 B CN106767921 B CN 106767921B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C25/00—Manufacturing, calibrating, cleaning, or repairing instruments or devices referred to in the other groups of this subclass
- G01C25/005—Manufacturing, calibrating, cleaning, or repairing instruments or devices referred to in the other groups of this subclass initial alignment, calibration or starting-up of inertial devices
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Abstract
The invention discloses a kind of FPGA implementation methods for optical fibre gyro test circuit, and by modularized design, FPGA realizes the function that serial ports reception, data smoothing, temperature acquisition, data buffer storage, serial ports are sent.Serial ports receives baud rate, check bit, data smoothing number, the width and depth for caching FIFO, by the parameter setting realization in FPGA design code, parameter setting can receive the fibre optic gyroscope serial ports output of different timing after the completion for the baud rate for sending data, check bit.The present invention is versatile, solves the test problem of the fibre optic gyroscope of different output timings.
Description
Technical field
The present invention relates to a kind of implementation methods for fibre optic gyroscope test circuit FPGA.
Background technique
Fibre optic gyroscope is used to measure the angular speed of inertial space, and one of output form of angular rate data is serial port-shaped
Formula, fibre optic gyroscope is externally sent under different situations baud rate, check bit are different, cause the test job of fibre optic gyroscope difficult
Degree is big；Simultaneously because fibre optic gyroscope is temperature sensor, when test, needs combination temperature data to carry out angular rate data
Analysis, therefore it is badly in need of a kind of flexible, general test method, the fibre optic gyroscope of different sequential exports is received, while can adopt
Collect temperature data.There are no this methods in the prior art.
Summary of the invention
The object of the present invention is to provide a kind of FPGA implementation methods for fibre optic gyroscope test circuit, pass through modularization
Design can test the fibre optic gyroscope of different output timings, implementation method letter by the parameter setting in FPGA design code
It is single quick, it is versatile.
The present invention is achieved by the following technical programs: a kind of realization side FPGA for fibre optic gyroscope test circuit
Method the described method comprises the following steps:
Step 1: the serial ports receiving unit reception optical fiber gyroscope angular rate data sends the angular rate data
To the data smoothing unit；
Step 2: the data smoothing unit receives the angular rate data, and will obtain after angular rate data smoothing processing
It is sent to the data buffer storage unit to average angular rate data and by the average angular rate data, while output smoothing is completed
Marking signal, and the smooth complement mark signal is exported to the temperature collecting cell；
Step 3: the temperature collecting cell receives temperature collection after the smooth complement mark signal, and temperature is sent out
Give the data buffer storage unit；
Step 4: it after the data buffer storage unit reception average angular rate data and the temperature and stores, and will
The average angular rate data and the temperature are exported to the data transmission unit；
Step 5: the average angular rate data and the temperature are sent to PC machine by the data transmission unit.
In the above-mentioned FPGA implementation method for fibre optic gyroscope test circuit, in step 1, serial ports receiving unit is connect
Receiving fibre optic gyroscope angular rate data includes: input of the serial ports receiving unit according to reception baud rate clock division parameter to FPGA
Clock is divided, and is obtained serial ports and is received baud rate clock, receive baud rate clock it is enabled under successively receive serial data
Start bit, a byte data position, check bit sum stop position, check bit is judged, one byte when check bit is correct
Data are received as correct byte data；Each correct byte data arrival hour counter adds 1；Counter receives when being 0
Frame head, counter receive 3 byte angular rate datas when being 1-3, receive postamble when being 4；When the frame head and postamble that receive are correct
When, the angular rate data received is sent to data smoothing module by serial ports receiving module.
In the above-mentioned FPGA implementation method for fibre optic gyroscope test circuit, in step 2, angular rate data is smooth
Processing includes: 2 receivedNA angular rate data is added up to obtain angular speed accumulated value, and angular speed accumulated value is divided by 2NIt obtains
Average angular rate data.
In the above-mentioned FPGA implementation method for fibre optic gyroscope test circuit, in step 3, the temperature acquisition list
First output temperature acquires clock, after receiving smooth complement mark signal under each acquisition clock temperature collection.
In the above-mentioned FPGA implementation method for fibre optic gyroscope test circuit, in step 4, the data buffer storage list
It is n, storage depth 2 that member, which stores the average angular rate data and temperature data that receive to data width,mCaching FIFO
In, the data of caching are exported to the data transmission unit when caching in FIFO is non-empty.
In the above-mentioned FPGA implementation method for fibre optic gyroscope test circuit, in step 5, the data send single
Member leads clock division parameter according to send wave spy and is divided to obtain serial ports transmission baud rate clock to the input clock of FPGA,
Send baud rate clock it is enabled under the average angular rate data of data cache module and temperature data are passed through into serial ports transmission.
The invention has the following advantages over the prior art:
1) the reception baud rate clock of serial ports receiving unit of the invention and check bit can be arranged in FPGA code, therefore
The fibre optic gyroscope of different sequential exports can be tested, implementation method is flexibly and fast, versatile；
2) data smoothing unit of the invention makes data smoothing, guarantees that data stabilization is reliable；
3) the baud rate clock of data transmission unit data of the invention transmission, check bit can be arranged in FPGA code,
Different data can be met and send demand.
Detailed description of the invention
Fig. 1 is the functional block diagram that optical fibre gyro tests circuit FPGA implementation method；
Fig. 2 is that optical fibre gyro tests circuit FPGA function module configuration parameter explanatory diagram；
Fig. 3 is the interface schema that optical fibre gyro tests circuit FPGA and A/D chip；
Fig. 4 is fibre optic gyroscope hardware block diagram.
Specific embodiment
The present invention is described in further detail below in conjunction with the accompanying drawings:
Fibre optic gyroscope is used to measure the angular speed of inertial space, and hardware block diagram is as shown in figure 4, its angular speed number
According to one of output form be serial port form.One frame data of serial ports end periodicity sending, data frame format be a byte frame head,
Three byte angular rate data words and a byte postamble.The baud rate that data are sent is usually 115200bps or 230400bps,
It include a start bit, a byte data position, a bit check position and a stop position when each byte data is sent.
The present embodiment provides a kind of FPGA implementation methods of fibre optic gyroscope test circuit, as shown in Fig. 2, passing through modularization
Design, the parameter of each functional module is arranged in FPGA code, can test the fibre optic gyroscope of different output timings.
A kind of FPGA implementation method of fibre optic gyroscope test circuit is illustrated below in conjunction in Fig. 1:
Step 1: angular rate data is sent to data and put down by 1 reception optical fiber gyroscope angular rate data of serial ports receiving unit
Sliding unit 2.
Specifically, serial ports receiving unit 1 divides the input clock of FPGA according to baud rate clock division parameter is received
Frequently, obtain serial ports and receive baud rate clock, receive baud rate clock it is enabled under successively receive serial data start bit, one
A byte data position, check bit sum stop position, judge check bit, and one byte data is as correct when check bit is correct
Byte data be received；
Each correct byte data arrival hour counter value adds 1；Counter receives frame head when being 0, counter connects when being 1-3
3 byte angular rate datas are received, receive postamble when being 4；When the frame head and correct postamble received, serial ports receiving module will be received
To angular rate data be sent to data smoothing module.
Step 2: data smoothing unit 2 receives angular rate data, and will obtain average angle after angular rate data smoothing processing
Average angular rate data are simultaneously sent to data buffer storage unit 4, while output smoothing complement mark signal by speed data, and will be put down
Sliding complement mark signal is exported to temperature collecting cell 3；
Specifically, angular rate data smoothing processing includes: 2 receivedNA angular rate data is added up to obtain angle speed
Rate accumulated value, angular speed accumulated value is divided by 2NObtain average angular rate data.
Step 3: temperature collecting cell 3 receives temperature collection after smooth complement mark signal, and sends a temperature to data
Cache unit 4.
Specifically, temperature acquisition is realized by the data of acquisition chip AD7686, interface such as Fig. 3 institute of AD7683 and FPGA
Show.Temperature collecting cell 3 exports chip selection signal CS and acquisition clock DCLOCK to AD7683, is receiving smooth complement mark signal
Afterwards in the Dout output of each acquisition clock DCLOCK acquisition AD7683, the data sampling time sequence of AD7683 can be found in the chip
User's manual.
Step 4: data buffer storage unit 4 is received after average angular rate data and temperature and is stored, and by average angular rate number
It exports according to temperature to data transmission unit 5.
Specifically, data buffer storage unit 4 stores the average angular rate data and temperature data that receive to data width
For n, storage depth 2mCaching FIFO in, the data of caching are exported when caching in FIFO is non-empty sent to data it is single
Member 5.
Step 5: average angular rate data and temperature are sent to PC machine by data transmission unit 5.
Specifically, data transmission unit 5 divides the input clock of FPGA according to baud rate clock division parameter is sent
Frequency obtains serial ports and sends baud rate clock, send baud rate clock it is enabled under by the average angular rate number of data cache module
It is sent according to temperature data by serial ports.
The present embodiment is by testing the angular rate data and temperature that circuit FPGA acquires fibre optic gyroscope using optical fibre gyro
Data, serial ports receive baud rate clock, check bit, the smooth number of angular rate data；The width and storage depth of FIFO；Send number
According to baud rate clock, check bit can be programmed and be modified by FPGA, therefore the fibre optic gyroscope of different sequential exports can be tested, together
When can temperature collection data, implementation method is flexibly and fast, versatile.
Embodiment of the present invention is described further with a specific embodiment below.
Assuming that the frame format of fibre optic gyroscope output angular rate data is the high byte of x " 53 " (frame head), angular rate data
Data, middle byte data, low byte data and x " 45 " (postamble), output baud rate are 115200bps, the verification of each byte
Position is even parity check, and the input clock that optical fibre gyro tests circuit FPGA is 11.0592MHz, and smooth number requires to be 128, caching
FIFO requirement width is 8Bits and depth is 1024, and the baud rate for sending data requires to be 230400bps, each word of transmission
Section check bit is odd.
By calculating, by 11.0592 × 10696 are obtained divided by 115200, baud rate clock division parameter is received and is set as
96,11.0592 × 10648 are obtained divided by 230400；Therefore it is as follows that each parameter is set in FPGA design code:
Serial ports receiving unit: receiving baud rate clock division parameter is 96, and receiving checking parameter is 0, a byte frame head
Data are x " 53 ", and byte postamble is x " 45 ", the output data frame format of corresponding fibre optic gyroscope be x " 53 " (frame head),
High byte data, middle byte data, low byte data and the x " 45 " (postamble) of angular rate data；Data export baud rate
115200bps, the check bit of each byte are even parity check, data smoothing unit: data smoothing number 2NIt is set as 27, i.e. N=7,
Corresponding smooth number is 128；
Data buffer storage unit: data width is set as n=8, storage depth 210=1024, i.e. n=8, m=10, it is corresponding
The width for caching FIFO is 8Bits, depth 1024；
Data transmission unit: sending baud rate clock division parameter and be set as 48, sends checking parameter and is set as 1, data
Transmission baud rate is 230400bps, and each byte check bit of transmission is odd.
Above-mentioned parameter can be used for after the FPGA code of fibre optic gyroscope test circuit is provided with to the fibre optic gyroscope
Test.
The reception baud rate clock and check bit of serial ports receiving unit of the invention can be arranged in FPGA code, therefore can
The fibre optic gyroscope of different sequential exports is tested, implementation method is flexibly and fast, versatile；Data smoothing unit of the invention makes
Data smoothing is obtained, guarantees that data stabilization is reliable；The baud rate clock of data transmission unit data transmission of the invention, check bit can
It is arranged in FPGA code, different data can be met and send demand.
Embodiment described above is the present invention more preferably specific embodiment, and those skilled in the art is in this hair
The usual variations and alternatives carried out in bright technical proposal scope should be all included within the scope of the present invention.
Claims (6)
1. a kind of FPGA implementation method for fibre optic gyroscope test circuit, which is characterized in that the method includes following steps
It is rapid:
Step 1: the angular rate data is sent to data by serial ports receiving unit (1) reception optical fiber gyroscope angular rate data
Smooth unit (2)；
Step 2: the data smoothing unit (2) receives the angular rate data, and will obtain after angular rate data smoothing processing
The average angular rate data are simultaneously sent to data buffer storage unit (4) by average angular rate data, while output smoothing completes mark
Will signal, and the smooth complement mark signal is exported and gives temperature collecting cell (3)；
Step 3: the temperature collecting cell (3) receives temperature collection after the smooth complement mark signal, and temperature is sent
Give the data buffer storage unit (4)；
Step 4: the data buffer storage unit (4) receives after the average angular rate data and the temperature and stores, and by institute
It states average angular rate data and the temperature exports and gives data transmission unit (5)；
Step 5: the average angular rate data and the temperature are sent to PC machine by the data transmission unit (5).
2. the FPGA implementation method according to claim 1 for fibre optic gyroscope test circuit, it is characterised in that: in step
In rapid one, serial ports receiving unit (1) reception optical fiber gyroscope angular rate data includes:
Serial ports receiving unit (1) divides the input clock of FPGA according to baud rate clock division parameter is received, and is gone here and there
Mouthful receive baud rate clock, receive baud rate clock it is enabled under successively receive the start bit of serial data, a byte number
According to position, check bit sum stop position, check bit is judged, one byte data is as correct byte number when check bit is correct
According to being received；
Each correct byte data arrival hour counter adds 1；Counter receives frame head when being 0, counter receives 3 words when being 1-3
Angular rate data is saved, receives postamble when being 4；When the frame head and correct postamble received, serial ports receiving module will be received
Angular rate data is sent to data smoothing module.
3. the FPGA implementation method according to claim 1 for fibre optic gyroscope test circuit, it is characterised in that: in step
In rapid two, angular rate data smoothing processing includes: 2 receivedNA angular rate data is added up to obtain angular speed accumulated value,
Angular speed accumulated value is divided by 2NObtain average angular rate data.
4. the FPGA implementation method according to claim 1 for fibre optic gyroscope test circuit, it is characterised in that: in step
In rapid three, temperature collecting cell (3) output temperature acquires clock, in each acquisition after receiving smooth complement mark signal
Temperature collection under clock.
5. the FPGA implementation method according to claim 1 for fibre optic gyroscope test circuit, it is characterised in that: in step
In rapid four, the data buffer storage unit (4), which stores the average angular rate data and temperature data that receive to data width, is
N, storage depth 2mCaching FIFO in, when cache FIFO in be non-empty when by the data of caching export give the data send
Unit (5).
6. the FPGA implementation method according to claim 1 for fibre optic gyroscope test circuit, it is characterised in that: in step
In rapid five, the data transmission unit (5) divides the input clock of FPGA according to baud rate clock division parameter is sent
Obtain serial ports and send baud rate clock, send baud rate clock it is enabled under by the average angular rate data of data cache module
It is sent with temperature data by serial ports.
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| CN201130428Y (en) * | 2007-12-29 | 2008-10-08 | 上海亨通光电科技有限公司 | Optic fiber gyroscope data acquisition model based on FPGA |
| CN102760111B (en) * | 2012-06-27 | 2015-05-20 | 浙江大学 | FPGA-based (Field Programmable Gate Array) extended multi-serial port device and data receiving-transmitting method thereof |
| CN103279058B (en) * | 2013-05-04 | 2015-05-20 | 北京航空航天大学 | Optical fiber IMU (inertial measurement unit) data collecting system for unmanned aerial vehicle electric power routing inspection |
| CN104132663A (en) * | 2014-05-27 | 2014-11-05 | 北京遥测技术研究所 | FPGA based navigation computer co-processor |
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