CN106716384A - Data shuffling apparatus and method - Google Patents

Abstract

Disclosed in an embodiment of the present invention is a data shuffling apparatus, the apparatus comprising: a cache module and a shuffling module; the cache module and the shuffling module are in a communication connection; the cache module is used for caching a first address and an address offset of each data in a data collection to be shuffled; the shuffling module is used to calculate a second address of each data according to the first address and the address offset of each data, the second address being used to indicate a storage location of each shuffled data in a storage chip; the shuffling module is used to perform data interaction according to the second address and the storage chip, in order to adjust a data sequence of the data collection to be shuffled and thereby obtain a shuffled data collection. Also provided in the embodiment of the present invention is a data shuffling method. The embodiment of the present invention directly conducts a data shuffling operation in random access memory, saves a large amount of computing resources in a central processing unit (CPU), and reduces data processing time delay.

Description

A kind of device and method of data shuffling Technical field

The present invention relates to computer realm, more particularly to a kind of device and method of data shuffling.

Background technology

With the continuous progress of technology, require that the parallel treatment technology of Multi-core also develops therewith in most of fields, in parallel processing due between each step in parallel granularity or dimension it is different, therefore usually require to shuffle the data in internal memory, shuffle process refers to that the element in gathering one is resequenced, such as by array { a, b, c, d, e } by different specified shuffle operations, realize the function that array element is arbitrarily exchanged, new array is obtained, such as：{ b, e, d, a, c }.

In the prior art, realize shuffle operation process approximately as described：

1st, central processing unit (CPU, Central Processing Unit) reads the data for needing to carry out shuffle operation from internal memory；

2nd, CPU, which is called, shuffles function completion shuffle operation；

3rd, CPU writes back the data for carrying out shuffle operations in internal memory.

The present inventor has found in the research of above-mentioned prior art and practice process, because shuffle operation is realized by CPU, CPU computing resource can be taken, and the read-write operation of internal memory will be carried out respectively by shuffling beginning and end, therefore when the data volume shuffled is very big, data transmission period that then will be longer, and need to open up caching array space, when cache memory space inside CPU is not enough, then need caching array being put into internal memory, the read-write number of times of internal memory can so be increased, the processing delay of whole operation is further increased.

The content of the invention

The embodiments of the invention provide a kind of device and method of data shuffling, it may not be necessary to is realized in the processor outside mixed washing apparatus and shuffles process, saves substantial amounts of computing resource in processor, reduces data processing time delay.

First aspect present invention provides a kind of device of data shuffling, and described device is applied to the buffer chip of internal memory, and the internal memory also includes storage chip, and described device includes：Cache module and shuffle module；

The cache module is communicated to connect with the shuffle module；

The cache module is used to cache the address offset amount for treating the first address of each data and each data in shuffling data set；

The shuffle module is used for the first address and the address offset amount of each data according to each data, the second address for obtaining each data is calculated, second address is used to indicate storage location of each data after shuffling in the storage chip；

The shuffle module is used to carry out data interaction according to second address and the storage chip, realizes to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

With reference to first aspect, in the first possible implementation, the cache module is address caching module, the address caching module is communicated to connect with the shuffle module, and the address caching module is used to cache the address offset amount for treating the first address of each data and each data in shuffling data set；Or,

The cache module includes address caching module and control cache module, and the address caching module is used to cache the first address for treating each data in shuffling data set, and the control cache module is used for the address offset amount for caching each data；Or,

The cache module includes address caching module and skew cache module, and the address caching module is used to cache the first address for treating each data in shuffling data set, and the skew cache module is used for the address offset amount for caching each data.

With reference to first aspect or first aspect the first possible implementation, in second of possible implementation, the shuffle module is used to carry out data interaction according to second address and the storage chip, realize to the adjustment for treating data order in shuffling data set, data acquisition system after being shuffled, can include：

The shuffle module is used for the second address that shuffling data set and each data are treated described in storage chip transmission, so that the storage chip treats the corresponding storage location in the second address that shuffling data writes each data according to the second address of each data by described, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

With reference to first aspect or first aspect the first possible implementation, in the third possible implementation, the shuffle module is used to carry out data interaction according to second address and the storage chip, realize to the adjustment for treating data order in shuffling data set, data acquisition system after being shuffled, can include：

The shuffle module is used for the second address that each data are transmitted to the storage chip, so that second address of the storage chip according to each data, each data are read from the corresponding storage location in the second address of each data, realization treats data order in shuffling data set to described Adjustment, the data acquisition system after being shuffled.

With reference to first aspect or first aspect the first to the third any possible implementation, in the 4th kind of possible implementation, the shuffle module can include：Mode Selection register,

The Mode Selection register shuffles switch control word for acquisition, and the switch control word that shuffles is turned on and off data shuffling function for instruction；

When it is described shuffle switch control word and indicate to open the data shuffling function when, the Mode Selection register is used for the address offset amount that each data are obtained from the cache module.

With reference to first aspect or first aspect the first to the 4th kind of any possible implementation, in the 5th kind of possible implementation, the absolute value for treating the address offset amount of each data in shuffling data set is both less than the size for the total memory space for being used to store each data, and the address offset amount sum of each data is zero.

With reference to the 4th kind of possible implementation of first aspect, in the 6th kind of possible implementation, the internal memory also includes being configured with the layout line being connected with the Mode Selection register in bus, the bus,

Described layout line one end is connected with the Mode Selection register, and the other end is connected by the slot of the internal memory with the chip beyond the internal memory；

The Mode Selection register shuffles switch control word for acquisition, including：

The Mode Selection register is used to shuffle switch control word by the described of layout line reception user configuring.

With reference to first aspect or first aspect the first to the 6th kind of any possible implementation, in the 7th kind of possible implementation, the shuffle module is used for the first address and the address offset amount of each data according to each data, the second address for obtaining each data is calculated, including：

The shuffle module is used for call address mapping function, the second address for obtaining each data is calculated, the address mapping function is the second address of each data and the first address of each data and the mapping relations of the address offset amount sum of each data.

Second aspect of the present invention provides a kind of method of data shuffling, and methods described is applied to the buffer chip of internal memory, and the internal memory also includes storage chip, including：

Obtain the address offset amount for treating the first address of each data and each data in shuffling data set；

According to the first address of each data and the address offset amount of each data, the second address for obtaining each data is calculated, second address is used to indicate each data after shuffling described Storage location in storage chip；

Data interaction is carried out according to second address and the storage chip, realized to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

It is described that data interaction is carried out according to second address and the storage chip in the first possible implementation with reference to second aspect, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled can include：

To the second address that shuffling data set and each data are treated described in storage chip transmission, so that the storage chip treats the corresponding storage location in the second address that shuffling data writes each data according to the second address of each data by described, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

It is described that data interaction is carried out according to second address and the storage chip in second of possible implementation with reference to second aspect, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled can include：

The second address of each data is transmitted to the storage chip, so that second address of the storage chip according to each data, from the second address of each data, corresponding storage location reads each data, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

With reference to second aspect, second aspect the first or second of possible implementation, in the third possible implementation, the acquisition treats that the first address of each data and the address offset amount of each data can include in shuffling data set：

Switch control word is shuffled in acquisition, and the switch control word that shuffles is turned on and off data shuffling function for instruction；

When it is described shuffle switch control word and indicate to open the data shuffling function when, obtain the first address of each data and the address offset amount of each data.

With reference to second aspect, second aspect the first to the third any possible implementation, in the 4th kind of possible implementation, first address and the address offset amount of each data according to each data, the second address for obtaining each data is calculated, can be included：

Call address mapping function, calculates the second address for obtaining each data, and the address mapping function is the second address of each data and the first address of each data and each data Address offset amount sum mapping relations.

Third aspect present invention provides a kind of device of data shuffling, including：

Acquisition module, the address offset amount of the first address of each data and each data in shuffling data set is treated for obtaining；

Computing module, for the first address according to each data and the address offset amount of each data, calculates the second address for obtaining each data, second address is used to indicate storage location of each data after shuffling in the storage chip；

Adjusting module, for carrying out data interaction according to second address and the storage chip, is realized to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

With reference to the third aspect of the embodiment of the present invention, in the first possible implementation, the adjusting module can include：

First transmission unit, for treating the second address of shuffling data set and each data described in being transmitted to the storage chip, so that the storage chip treats the corresponding storage location in the second address that shuffling data writes each data according to the second address of each data by described, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

With reference to the third aspect of the embodiment of the present invention, in second of possible implementation, the adjusting module includes：

Second transmission unit, the second address for transmitting each data to the storage chip, so that second address of the storage chip according to each data, from the second address of each data, corresponding storage location reads each data, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

With reference to the third aspect, the third aspect the first or second of possible implementation, in the third possible implementation, the acquisition module can include：

First acquisition unit, shuffles switch control word, the switch control word that shuffles is turned on and off data shuffling function for instruction for obtaining；

Second acquisition unit, for when it is described shuffle switch control word and indicate to open the data shuffling function when, obtain the first address of each data and the address offset amount of each data.

With reference to the third aspect, the third aspect the first to the third any possible implementation, in the 4th kind of possible implementation, the computing module can include：

Computing unit, for call address mapping function, the second address for obtaining each data is calculated, the address mapping function is the second address of each data and the first address of each data and the mapping relations of the address offset amount sum of each data.

As can be seen from the above technical solutions, the embodiment of the present invention has advantages below：

In the embodiment of the present invention, the device of the data shuffling of offer apply with the cache chip of internal memory, need the buffer chip in improved only internal memory, rather than the construction of whole internal memory, therefore implement more simple, simultaneously, the function of shuffling of the device is by hard-wired in internal memory, carried out simultaneously along with the process of reading and writing data again, need not by internal memory outside processor complete said process, it so can largely save the computing resource of processor, especially alleviate CPU work load, also largely reduce the time delay of data processing, when data volume is larger, further embody the short advantage of data transmission period.

Brief description of the drawings

Technical scheme in order to illustrate the embodiments of the present invention more clearly, the accompanying drawing used required in being described below to embodiment is briefly described, apparently, drawings in the following description are only some embodiments of the present invention, for those skilled in the art, on the premise of not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.

Fig. 1 is internal memory schematic diagram in the embodiment of the present invention；

Fig. 2 is the internal structure schematic diagram of storage chip in the embodiment of the present invention；

Fig. 3 is the shuffle module schematic diagram increased newly in buffer chip in the embodiment of the present invention；

Fig. 4 is the structure of shuffle module in the embodiment of the present invention；

Fig. 5 is the function control word schematic diagram of Mode Selection register in the embodiment of the present invention；

Fig. 6 is data shuffling performed by the device of data shuffling in the embodiment of the present invention and the process schematic of write-in；

Fig. 7 is data shuffling performed by the device of data shuffling in the embodiment of the present invention and the process schematic read；

Fig. 8 is method one embodiment schematic diagram of data shuffling in the embodiment of the present invention；

Fig. 9 is device one embodiment schematic diagram of data shuffling in the embodiment of the present invention；

Figure 10 is another embodiment schematic diagram of the device of data shuffling in the embodiment of the present invention；

Figure 11 is another embodiment schematic diagram of the device of data shuffling in the embodiment of the present invention；

Figure 12 is another embodiment schematic diagram of the device of data shuffling in the embodiment of the present invention；

Figure 13 is another embodiment schematic diagram of the device of data shuffling in the embodiment of the present invention；

Figure 14 is one structural representation of device of data shuffling in the embodiment of the present invention.

Embodiment

The embodiment of the present invention provides a kind of method of data shuffling, can save substantial amounts of computing resource in processor, reduces data processing time delay.The embodiment of the present invention additionally provides the device of corresponding data shuffling.It is described in detail individually below.

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those skilled in the art are obtained under the premise of creative work is not made belongs to the scope of protection of the invention.

Fig. 1 is internal memory schematic diagram, referring to Fig. 1, the data shuffling process in the embodiment of the present invention is carried out in internal memory.Internal memory is made up of several storage chips and a buffer chip.

It should be noted that 8 storage chips in Fig. 1 are a signal, in actual applications, the number to storage chip is not specifically limited.

Internal memory is to connect CPU and the passage of other equipment, and play a part of buffering and data exchange, when CPU works, need to read data from the external memory storages such as hard disk, but be due to external memory storage memory capacity it is larger, and apart from CPU position farther out, therefore the speed of transmission data will slow down, causing CPU operating efficiency reduces, in order to solve this problem, then internal memory is established between external memory storage and CPU, and the content that internal memory is depended on internal memory, all external memory storages is required for acting on by internal memory competence exertion.

Some programs used in everyday, for example, Windows XP systems, typewriting software and Games Software etc., typically all it is arranged on the external memory storages such as hard disk, but only this can not use its function, they must be called in in internal memory operation could really realize its function, therefore generally want the mass data of persistence to be stored in external memory storage, and some temporarily or a small amount of data and program be placed in internal memory.

Fig. 2 is the internal structure schematic diagram of storage chip, referring to Fig. 2, storage chip is located in internal memory in the embodiment of the present invention.Wherein each storage chip is made up of several storage arrays, and each storage array arranges the two-dimensional storage array constituted by multiple rows with multiple, and one row of each storage array correspondence delays Rush device, the storage size of line buffer just corresponds to the storage size in storage array per a line, each storage array further comprises the corresponding data cache module of storage chip external interface and address caching module simultaneously, data cache module be used for by some data it is temporary be saved for read and read again, and address caching module temporarily saves the corresponding address of data, it can be used for calling.The bit wide of data cache module is generally much less than the bit wide of line buffer, this be due to data/address bus bit wide it is limited, data/address bus is responsible for transmission of the Computer Data between each part, data-bus width refers to the width transmitted in each Data within the chip, and data-bus width then determines the information content of a data transfer between CPU and L2 cache, internal memory and input or output equipment, for example, CPU data-bus width is exactly 64, the maximum that then it can once transmit data is 64, i.e., can once handle 8 bytes.

It should be noted that 2 storage arrays in Fig. 2 are a signals, in actual applications, the storage array number in storage chip is not specifically limited.

Process of the storage chip when reading data is as follows：

Row information in address information determines the position of correspondence row in corresponding storage array, and the data of full line are write in line buffer；

Column information in address information determines the position of respective column in corresponding line buffer, determines after storage location, and data therein are put into data cache module；

It is output to from data cache module outside storage chip.

Process of the storage chip when writing data is as follows：

Data message and address information by storage chip outside interface enter correspondence storage array data cache module and address caching module in；

Column information in address information, refreshes the data of respective column in line buffer,

Row information in address information, by the Refresh Data of whole line buffer into corresponding row.

Therefore, the read-write of storage array is written and read in units of a full line every time, has arrived after line buffer and the read-write of specific memory cell is just carried out according to specific column address.

According to the design feature of internal memory, the present invention proposes a kind of scheme that data shuffling is directly realized by the internal memory of computer, i.e., increase a shuffle module on the buffer chip of internal memory, realize and shuffle function during reading and writing data.

Fig. 3 is the shuffle module schematic diagram increased newly in buffer chip, referring to Fig. 3, being wrapped in buffer chip Bus interface module, data cache module, control cache module, address caching module and shuffle module are included, in fact, cache chip can also include skew cache module.Wherein, bus interface module is interrelated for being realized between distinct device, commonly use one group of circuit, configuration is with appropriate interface circuit, it is connected with each part and ancillary equipment, and the HW highway that information is transmitted between all parts is referred to as bus, the bus of computer can be divided into data/address bus (DB, Data Bus), controlling bus (CB, Control Bus) and address bus (AB, Address Bus), buffer chip main function is to realize to cache and shaping DB, CB and AB signal.

It should be noted that, above-mentioned control cache module its main function referred to is cache control signal and clock signal, in control signal, have plenty of microprocessor and be sent to memory and input-output equipment interface circuit, the signal such as read or write, chip selection signal or interrupt response signal, also have is other component feedbacks to CPU, such as interrupt application signal, reset signal, bus request signal or the standby ready signal of limit, there can also be other control signals, the selection of particular use depends on CPU to its demand.

It is appreciated that, exist between above-mentioned modules and each distinguish corresponding hardware circuit, by transmission line, being associated property connects in buffer chip between these circuits, and specific type of attachment is related to circuit design, therefore the form not to connection is limited herein.

Shuffle module can be connected with address caching module, can also be connected with address caching module and control cache module, can also be connected with address caching module and skew cache module, and connected mode is communication connection.The process of shuffling can't change data in itself, it is but relevant with control signal and address signal, therefore shuffle module is mainly used in the signal stream that transmitting-receiving is passed over from data cache module with control cache module.It should be noted that only have modified the buffer chip on internal memory in this programme, the storage chip on internal memory is not changed, therefore the present invention changes and little for internal memory.

Fig. 4 is the structural representation of shuffle module, refer to Fig. 4, the function shuffled is to realize that data position in internal memory is rearranged, that is shuffling the address of rear data can change, as long as being therefore aware of the original address of each data and new address, each data are then exchanged into new address from original address be achieved that and shuffle function.In order to calculate new address, it is necessary to know offset of the new address relative to original address of each data, it is assumed that original address is addr_old, address offset amount is shift, then new address is addr_new=addr_old+shift.As fully visible, shuffle module can be an address conversion module.

Alternatively, the embodiment of the present invention also provides a kind of application programming interface (API, Application Programming Interface), API is the calling interface that operating system leaves application program for, application program makes operating system go to perform the order or action of application program by the API of call operation system, API is some pre-defined functions, purpose is to provide application program and ability of the developer based on one group of routine of certain software or hardware access, and source code need not be accessed, or understand the details of internal work mechanism, one API can be as a specification, and it defines the mode handed between two softwares with data exchange.

And in the embodiment of the present invention, the programming of user is used for convenience, propose a kind of unified API, function of shuffling based on internal memory is packaged, that is, the attribute of hidden object and details is realized in program, only external disclosure interface, the access level that attribute is read and changed in control program, abstract obtained data and function phase are combined, an organic whole are formed, that is, data are organically combined with the source code of peration data, one " class " is formed, wherein data and function are all the members of " class ".User only needs to call the interface function, you can realize shuffle operation.

Use for convenience and simplify control word, our the read-write processes to data respectively define an api function, and the api function of ablation process can be defined as：

void MemShuffleWrt(&Data1,size1,shift1)   (1)

And can be to readout one api function of definition of data：

ShuffledData=MemShuffleRd (s ＆Data2, size2, shift2) (2)

Wherein, there is progress data shuffling operation while writing data in representing in expression formula (1), Data1 refers to data to be written, and size1 refers to the bit wide of each data element to be written, and shift1 is the corresponding address offset amount of each data of array representation.There is progress data shuffling operation while reading data in representing in expression formula (2), ShuffledData represents to carry out the data after shuffle operation, Data2 refers to the data before shuffling, size2 refers to the bit wide for being read out data element, and shift2 is the corresponding address offset amount of each data of array representation.

Fig. 5 is the function control word schematic diagram of Mode Selection register in the embodiment of the present invention, referring to Fig. 5, Mode Selection register treats the address offset amount of shuffling data by API acquisition user configurings, and stores the address offset amount of user configuring.User can be as needed, and Mode Selection register is configured.

Alternatively, shuffle module also includes Mode Selection register, and it shuffles switch control word for acquisition, and these shuffle switch control word and are turned on and off data shuffling function for instruction, when shuffling switch control word When indicating that turn-on data shuffles function, Mode Selection register can obtain the corresponding address offset amount of each data from cache module, and the absolute value of each address offset amount will be less than the size for the total memory space for storing each data.

The function that shuffle module is realized is to be added raw address with address offset amount to obtain new address.Wherein raw address is passed over by address bus from processor, such as CPU or microprocessor, address offset amount is extracted in slave pattern mask register, internal memory goes to read or write data using the new address calculated, so as to which data have been transformed into new address from original address, it is finally completed and shuffles function.

In the present invention, assuming that S_on is the first value, represent that turn-on data shuffles function, S_on is second value, represent to close data shuffling function, as S_on=1 represents that turn-on data shuffles function, it is the size for representing each data element bit wide size that S_on=0, which represents to close after data shuffling function, S_on, and the bit wide of normal conditions downlink buffer is more than the bit wide of data element, therefore there are enough spaces to deposit each data in line buffer, the spilling of data will not be caused.Remaining control word, for example：Shift_0 represents the address offset amount 0 of corresponding data, shift_1 represents the address offset amount -3 of corresponding data, the address offset amount to each corresponding data is set successively, by the data shuffling between multirow, while also achieving the purpose to data shuffling between multiple row.Larger space can be opened up when opening space, if the space opened up is big can to deposit the data write next time, larger space is often first opened up if repeatedly write-in, the write-in of data is then carried out several times with shuffling, and fill up these spaces.

At the same time, bus is further comprises in internal memory, one or more layout line being connected with Mode Selection register is configured with the bus, and layout line one end is connected with Mode Selection register, the other end is then to be connected by the slot of internal memory with the chip beyond internal memory.Chip beyond internal memory can be cpu chip or north bridge chips, can also be that other realize the chip of the input of address offset amount or output.Wherein, north bridge chips are the important components played a leading role in board chip set, also referred to as it is main bridge, generally, the title of chipset is named with the title of north bridge chips, and the north bridge chips of such as Intel's 845E chipsets are 82845E, the north bridge chips of 875P chipsets are 82875P, north bridge chips are responsible for contacting with CPU, and control internal memory there is provided the front-side bus frequency to cpu type, dominant frequency and system.

User can realize the write-in of register control word by this specialized configuration line, and the control word of these write-ins is used to be turned on and off data shuffling function, set data corresponding address offset, other control words can also be write according to user's request, then the user is obtained by the device of data shuffling and pass through specialized configuration The information of line configuration, for carrying out data shuffling, this method needs to change the hardware interface of internal memory.

It should be noted that, also there is the mode of other configurations Mode Selection register, for example, utilize existing control line in internal memory, change the agreement of control line, increase the transmitting procedure of register control word, then the information of user configuring is obtained by changing agreement by the device of data shuffling, this method need not change the hardware interface of internal memory.There can also be other modes realized, therefore be not construed as limiting herein.

Fig. 6 is data shuffling performed by the device of data shuffling in the embodiment of the present invention and the process schematic of write-in, referring to Fig. 6, data shuffling ablation process schematic diagram is as shown in the figure.

In the present embodiment, the device of data shuffling is applied to the buffer chip of internal memory, and storage chip is further comprises in internal memory, the device includes cache module and shuffle module, communicated to connect between them, cache module is used to cache the address offset amount for treating the first address of each data and each data in shuffling data set, first address is then indicated for storage location of each data before shuffling in storage chip, shuffle module is according to the first address of each data and the address offset amount of each data, calculate the second address for obtaining each data, second address is used to indicate storage location of each data after shuffling in storage chip, shuffle module carries out data interaction further according to the second address and storage chip, realize the adjustment for treating data order in shuffling data set, data acquisition system after being shuffled.

It should be noted that cache module can be address caching module or address caching module and control cache module, address caching module and skew cache module are can also be, the composition of cache module is not limited herein.

When one section of continuous data write-in internal memory on address, need again simultaneously when assigning the new address of these data during write-in, shuffle module can transmit the second address for treating shuffling data set and each data to storage chip, so that storage chip will treat that shuffling data writes the corresponding storage location in the second address of each data according to the second address of each data, realize the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

It is appreciated that, in practical application, first address is not artificial distribution and write, but distributed unitedly by operating system and managed, and discontinuous situation can also occur under special circumstances in the first address in address caching module, therefore the selection and arranging situation not to the first address are construed as limiting herein.

The process of implementing can be as follows：

First address into address cache module of data, the first address are respectively 50,51,52,53,54,55 by CPU, by data a, b, and c, d, e, f is write in data cache module, by address offset amount In 0, -3, -6,2,7, -1 write-in control caching, wherein data and address offset amount are programmer's settings, and to be system distribute automatically for the first address；

Shuffle module call address mapping function void MemShuffleWrt (s ＆Data1, size1, shift1), the second address for obtaining each data is calculated, address mapping function is the second address of each data and the first address of each data and the mapping relations of the address offset amount sum of each data；

It is respectively 50,48,46,55 that calculating, which obtains the second address, 61,54, then the data in data cache module are write in line buffer according to the second address, a memory refresh operation is carried out again, and data brush in line buffer is returned in storage array, the write-in for completing data and the operation shuffled.

It is understood that being then to write data into the first address when address offset amount is zero, shuffle operation is not carried out, when address offset is not zero, the second address is obtained by shuffle module, data can be write in the second address, and shuffle operation has been carried out during write-in.

But it is related to address during write-in it is possible that the situation of plug hole and not plug hole, when plug hole, the first address is continuous, and the second address is discontinuous；When not plug hole, the first address is continuous, and the second address is also continuous, and simply the corresponding order in address is changed.If during plug hole, address offset amount sum, which differs, is set to zero, because in the case of plug hole, address offset is not limited, when being zero, the data of write-in can be ring shift left or ring shift right, it can also be other modes, and in most cases be not zero.

Fig. 7 is data shuffling performed by the device of data shuffling in the embodiment of the present invention and the process schematic schematic diagram read, referring to Fig. 7, data shuffling readout schematic diagram is as shown in the figure.

There is provided a kind of method of data shuffling readout in the present embodiment, while a kind of device for the data shuffling that can realize this method is also provided, and the device of device embodiment description corresponding with above-mentioned Fig. 6 is consistent, therefore do not repeat herein.

When need read internal memory in one section of continuous data, need again simultaneously when assigning the new address of these data during reading, shuffle module transmits the second address of each data to storage chip, so that second address of the storage chip according to each data, from the second address of each data, corresponding storage location reads each data, realize the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

The process of implementing can be as follows：

First address into address cache module of data, the first address are respectively 50,51,52 by CPU, 53,54,55, and these addresses are necessary for a continuous sector address, by the write-in control caching of address offset amount 1,1,1,1,1, -5, wherein data and address offset amount are programmer's settings, and to be system distribute automatically for the first address；

Shuffle module calls ShuffledData=MemShuffleRd (s ＆Data2, size2, shift2), the second address for obtaining each data is calculated, address mapping function is the second address of each data and the first address of each data and the mapping relations of the address offset amount sum of each data；

It is respectively 51 that calculating, which obtains the second address, 52,53,54,55,50, it can be seen that realizing the ring shift right of data after shuffling, that a line of the storage array where the second address corresponding data is refreshed into line buffer again, finally the corresponding data in the second address in line buffer are downloaded in pending data cache module and these data are read by data/address bus, the reading for completing data and the operation shuffled.

Relative to the process of write-in, in the absence of the situation of plug hole during reading, therefore read when address offset amount sum one be set to zero.

Alternatively, during data or write-in data are read, the device of data shuffling needs call address mapping function, the second address for obtaining each data is calculated by this function, address mapping function is the second address of each data and the first address of each data and the mapping relations of the address offset amount sum of each data.

The device of data shuffling can apply to mobile phone EMS memory, random access memory (RAM, random access memory) or embedded system, can also be applied and base station system due to the function with rapid configuration in above-mentioned introduction, the present invention.Such as in the mobile data processing of multi-antenna multi-user, carrying out a shuffle operation probably needs 100us time, and shuffling for data is directly realized by internal memory using the device of data shuffling proposed by the present invention, only needing to several clock cycle can complete, assuming that the clock frequency of memory modules be 1600MHz, then shuffle operation can within the time of ns magnitudes the time.Therefore it is rational that the device of data shuffling proposed by the present invention, which is applied in storage device,.

In the embodiment of the present invention, the device of the data shuffling of offer apply with the cache chip of internal memory, need the buffer chip in improved only internal memory, rather than the construction of whole internal memory, therefore implement more simple, simultaneously, the function of shuffling of the device is by hard-wired in internal memory, carried out simultaneously along with the process of reading and writing data again, need not by internal memory outside processor complete said process, it so can largely save the computing resource of processor, especially alleviate CPU work load, also largely reduce the time delay of data processing, when data volume is larger, further embody data transmission period Short advantage.

The method to the data shuffling in the present invention is described in detail below, referring to Fig. 8, a kind of embodiment of the method for data shuffling provided in an embodiment of the present invention includes：

801st, the address offset amount for treating the first address of each data and each data in shuffling data set is obtained；

In the present embodiment, the device of data shuffling obtains the first address for treating each data in shuffling data set, first address is indicated for the storage location in storage chip before each data shuffling, meanwhile, the device of data shuffling also obtains the corresponding address offset amount of each data.

802nd, according to the first address of each data and the address offset amount of each data, the second address for obtaining each data is calculated, the second address is used to indicate storage location of each data after shuffling in storage chip；

In the present embodiment, the device of data shuffling is according to the first address of each data and the address offset amount of each data, and calculating obtains corresponding second address of each data, and the second address is used to indicate storage location of each data after shuffling in storage chip.

803rd, data interaction is carried out according to the second address and storage chip, realizes the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

In the present embodiment, the second address that the device of data shuffling is obtained according to calculating carries out data interaction with storage chip, it is possible to achieve treat the adjustment of data order in shuffling data set, the data acquisition system after being shuffled.

In the embodiment of the present invention, the device of data shuffling obtains and treats the first address of each data and corresponding address offset amount in shuffling data, corresponding second address of each data is obtained by calculating, the order adjustment for treating shuffling data is realized according to the data interaction of the second address and storage chip, data after being shuffled, and said process is applied in the cache chip of internal memory, do not need and realize and shuffle in reprocessor, therefore the computing resource of processor is largely saved, while reducing the processing delay of data.

Alternatively, on the basis of the corresponding embodiments of above-mentioned Fig. 8, in first alternative embodiment of data shuffling method provided in an embodiment of the present invention, data interaction is carried out according to the second address and storage chip, realize the adjustment for treating data order in shuffling data set, data acquisition system after being shuffled, including：

The second address for treating shuffling data set and each data is transmitted to storage chip, so that storage chip The second address according to each data will treat that shuffling data writes the corresponding storage location in the second address of each data, realize the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

In the present embodiment, the device of data shuffling is transmitted to storage chip treats shuffling data set and the second address of each data, storage chip is first write in line buffer according to corresponding second address of each data, a memory refresh operation is carried out again, Refresh Data in line buffer is returned in storage array, i.e., in the corresponding storage location in each address of data second.

It should be noted that, memory refresh is operated generally, must be within several milliseconds to dynamic random access memory (DRAM, Dynamic Random Access Memory) refresh once, otherwise data be able to may lose, and DRAM refreshing mode has a variety of, can separately it be carried out with refresh operation for normal read or write operation, refresh the centralization concentrated and completed, but there can be one time for stopping writing after reading, be applicable and high-speed memory；The distributing of normal read or write operation and refresh operation can also be carried out respectively for a storage system cycle is divided into two times, but the speed of system operation can be reduced；Asynchronous system once can also just be refreshed at regular intervals, it is ensured that whole storage chip is refreshed one time within the refresh cycle, therefore specific refreshing mode not limited herein for that above two ways will combine.

Secondly, in the embodiment of the present invention, the device of data shuffling is during shuffle operation is realized, along with the write-in of data so that data shuffling and data write-in can be completed all in internal memory, save substantial amounts of processing time, the practicality with season scheme is stronger.

Alternatively, on the basis of the corresponding embodiments of above-mentioned Fig. 8, in second alternative embodiment of data shuffling method provided in an embodiment of the present invention, data interaction is carried out according to the second address and storage chip, realize the adjustment for treating data order in shuffling data set, data acquisition system after being shuffled, including：

The second address of each data is transmitted to storage chip, so that second address of the storage chip according to each data, from the second address of each data, corresponding storage location reads each data, realizes the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

In the present embodiment, the device of data shuffling transmits the second address of each data to storage chip, so that second address of the storage chip according to each data, reads each data from the corresponding storage location in the second address of each data, complete the reading of data and shuffle.

It should be noted that it can be by one or more host-host protocols, such as transmission control protocol (TCP, Transmission Control that the device of data shuffling transmits two address mode to storage chip Protocol), or User Datagram Protocol (UDP, User Datagram Protocol) or two address information to storage chip is transmitted by address bus, therefore specific transmission means not limited herein.

Secondly, in the embodiment of the present invention, the device of data shuffling is during shuffle operation is realized, along with the reading of data so that data shuffling and digital independent can be completed all in internal memory, similar to the inverse process of data writing process, save substantial amounts of processing time, corresponding data in one section of continuation address can be flexibly grasped simultaneously, is easy to research and uses, the practicality of scheme is further increased.

Alternatively, on the basis of any one of the corresponding embodiment of above-mentioned Fig. 8, first alternative embodiment and second alternative embodiment, in 3rd alternative embodiment of data shuffling method provided in an embodiment of the present invention, acquisition treats that the first address of each data and the address offset amount of each data include in shuffling data set：

Switch control word is shuffled in acquisition, is shuffled switch control word and is turned on and off data shuffling function for instruction；

When shuffling switch control word and indicating that turn-on data shuffles function, the first address of each data and the address offset amount of each data are obtained.

In the present embodiment, when the device of data shuffling includes Mode Selection register, then the device of data shuffling can obtain and shuffle switch control word, and shuffle switch control word and be indicated for being turned on or off data shuffling function, when shuffling switch control word and indicating that turn-on data shuffles function, the device of data shuffling obtains the first address of each data.

It should be noted that, when user configures to Mode Selection register, it can be configured by the increased specialized configuration line of internal memory, the layout line is added in the bus, but this method needs to change the hardware interface of internal memory, can also pass through existing control line in internal memory, change the agreement of control line, increase the transmitting procedure of register control word, and this method need not change the hardware interface of internal memory, therefore the method not to concrete configuration Mode Selection register is limited herein.

Again, in the embodiment of the present invention, the device of data shuffling includes Mode Selection register, and user can set the address offset amount of data by configuration mode mask register, also other control words such as bit wide size of data, in actual applications, the setting to address offset can realize that datacycle is moved to left, ring shift right, or any other new arrangement modes such as exchange, therefore the flexibility of the program and practicality are all lifted, meanwhile, operability is also enhanced.

Alternatively, on the basis of any one of the corresponding embodiment of above-mentioned Fig. 8, first alternative embodiment, second alternative embodiment and the 3rd alternative embodiment, in 4th alternative embodiment of data shuffling method provided in an embodiment of the present invention, according to the first address of each data and the address offset amount of each data, the second address for obtaining each data is calculated, including：

Call address mapping function, calculates the second address for obtaining each data, and address mapping function is the second address of each data and the first address of each data and the mapping relations of the address offset amount sum of each data.

In the present embodiment, the device call address mapping function of data shuffling, the second address for obtaining each data is calculated by this function, address mapping function is the second address of each data and the first address of each data and the mapping relations of the address offset amount sum of each data.

It should be noted that address mapping function can be compiled by API to it, the function can be the write-in function referred in above-described embodiment：Void MemShuffleWrt (s ＆Data1, size1, shift1) or reading function：ShuffledData=MemShuffleRd (s ＆Data2, size2, shift2), and in actual applications, the position of element in function expression can also be changed, Li Ru ＆Data1, size1 and shift1 order change, it can also be and the element project in function expression is adjusted, for example increase the project of data bandwidth, be set as that the expression formula in bps1, therefore the present embodiment not to specific address mapping function is limited.

Further, in the embodiment of the present invention, the device of data shuffling calls the address mapping function that user sets, the first address that can be according to data and address offset amount, map out the second address, and realize that the address mapping function of this function can be compiled by API, and the use of coding is fairly simple, the whole process for shuffling conversion is also transparent for a user, user can be as needed to address mapping function form be modified, the flexibility for sufficiently embodying this programme is good, while the characteristics of having a wide range of application.

For ease of understanding, a kind of method of data shuffling in the present invention is described in detail with a concrete application scene below, is specially：

There are many users in first building while carrying out voice transfer, sending and receiving e-mail, web page browsing, online see video and dial the operation of videophone, in the transmitting-receiving for being the need for multiple antennas support signal, there are user 1, user 2 and user 3 in first building, and user 1, user 2 and user 3 use antenna 1, antenna 2, antenna 3 and antenna 4,, need to be in short-term now in the mobile data processing of multi-antenna multi-user It is interior to carry out a data shuffling operation so that data processing is carried out using antenna as unit.

Technician has compiled write-in function by api interface with reading function respectively, and it is as follows that it writes function：

Void MemShuffleWrt(&Data,size,shift)

And it is as follows to readout one api function of definition of data：

ShuffledData=MemShuffleRd (s ＆Data, size, shift)

The data that Data refers to be read out or write, size refers to the bit wide of each data element, and shift refers to the corresponding address offset amount of each data in an array, corresponding mapping result is determined according to above-mentioned functional relation.

Now user increases the transmitting procedure of register control word by changing control wire protocol, and is set as address offset amount shift1=0, shift2=2, shift3=4, shift4=6, shift5=-3, shift6=-1, shift7=1, shift8=3, shift9=-6, shift10=-4, shift11=-2, shift12=0.

The device of data shuffling is obtained from the data buffer storage in storage chip treats that shuffling data is A, B, C, D, E, F, G, H, I, J, K, L, and it is respectively addr_odd1=1 to addr_odd12=12 to obtain from address caching the raw address addr_odd of corresponding 12 addresses.

Then the mapping between raw address and new address is proceeded by the address mapping module of the device of data shuffling, call reading function ShuffledData=MemShuffleRd (s ＆Data, size, shift), data below is substituted into according to the relation of the function, for example：Data=A, size=2Byte, shift1=0, its correspondence raw address are 1 corresponding to addr_odd1, by corresponding mapping relations, can obtain treating shuffling data A new address addr_new1=addr_odd1+shift1, i.e. addr_new1=1+0=1.

The like can obtain new address：Addr_new2=4, addr_new3=7, addr_new4=10, addr_new5=2, addr_new6=5, addr_new7=8, addr_new8=11, addr_new9=3, addr_new10=6, addr_new11=9 and addr_new12=12, and it is corresponding, data after shuffling can be placed in new address, specially data B is located at address 4, data C is located at address 7, data D is located at address 10, data E is located at address 2, data F is located at address 5, data G is located at address 8, data H is located at address 11, data I is located at address 3, data J is located at address 6, data K is located at address 9, data L is located at address 12, the process of data shuffling terminates.

Finally, these Data Migrations after shuffling are into line buffer, and new all corresponding data of address addr_new can be downloaded in data buffer storage, and read these data, technical staff can be analyzed these data, laid the foundation for the more smooth data transfer of realization.

The data shuffling method in the embodiment of the present invention is described above, the device of the data shuffling in the embodiment of the present invention is described below, referring to Fig. 9, device one embodiment of the data shuffling in the embodiment of the present invention includes：

Acquisition module 901, the address offset amount of the first address of each data and each data in shuffling data set is treated for obtaining；

Computing module 902, for the first address according to each data and the address offset amount of each data, the second address for obtaining each data is calculated, second address is used to indicate storage location of each data after shuffling in the storage chip；

Adjusting module 903, for carrying out data interaction according to second address and the storage chip, is realized to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

In the present embodiment, acquisition module 901 obtains the address offset amount for treating the first address of each data and each data in shuffling data set, computing module 902 is according to the first address of each data and the address offset amount of each data, calculate the second address for obtaining each data, second address is used to indicate storage location of each data after shuffling in storage chip, adjusting module 903 carries out data interaction according to the second address and storage chip, realize the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

In the embodiment of the present invention, the device of data shuffling obtains and treats the first address of each data and corresponding address offset amount in shuffling data, corresponding second address of each data is obtained by calculating, the order adjustment for treating shuffling data is realized according to the data interaction of the second address and storage chip, data after being shuffled, and said process is applied in the cache chip of internal memory, do not need and realize and shuffle in reprocessor, therefore the computing resource of processor is largely saved, while reducing the processing delay of data.

Referring to Fig. 10, another embodiment of the device of data shuffling includes in the embodiment of the present invention：

Acquisition module 1001, the address offset amount of the first address of each data and each data in shuffling data set is treated for obtaining；

Computing module 1002, for the first address of each data obtained according to the acquisition module 1001 and the address offset amount of each data, the second address for obtaining each data is calculated, second address is used to indicate storage location of each data after shuffling in the storage chip；

Adjusting module 1003, the second address and the storage chip for being calculated according to the computing module 1002 carry out data interaction, realize to the adjustment for treating data order in shuffling data set, obtain Data acquisition system after shuffling；

The adjusting module 1003 may further include：

First transmission unit 10031, for treating the second address of shuffling data set and each data described in being transmitted to the storage chip, so that the storage chip treats the corresponding storage location in the second address that shuffling data writes each data according to the second address of each data by described, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

Secondly, in the embodiment of the present invention, the device of data shuffling is during shuffle operation is realized, along with the write-in of data so that data shuffling and data write-in can be completed all in internal memory, save substantial amounts of processing time, the practicality with season scheme is stronger.

Referring to another embodiment of the device of data shuffling in Figure 11, the embodiment of the present invention includes：

Acquisition module 1101, the address offset amount of the first address of each data and each data in shuffling data set is treated for obtaining；

Computing module 1102, for the first address of each data obtained according to the acquisition module 1101 and the address offset amount of each data, the second address for obtaining each data is calculated, second address is used to indicate storage location of each data after shuffling in the storage chip；

Adjusting module 1103, the second address and the storage chip for being calculated according to the computing module 1102 carry out data interaction, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled；

The adjusting module 1103 may further include：

Second transmission unit 11031, the second address for transmitting each data to the storage chip, so that second address of the storage chip according to each data, from the second address of each data, corresponding storage location reads each data, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

Secondly, in the embodiment of the present invention, the device of data shuffling is during shuffle operation is realized, along with the reading of data so that data shuffling and digital independent can be completed all in internal memory, similar to the inverse process of data writing process, save substantial amounts of processing time, corresponding data in one section of continuation address can be flexibly grasped simultaneously, is easy to research and uses, the practicality of scheme is further increased.

Referring to another embodiment of the device of data shuffling in Figure 12, the embodiment of the present invention includes：

Acquisition module 1201, the first address of each data and each is treated in shuffling data set for obtaining The address offset amount of data；

Computing module 1202, for the first address of each data obtained according to the acquisition module 1201 and the address offset amount of each data, the second address for obtaining each data is calculated, second address is used to indicate storage location of each data after shuffling in the storage chip；

Adjusting module 1203, the second address and the storage chip for being calculated according to the computing module 1202 carry out data interaction, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled；

The acquisition module 1201 may further include：

First acquisition unit 12011, shuffles switch control word, the switch control word that shuffles is turned on and off data shuffling function for instruction for obtaining；

Second acquisition unit 12012, for when the first acquisition unit 12011 obtain when shuffling switch control word and indicating to open the data shuffling function, obtain the first address of each data and the address offset amount of each data.

The adjusting module 1203 may further include：

Second transmission unit 12031, the second address for transmitting each data to the storage chip, so that second address of the storage chip according to each data, from the second address of each data, corresponding storage location reads each data, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

Again, in the embodiment of the present invention, the device of data shuffling includes Mode Selection register, and user can set the address offset amount of data by configuration mode mask register, also other control words such as bit wide size of data, in actual applications, the setting to address offset can realize that datacycle is moved to left, ring shift right, or any other new arrangement modes such as exchange, therefore the flexibility of the program and practicality are all lifted, meanwhile, operability is also enhanced.

Referring to another embodiment of the device of data shuffling in Figure 13, the embodiment of the present invention includes：

Acquisition module 1301, the address offset amount of the first address of each data and each data in shuffling data set is treated for obtaining；

Computing module 1302, for the first address of each data obtained according to the acquisition module 1301 and the address offset amount of each data, the second address for obtaining each data is calculated, second address is used to indicate storage location of each data after shuffling in the storage chip；

Adjusting module 1303, the second address and the storage chip for being calculated according to the computing module 1302 carry out data interaction, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled；

The acquisition module 1301 may further include：

First acquisition unit 13011, shuffles switch control word, the switch control word that shuffles is turned on and off data shuffling function for instruction for obtaining；

Second acquisition unit 13012, for when the first acquisition unit 13011 obtain when shuffling switch control word and indicating to open the data shuffling function, obtain the first address of each data and the address offset amount of each data.

The computing module 1302 may further include：

Computing unit 13021, for call address mapping function, the second address for obtaining each data is calculated, the address mapping function is the second address of each data and the first address of each data and the mapping relations of the address offset amount sum of each data.

The adjusting module 1303 may further include：

Second transmission unit 13031, the second address for transmitting each data to the storage chip, so that second address of the storage chip according to each data, from the second address of each data, corresponding storage location reads each data, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

Further, in the embodiment of the present invention, the device of data shuffling calls the address mapping function that user sets, the first address that can be according to data and address offset amount, map out the second address, and realize that the address mapping function of this function can be compiled by API, and the use of coding is fairly simple, the whole process for shuffling conversion is also transparent for a user, user can be as needed to address mapping function form be modified, the flexibility for sufficiently embodying this programme is good, while the characteristics of having a wide range of application.

Figure 14 is a kind of apparatus structure schematic diagram of data shuffling provided in an embodiment of the present invention, the device 1400 of the data shuffling can be produced than larger difference because of configuration or performance difference, one or more central processing units 1422 can be included (for example, one or more processors) and memory 1432, one or more store the storage medium 1430 (such as one or more mass memory units) of application programs 1442 or data 1444.Wherein, memory 1432 and storage medium 1430 can be of short duration deposit Storage or persistently storage.One or more modules (diagram is not marked) can be included by being stored in the program of storage medium 1430, and each module can include operating the series of instructions in server.Further, central processing unit 1422 be could be arranged to communicate with storage medium 1430, and the series of instructions operation in storage medium 1430 is performed on server 1400.

Central processing unit 1422 is used for：

Obtain the address offset amount for treating the first address of each data and each data in shuffling data set；

According to the first address of each data and the address offset amount of each data, the second address for obtaining each data is calculated, second address is used to indicate storage location of each data after shuffling in the storage chip；

Data interaction is carried out according to second address and the storage chip, realized to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

In the embodiment of the present invention, the device of data shuffling obtains and treats the first address of each data and corresponding address offset amount in shuffling data, corresponding second address of each data is obtained by calculating, the order adjustment for treating shuffling data is realized according to the data interaction of the second address and storage chip, data after being shuffled, and said process is applied in the cache chip of internal memory, do not need and realize and shuffle in reprocessor, therefore the computing resource of processor is largely saved, while reducing the processing delay of data.

It is used as a kind of optional mode, central processing unit 1422 is additionally operable to the second address that shuffling data set and each data are treated described in storage chip transmission, so that the storage chip treats the corresponding storage location in the second address that shuffling data writes each data according to the second address of each data by described, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

Secondly, in the embodiment of the present invention, the device of data shuffling is during shuffle operation is realized, along with the write-in of data so that data shuffling and data write-in can be completed all in internal memory, save substantial amounts of processing time, the practicality with season scheme is stronger.

It is used as a kind of optional mode, central processing unit 1422 is additionally operable to transmit the second address of each data to the storage chip, so that second address of the storage chip according to each data, from the second address of each data, corresponding storage location reads each data, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.

Secondly, in the embodiment of the present invention, the device of data shuffling is during shuffle operation is realized, companion With the reading of data, data shuffling and digital independent are completed all in internal memory, it is similar to the inverse process of data writing process, save substantial amounts of processing time, it can flexibly grasp corresponding data in one section of continuation address simultaneously, it is easy to research and uses, further increases the practicality of scheme.

As a kind of optional mode, central processing unit 1422 is additionally operable to acquisition and shuffles switch control word, and the switch control word that shuffles is turned on and off data shuffling function for instruction；

When it is described shuffle switch control word and indicate to open the data shuffling function when, obtain the first address of each data and the address offset amount of each data.

Again, in the embodiment of the present invention, the device of data shuffling includes Mode Selection register, and user can set the address offset amount of data by configuration mode mask register, also other control words such as bit wide size of data, in actual applications, the setting to address offset can realize that datacycle is moved to left, ring shift right, or any other new arrangement modes such as exchange, therefore the flexibility of the program and practicality are all lifted, meanwhile, operability is also enhanced.

It is used as a kind of optional mode, central processing unit 1422 is additionally operable to call address mapping function, the second address for obtaining each data is calculated, the address mapping function is the second address of each data and the first address of each data and the mapping relations of the address offset amount sum of each data.

Further, in the embodiment of the present invention, the device of data shuffling calls the address mapping function that user sets, the first address that can be according to data and address offset amount, map out the second address, and realize that the address mapping function of this function can be compiled by API, and the use of coding is fairly simple, the whole process for shuffling conversion is also transparent for a user, user can be as needed to address mapping function form be modified, the flexibility for sufficiently embodying this programme is good, while the characteristics of having a wide range of application.

The device 1400 of data shuffling can also include one or more power supplys 1426, one or more wired or wireless network interfaces 1450, one or more input/output interfaces 1458, and/or, one or more operating systems 1441, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM etc..

Can the apparatus structure based on the data shuffling shown in the Figure 14 as the step performed by the device of data shuffling in above-described embodiment.

In the above-described embodiments, the description to each embodiment all emphasizes particularly on different fields, and does not have in some embodiment The part of detailed description, may refer to the associated description of other embodiment.

In several embodiments provided herein, it should be understood that disclosed system, apparatus and method can be realized by another way.For example, device embodiment described above is only schematical, for example, the division of the unit, it is only a kind of division of logic function, there can be other dividing mode when actually realizing, such as multiple units or component can combine or be desirably integrated into another system, or some features can be ignored, or do not perform.Another, it, by some interfaces, the INDIRECT COUPLING or communication connection of device or unit, can be electrical, machinery or other forms that shown or discussed coupling or direct-coupling or communication connection each other, which can be,.

The unit illustrated as separating component can be or may not be physically separate, and the part shown as unit can be or may not be physical location, you can with positioned at a place, or can also be distributed on multiple NEs.Some or all of unit therein can be selected to realize the purpose of this embodiment scheme according to the actual needs.

In addition, each functional unit in each of the invention embodiment can be integrated in a processing unit or unit is individually physically present, can also two or more units it is integrated in a unit.Above-mentioned integrated unit can both be realized in the form of hardware, it would however also be possible to employ the form of SFU software functional unit is realized.

If the integrated unit is realized using in the form of SFU software functional unit and as independent production marketing or in use, can be stored in a computer read/write memory medium.Understood based on such, the part or all or part of the technical scheme that technical scheme substantially contributes to prior art in other words can be embodied in the form of software product, the computer software product is stored in a storage medium, including some instructions to cause a computer equipment (can be personal computer, server, or the network equipment etc.) perform all or part of step of each embodiment methods described of the invention.And foregoing storage medium includes：USB flash disk, mobile hard disk, read-only storage (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disc or CD etc. are various can be with the medium of store program codes.

A kind of method of data shuffling provided by the present invention is described in detail above, specific case used herein is set forth to the principle and embodiment of the present invention, and the explanation of above example is only intended to help to understand method and its core concept of the invention；Simultaneously for those skilled in the art, according to the thought of the embodiment of the present invention, it will change in specific embodiments and applications, In summary, this specification content should not be construed as limiting the invention.

Claims (18)

1. A kind of device of data shuffling, it is characterised in that described device is applied to the buffer chip of internal memory, the internal memory also includes storage chip, and described device includes：Cache module and shuffle module；

   The cache module is communicated to connect with the shuffle module；

   The cache module is used to cache the address offset amount for treating the first address of each data and each data in shuffling data set；

   The shuffle module is used for the first address and the address offset amount of each data according to each data, the second address for obtaining each data is calculated, second address is used to indicate storage location of each data after shuffling in the storage chip；

   The shuffle module is used to carry out data interaction according to second address and the storage chip, realizes to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.
2. Device according to claim 1, it is characterised in that

   The cache module is address caching module, and the address caching module is communicated to connect with the shuffle module, and the address caching module is used to cache the address offset amount for treating the first address of each data and each data in shuffling data set；Or,

   The cache module includes address caching module and control cache module, and the address caching module is used to cache the first address for treating each data in shuffling data set, and the control cache module is used for the address offset amount for caching each data；Or,

   The cache module includes address caching module and skew cache module, and the address caching module is used to cache the first address for treating each data in shuffling data set, and the skew cache module is used for the address offset amount for caching each data.
3. Device according to claim 1 or 2, characterized in that, the shuffle module is used to carry out data interaction according to second address and the storage chip, realize to the adjustment for treating data order in shuffling data set, data acquisition system after being shuffled, including：

   The shuffle module is used for the second address that shuffling data set and each data are treated described in storage chip transmission, so that the storage chip treats the corresponding storage location in the second address that shuffling data writes each data according to the second address of each data by described, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.
4. Device according to claim 1 or 2, it is characterised in that the shuffle module is used for root Data interaction is carried out according to second address and the storage chip, is realized to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled, including：

   The shuffle module is used for the second address that each data are transmitted to the storage chip, so that second address of the storage chip according to each data, from the second address of each data, corresponding storage location reads each data, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.
5. According to any described devices of claim 1-4, it is characterised in that the shuffle module includes：Mode Selection register,

   The Mode Selection register shuffles switch control word for acquisition, and the switch control word that shuffles is turned on and off data shuffling function for instruction；

   When it is described shuffle switch control word and indicate to open the data shuffling function when, the Mode Selection register is used for the address offset amount that each data are obtained from the cache module.
6. According to any described devices of claim 1-5, it is characterized in that, the absolute value for treating the address offset amount of each data in shuffling data set is both less than the size for the total memory space for being used to store each data, and the address offset amount sum of each data is zero.
7. Device according to claim 5, it is characterised in that the internal memory also includes being configured with the layout line being connected with the Mode Selection register in bus, the bus,

   Described layout line one end is connected with the Mode Selection register, and the other end is connected by the slot of the internal memory with the chip beyond the internal memory；

   The Mode Selection register shuffles switch control word for acquisition, including：

   The Mode Selection register is used to shuffle switch control word by the described of layout line reception user configuring.
8. According to any described device in claim 1 to 7, it is characterised in that the shuffle module is used for the first address and the address offset amount of each data according to each data, the second address for obtaining each data is calculated, including：

   The shuffle module is used for call address mapping function, the second address for obtaining each data is calculated, the address mapping function is the second address of each data and the first address of each data and the mapping relations of the address offset amount sum of each data.
9. A kind of method of data shuffling, it is characterised in that methods described is applied to the buffer chip of internal memory, The internal memory also includes storage chip, and methods described includes：

   Obtain the address offset amount for treating the first address of each data and each data in shuffling data set；

   According to the first address of each data and the address offset amount of each data, the second address for obtaining each data is calculated, second address is used to indicate storage location of each data after shuffling in the storage chip；

   Data interaction is carried out according to second address and the storage chip, realized to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.
10. Method according to claim 9, it is characterised in that described to carry out data interaction according to second address and the storage chip, is realized to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled, including：

    To the second address that shuffling data set and each data are treated described in storage chip transmission, so that the storage chip treats the corresponding storage location in the second address that shuffling data writes each data according to the second address of each data by described, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.
11. Method according to claim 9, it is characterised in that described to carry out data interaction according to second address and the storage chip, is realized to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled, including：

    The second address of each data is transmitted to the storage chip, so that second address of the storage chip according to each data, from the second address of each data, corresponding storage location reads each data, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.
12. Method according to any one of claim 9 to 11, it is characterised in that the acquisition treats that the first address of each data and the address offset amount of each data include in shuffling data set：

    Switch control word is shuffled in acquisition, and the switch control word that shuffles is turned on and off data shuffling function for instruction；

    When it is described shuffle switch control word and indicate to open the data shuffling function when, obtain the first address of each data and the address offset amount of each data.
13. According to method of the claim 9 to 12 any one of, it is characterised in that first address and the address offset amount of each data according to each data, calculating obtains described every Second address of individual data, including：

    Call address mapping function, calculates the second address for obtaining each data, and the address mapping function is the second address of each data and the first address of each data and the mapping relations of the address offset amount sum of each data.
14. A kind of device of data shuffling, it is characterised in that described device is applied to the buffer chip of internal memory, the internal memory also includes storage chip, and described device includes：

    Acquisition module, the address offset amount of the first address of each data and each data in shuffling data set is treated for obtaining；

    Computing module, for the first address according to each data and the address offset amount of each data, calculates the second address for obtaining each data, second address is used to indicate storage location of each data after shuffling in the storage chip；

    Adjusting module, for carrying out data interaction according to second address and the storage chip, is realized to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.
15. Device according to claim 14, it is characterised in that the adjusting module includes：

    First transmission unit, for treating the second address of shuffling data set and each data described in being transmitted to the storage chip, so that the storage chip treats the corresponding storage location in the second address that shuffling data writes each data according to the second address of each data by described, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.
16. Device according to claim 14, it is characterised in that the adjusting module includes：

    Second transmission unit, the second address for transmitting each data to the storage chip, so that second address of the storage chip according to each data, from the second address of each data, corresponding storage location reads each data, realize to the adjustment for treating data order in shuffling data set, the data acquisition system after being shuffled.
17. Device according to any one of claim 14 to 16, it is characterised in that the acquisition module includes：

    First acquisition unit, shuffles switch control word, the switch control word that shuffles is turned on and off data shuffling function for instruction for obtaining；

    Second acquisition unit, for when it is described shuffle switch control word and indicate to open the data shuffling function when, obtain the first address of each data and the address offset amount of each data.
18. Device according to any one of claim 14 to 17, it is characterised in that the computing module includes：

    Computing unit, for call address mapping function, the second address for obtaining each data is calculated, the address mapping function is the second address of each data and the first address of each data and the mapping relations of the address offset amount sum of each data.