CN106712802B - A kind of digital bit synchronization system and its method for noncoherent detection - Google Patents
A kind of digital bit synchronization system and its method for noncoherent detection Download PDFInfo
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- CN106712802B CN106712802B CN201710014394.XA CN201710014394A CN106712802B CN 106712802 B CN106712802 B CN 106712802B CN 201710014394 A CN201710014394 A CN 201710014394A CN 106712802 B CN106712802 B CN 106712802B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/709—Correlator structure
- H04B1/7093—Matched filter type
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2689—Link with other circuits, i.e. special connections between synchronisation arrangements and other circuits for achieving synchronisation
- H04L27/2695—Link with other circuits, i.e. special connections between synchronisation arrangements and other circuits for achieving synchronisation with channel estimation, e.g. determination of delay spread, derivative or peak tracking
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B2001/70706—Spread spectrum techniques using direct sequence modulation using a code tracking loop, e.g. a delay locked loop
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- Computer Networks & Wireless Communication (AREA)
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- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a kind of digital bit synchronization system and its method for noncoherent detection, feature includes matched filtering circuit, delay circuit, bit synchronization circuit, decision circuit, parallel-to-serial converter, coherently despreading circuit；Matched filtering circuit is for being sampled and being filtered, delay circuit is used for the delay disposal of a code-element period, bit synchronization circuit is used for mean value computation, Edge check and peak detection process, decision circuit is for adjudicating and dipole inversion processing, parallel-to-serial converter is calculated for being converted into serial bit data flow, coherently despreading circuit for demodulating.The present invention can realize noncoherent detection bit synchronization in the case where occupancy resource is less, to reduce the area shared by realizing noncoherent detection bit synchronization in the chips, reduce chip cost.
Description
Technical field
The present invention relates to a kind of digital bit synchronization system and its method, more specifically refer to a kind of for noncoherent detection
Digital bit synchronization method is adapted to carry out and receives to DSSS (Direct Sequence Spread Spectrum) communication and IEEE 802.15.4 communication etc.
The bit synchronization of signal.
Background technique
With the development of communication technology, more and more communications all use digital communication mode, and digital communication has anti-dry
Disturb that ability is strong, noiseless accumulation, mistake is controllable, is easy to the advantages of secrecy.In addition, being with the raising of chip system complexity
It is integrated with more and more modules in irrespective of size chip, there is cross clock domain path mostly, data will necessarily be between different zones
It is transmitted, the synchronous problem of data can be faced.
Currently, often using noncoherent detection and data bit synchronization circuit in a communications system.Existing incoherent inspection
The bit synchronization technology of survey, not only algorithm is complicated but also needs phaselocked loop mostly, increase the area of chip while increasing into
This.
Summary of the invention
The present invention is to provide a kind of number for noncoherent detection to avoid above-mentioned existing deficiencies in the technology
Word bit synchronization system and its method, to noncoherent detection bit synchronization be realized, to subtract in the case where occupancy resource is less
It is small to realize noncoherent detection bit synchronization shared area in the chips, reduce chip cost；And it can be by being configured to across clock
The synchronization of numeric field data.
The present invention adopts the following technical scheme that in order to solve the technical problem
A kind of the characteristics of digital bit synchronization system for noncoherent detection of the invention includes: that matched filtering module, position are same
Walk module, judging module, parallel serial conversion module, coherently despreading module；
The matched filtering module receives externally input I, Q two paths of signals and is sampled and be filtered respectively, obtains
To after FI signal and FQ signal, the FQ signal is exported to the bit sync module, the FI signal is exported and is prolonged to described
Slow module；
The Postponement module to received FI signal carry out the delay disposal of a code-element period Tc, after obtaining DI signal
Pass to the bit sync module；
The bit sync module carries out mean value computation, Edge check and peak value to the received DI signal of institute and FQ signal respectively
Detection processing obtains sampling enable signal SEN, average sample mean value SI and SQ, and is exported together to the judging module；
The judging module sentences the sample mean SI and SQ according to the received sampling enable signal SEN of institute
Certainly with dipole inversion processing, JI signal and JQ signal are obtained, and is exported to the parallel serial conversion module；
The parallel serial conversion module passes to after the JI signal and JQ signal to be converted into serial bit data flow P2S
The coherently despreading module；
The coherently despreading module carries out demodulation calculating to the bit data flow P2S, the output data after being demodulated
Dout。
The characteristics of digital bit synchronization system of the present invention for noncoherent detection, lies also in:
The matched filtering module use can configure matched Ctrl signal control filter process, so that described
Matched filtering module can work according to corresponding configuration in different filter states.
The bit sync module carries out mean filter processing to the DI signal and FQ signal first, obtains average sample
Then mean value SI and SQ are seeking absolute value to average sample the mean value SI and SQ, are then carrying out respectively to the absolute value
Peak detection and Edge check obtain peak indication signal and edge indication signal, recycle the peak indication signal knot later
It closes the edge indication signal and generates sampling enable signal SEN, while exporting average sample mean value SI and SQ.
The judging module is according to the received sampling enable signal SEN of institute, to institute under the conditions of the enabled SEN of sampling is effective
It states average sample mean value SI and SQ to be sampled, the sampled value is made decisions after obtaining sampled value, if sampled value is greater than 0,
Then decision value be 1, otherwise, decision value be -1, finally to decision value carry out change in polarity processing, output judgement after JI signal and
JQ signal.
PN code mapping table of the coherently despreading module by PN code represented by the bit data flow P2S, with internal system
In 16 PN codes carry out related calculation, symbol corresponding to the maximum PN code of correlation is as output data Dout.
A kind of the characteristics of digital bit synchronization method for noncoherent detection of the invention is to carry out as follows:
Step 1 is sampled and is filtered respectively to I, Q two paths of signals, and FI signal and FQ signal are obtained；
Step 2, the delay disposal that a code-element period Tc is carried out to the FI signal, obtain DI signal；
Step 3 carries out mean value computation, Edge check and peak detection process to the DI signal and FQ signal, is adopted
Sample enable signal SEN, average sample mean value SI and SQ；
Step 4, according to the sampling enable signal SEN, the sample mean SI and SQ is made decisions and polarity turn
Processing is changed, JI signal and JQ signal are obtained；
Step 5 after the JI signal and JQ signal are converted into serial bit data flow P2S, then carries out demodulation calculating,
Output data Dout after being demodulated.
Compared with the prior art, the invention has the advantages that:
1, present system utilizes matched filtering module, bit sync module, judging module, parallel serial conversion module, related solution
Expand module；Phaselocked loop and bit timing module are not needed, to reduce the area shared by realizing noncoherent detection bit synchronization in the chips,
Chip cost is reduced, full digital starting, algorithm are simple, are easily achieved.
2, bit sync module of the present invention is calculated and is compared by simple signal magnitude, realizes the low of more modulation mode
Cost is synchronous, synchronous without clock, reduces the requirement to system clock, reduces the complexity of design.
3, coherently despreading 16 road signal multiplexing, 1 correlator in coherently despreading module of the present invention, saves hardware resource；
4, configurable matched filter is used in matched filtering module of the present invention, can flexibly handle various modulation systems
Signal, precision are high, are suitable for plurality of communication systems.
5, the method for the present invention is to complete signal detection bit synchronization using signal waveform matching, peak detection, Edge check etc.
Method, this method be not necessarily to phaselocked loop, directly utilize modulated signal amplitude Characteristics progress Direct Sequence Spread Spectrum despreading, method
It is simple and easy, reduce hardware resource, reduces system cost, reduce system power dissipation, reduce the bit error rate.
Detailed description of the invention
Fig. 1 is present system functional block diagram；
Fig. 2 is bit synchronization submodule block diagram of the present invention；
Fig. 3 is the block diagram of mean module of the present invention；
Fig. 4 is the block diagram of coherently despreading module of the present invention；
Fig. 5 is the schematic diagram of correlator of the present invention.
Specific embodiment
In the present embodiment, as shown in Figure 1, a kind of digital bit synchronization system for noncoherent detection is that work connects in number
Inside receipts machine, for detecting and demodulating the digital baseband signal received, comprising: matched filtering module, bit sync module, judgement
Module, parallel serial conversion module, coherently despreading module；
In matched filtering module, the signal for enabling I-ADC export is I, and the output signal of Q-ADC is Q, and I signal is connected to I
The input terminal of the matched filter on road, Q signal are connected to the input terminal of the matched filter on the road Q, and the output end of I path filter is
The output end of FI, Q path filter is FQ.Matched filtering module receives externally input I, Q two paths of signals and is sampled respectively
And filtering processing, after obtaining FI signal and FQ signal, FQ signal is exported to bit sync module, FI signal is exported and gives delay mould
Block；
In specific implementation, the process that matched filtering module is filtered using configurable control signal Ctrl signal control,
So that matched filtering module can work according to corresponding configuration in different filter states；Wherein, Ctrl signal is from deposit
Device can change the numerical value of Ctrl by writing register.
The input terminal of Postponement module is connected to the output end FI of the road I matched filter, output end DI, can be according to difference
Configuration to received FI signal carry out the delay disposal of a code-element period Tc, pass to bit synchronization mould after obtaining DI signal
Block；So that symbol alignment when the road I, Q signal reaches the input terminal of bit sync module.
Bit sync module is as shown in Fig. 2, by mean module, ask absolute value block, peak detection block, Edge check module
It is formed with control unit, its first input end is enabled to connect the road I signal DI, the second input terminal connects the road Q signal FQ, the first output end
For SI, second output terminal SQ, third output end is SEN, which respectively carries out the received DI signal of institute and FQ signal equal
Value calculating, Edge check and peak detection process obtain sampling enable signal SEN, average sample mean value SI and SQ, and defeated together
Out to judging module；Wherein, Edge check is easy to be influenced by input noise interference, increases mean value mould before Edge check
Block, can smooth input terminal signal, the malfunction of input noise bring is effectively reduced to reach.Mean module such as Fig. 3 institute
Show, including summation module and module of averaging, first to the 2^k of input (k=1,2,3 ..., n) a data (D0, D1,
D2 ...) it is summed to obtain sum, it then averages to sum, according to the feature of digital circuit, mean module is without answering
Miscellaneous divide operations, it is only necessary to cut out the low k data (k=2 in Fig. 3) of sum, to obtain average value average, save hard
Part resource.
Specifically, mean filter processing is carried out to DI signal and FQ signal first, obtains average sample mean value SI and SQ,
Then absolute value is being sought to average sample mean value SI and SQ, peak detection then is carried out respectively to absolute value and Edge check obtains
To peak indication signal and edge indication signal, recycling peak indication signal combination edge indication signal to generate sampling later makes
Energy signal SEN, while average sample mean value SI and SQ are exported, SI, SQ are the road I, Q signal after synchronizing.
Judging module makes decisions sample mean SI and SQ and polarity according to the received sampling enable signal SEN of institute
Conversion process obtains JI signal and JQ signal, and exports to parallel serial conversion module；Wherein, JI is the data after the judgement of the road I, JQ
Specifically for the data after the judgement of the road Q,
Judging module enables its first input end be connected to SI, and the second fan-in is connected to SQ, the connection of third input terminal
To SEN, the first output end is JI, second output terminal JQ；The module is according to the received sampling enable signal SEN of institute, using adopting
Sample enables condition and samples to average sample mean value SI and SQ, makes decisions after obtaining sampled value to sampled value, if sampled value
Greater than 0, then decision value is 1, and otherwise, decision value is -1, finally carries out change in polarity processing to decision value, it is serial to revert to the road I
The road sequence signal JI and q serial sequence signal JQ.
Parallel serial conversion module enables its first input end be connected to JI, and the second input terminal is connected to JQ, output end P2S；It should
Module passes to coherently despreading module after JI signal and JQ signal to be converted into serial data flow P2S signal；Wherein P2S be I,
Serial data stream after the merging of Q two paths of signals.
Coherently despreading module enables its input terminal be connected to P2S, output end DOUT, for carrying out to serial data stream P2S
Demodulation calculates, the output data Dout after being demodulated.Wherein DOUT is the data after the demodulation of the road I, Q signal, specifically,
Coherently despreading module is made of controller, correlator, PN code and its mapping, judging module, structural block diagram such as Fig. 4 institute
Show, chip of the 16 PN codes in PN code mapping table all with 32 is controlled by controller and carries out a related operation, 16 phases
After closing operation, decision device makes decisions 16 operation results, selects symbol corresponding to the maximum PN code of correlated results
It is exported as despread data.I.e. by 16 in PN code represented by bit data flow P2S, with the PN code mapping table of internal system
PN code carries out related calculation, and symbol corresponding to the maximum PN code of correlation is as output data Dout.With the use parallel phase in 16 tunnels
Operation is closed, the present invention saves 15 correlators using the method for multiplexing.Correlator circuit structure is as shown in figure 5, correlator pair
Each of 32 chips and PN code are done same or, then summing to resulting 32 results respectively, and acquire and work
For correlated results output；Existing correlator circuit mostly uses multiplier to realize greatly, in contrast: correlator of the invention is saved
Hardware resource.
Wherein, judging module, parallel serial conversion module, coherently despreading module are worked under the action of gated clock, energy
It is enough to complete work in the case where more much lower than system clock, to effectively reduce system power dissipation.
In the present embodiment, a kind of digital bit synchronization method for noncoherent detection is to carry out as follows:
Step 1 is sampled and is filtered respectively to I, Q two paths of signals, and FI signal and FQ signal are obtained；
Step 2, the delay disposal that a code-element period Tc is carried out to FI signal, obtain DI signal
Step 3 carries out mean value computation, Edge check and peak detection process to DI signal and FQ signal, and obtaining sampling makes
It can signal SEN, average sample mean value SI and SQ；
Step 4, according to sampling enable signal SEN, sample mean SI and SQ are made decisions and dipole inversion processing, obtain
To JI signal and JQ signal；
Step 5 after JI signal and JQ signal are converted into serial bit data flow P2S, then carries out demodulation calculating, obtains
Output data Dout after demodulation.
In conclusion the present invention can rapidly carry out noncoherent detection bit synchronization, realize digital demodulation despreading, and have
Have that small power consumption, area are small, stability is high, small advantage is influenced by the external world.
Claims (6)
1. a kind of digital bit synchronization system for noncoherent detection, feature include: matched filtering module, bit sync module,
Judging module, parallel serial conversion module, coherently despreading module；
The matched filtering module receives externally input I, Q two paths of signals and is sampled and be filtered respectively, obtains FI
After signal and FQ signal, the FQ signal is exported to the bit sync module, the FI signal is exported to Postponement module；
The Postponement module to received FI signal carry out the delay disposal of a code-element period Tc, transmitted after obtaining DI signal
To the bit sync module；
The bit sync module carries out mean value computation, Edge check and peak detection to the received DI signal of institute and FQ signal respectively
Processing obtains sampling enable signal SEN, average sample mean value SI and SQ, and is exported together to the judging module；
The judging module makes decisions average sample the mean value SI and SQ according to the received sampling enable signal SEN of institute
With dipole inversion processing, JI signal and JQ signal are obtained, and is exported to the parallel serial conversion module；
The JI signal and JQ signal are converted into passing to after serial bit data flow P2S described by the parallel serial conversion module
Coherently despreading module；
The coherently despreading module carries out demodulation calculating to the bit data flow P2S, the output data Dout after being demodulated.
2. the digital bit synchronization system according to claim 1 for noncoherent detection, it is characterised in that: the matching filter
Wave module use can configure matched Ctrl signal control filter process so that the matched filtering module energy according to
Corresponding configuration works in different filter states.
3. the digital bit synchronization system according to claim 1 for noncoherent detection, it is characterised in that: the bit synchronization
Module carries out mean filter processing to the DI signal and FQ signal first, obtains average sample mean value SI and SQ, then right again
Average sample the mean value SI and SQ seek absolute value, then carry out peak detection respectively to the absolute value and Edge check obtains
To peak indication signal and edge indication signal, the peak indication signal is recycled to produce in conjunction with the edge indication signal later
Raw sampling enable signal SEN, while exporting average sample mean value SI and SQ.
4. the digital bit synchronization system according to claim 1 for noncoherent detection, it is characterised in that: the judgement mould
Root tuber according to the received sampling enable signal SEN of institute, sample enabled SEN it is effective under the conditions of to the average sample mean value SI with
SQ is sampled, and is made decisions after obtaining sampled value to the sampled value, if sampled value is greater than 0, otherwise decision value 1 is sentenced
Certainly value is -1, finally carries out change in polarity processing, JI signal and JQ signal after output judgement to decision value.
5. the digital bit synchronization system according to claim 1 for noncoherent detection, it is characterised in that: the related solution
Expand module for PN code represented by the bit data flow P2S, is done to 16 PN codes in the PN code mapping table of internal system related
Operation, symbol corresponding to the maximum PN code of correlation is as output data Dout.
6. a kind of digital bit synchronization method for noncoherent detection, it is characterized in that carrying out as follows:
Step 1 is sampled and is filtered respectively to I, Q two paths of signals, and FI signal and FQ signal are obtained；
Step 2, the delay disposal that a code-element period Tc is carried out to the FI signal, obtain DI signal；
Step 3 carries out mean value computation, Edge check and peak detection process to the DI signal and FQ signal, and obtaining sampling makes
It can signal SEN, average sample mean value SI and SQ；
Step 4, according to the sampling enable signal SEN, average sample the mean value SI and SQ are made decisions and dipole inversion
Processing, obtains JI signal and JQ signal；
Step 5 after the JI signal and JQ signal are converted into serial bit data flow P2S, then carries out demodulation calculating, obtains
Output data Dout after demodulation.
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| US20120093206A1 (en) * | 2010-10-18 | 2012-04-19 | Qualcomm Incorporated | Radio data system monophonic demodulation |
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| CN105306397A (en) * | 2015-11-13 | 2016-02-03 | 成都天奥信息科技有限公司 | DQPSK intermediate frequency differential demodulation method |
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