CN106712746A - Clock rate supply system - Google Patents
Clock rate supply system Download PDFInfo
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- CN106712746A CN106712746A CN201510794497.3A CN201510794497A CN106712746A CN 106712746 A CN106712746 A CN 106712746A CN 201510794497 A CN201510794497 A CN 201510794497A CN 106712746 A CN106712746 A CN 106712746A
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- 230000008054 signal transmission Effects 0.000 claims abstract description 11
- 210000001367 artery Anatomy 0.000 claims description 13
- 210000003462 vein Anatomy 0.000 claims description 13
- 230000009183 running Effects 0.000 claims description 11
- 238000005520 cutting process Methods 0.000 claims description 8
- 230000009471 action Effects 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 5
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 230000005540 biological transmission Effects 0.000 description 17
- 238000013461 design Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 11
- 238000012545 processing Methods 0.000 description 9
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/145—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of resonant circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
- H03H9/205—Constructional features of resonators consisting of piezoelectric or electrostrictive material having multiple resonators
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- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention provides a clock rate supply system comprising a multi-unit cell chip and a clock rate supply device. The multi-unit cell chip comprises a semiconductor substrate, a plurality of unit cells and a plurality of signal transmission line groups. These unit cells can be arranged on the semiconductor substrate. The unit cells and adjacent unit cells can have at least one interval space. The signal transmission line groups can be configured on the interval spaces between the adjacent unit cells and be applied to the signal transmission between the adjacent unit cells. The multi-unit cell chip can be cut by a part of the interval spaces to cut off a part of the signal transmission line groups, so that the multi-unit cell chip can be divided into a plurality of sub-chips, and the part of cut sub-chips can still be used. The clock rate supply device can be coupled to at least one interface unit cell in these unit cells. The clock rate supply device can provide working clock rate signals necessary for the operation of the unit cells through the at least one interface unit cell and the signal transmission line groups. Therefore, the overall stability of the clock rate supply system is improved.
Description
Technical field
The invention relates to a kind of clock pulse supply system, and in particular to a kind of many structure cell chips
Clock pulse supply system.
Background technology
In the epoch of information explosion now, integrated circuit has inseparable relation, nothing with daily life
In terms of living to go and educating pleasure in food clothing, generally can all use to the electronic product being made up of integrated circuit component.
With the continuous evolution of manufacture of semiconductor technology, more and more operation processing units can be integrated into single
In chip, and can be made using the manufacture of semiconductor technology of high-order.Due to the semiconductor system using high-order
The cost of manufacture (such as light shield) of journey incurs a considerable or great expense, therefore existing scheme is mostly examining based on computing power high
Amount carrys out design chips.If user's considering come design chips based on computing power high, such as transport multiple
Calculation processing unit is integrated in so far chip, then the cost of the chip of this computing power high can be higher, is also not suitable for
Apply at a low price and in the electronic product of low computing power demand.That is, current programme is designed in chip
Or after completing, just cannot again provide user carries out bullet between chip computing power and chip cost
Property ground selection.
In addition, this little operation processing unit in chip need to be couple to a time clock source.Thereby, clock pulse
Source can simultaneously supply this little operation processing unit running required clock signal, so that this little calculation process list
Unit can normal operation.However, when this little operation processing unit react on received clock signal and
When same time section is operated together, be likely to result in electronic product reduces because instantaneous power consumption is excessive
The transient stability of the power system of electronic product.
The content of the invention
In view of this, the present invention provides a kind of clock pulse supply system, it is possible to provide many in clock pulse supply system
Work time pulse signal needed for the running of structure cell chip, wherein after many structure cell chips connect required power supply and signal
It is usable (can operate).When many structure cell chips are not yet cut again, data can be in many structure cell cores
Decentralized processing is carried out in multiple structure cells in piece.And the signal of the different structure cells in many structure cell chips can pass through
Signal transmssion line group between structure cell is transmitted.In addition, the also visual practical application of user, institute
Need operational capability or considering for cost and many structure cell chips are flexibly cut in units of structure cell,
To be cut into many sub- chips, wherein the portion's molecular chip after cutting still may be used after connecting required power supply and signal
Use (can still operate).In addition, the clock pulse supply system can reduce instantaneous power consumption, when can also reduce
Switching noise produced during the transition simultaneously of the work time pulse signal of each structure cell in arteries and veins supply system, so as to carry
Rise the monolithic stability degree of clock pulse supply system.In addition, the clock pulse transmission means between each structure cell can lead to
Cross and change in each structure cell clock pulse selecting sequence set in advance and be adjusted.Therefore, clock pulse confession can be increased
Answer system elasticity in design.
Clock pulse supply system of the invention may include many structure cell chips and clock pulse supply device.Many structure cell cores
Piece may include semiconductor base, multiple structure cells and multiple signal transmssion line groups.This little structure cell can be arranged in
On semiconductor base.Can have at least one to be separated by space between each structure cell and adjacent structure cell.Each signal transmission
Line group is configurable on being separated by spatially between adjacent cell, and is used for the biography of the signal between adjacent cell
Defeated action.Above-mentioned many structure cell chips are usable (can operate), and many structure cell chips can be by part
This is separated by space and is cut this little signal transmssion line group with cut-off parts, causes many structure cell chips can quilt
Many sub- chips are divided into, wherein this little chip of part after cutting still can be used (can still operate).Clock pulse
Feeding mechanism can couple at least one of this little structure cell interface structure cell.Clock pulse supply device can be by least
One interface structure cell provides each structure cell running required work time pulse signal with this little signal transmssion line group.
In one embodiment of this invention, there can be multiple weld pads on above-mentioned each structure cell.Each at least one connects
At least one of this little weld pad on mouth structure cell may be coupled to clock pulse supply device to receive at least one first
Clock signal.
In one embodiment of this invention, when each structure cell judges to receive at least 1 from clock pulse supply device
During one clock signal, each structure cell may be selected this at least one first clock signal as each structure cell work when
Arteries and veins signal, each structure cell can using this at least one first clock signal as at least one second clock signal and along
First direction is sent to the first adjacent structure cell, and each structure cell can using this at least one first clock signal as
At least one the 3rd clock signal is simultaneously sent to the second adjacent structure cell along second direction.
In one embodiment of this invention, when each structure cell judges not receive at least one from clock pulse supply device
During the first clock signal, each structure cell can determine whether from the adjacent structure cell of third phase receive at least one second when
Arteries and veins signal.If the determination result is YES, each structure cell may be selected this at least one second clock signal as each crystalline substance
The work time pulse signal of born of the same parents, and each structure cell can along a first direction transmit this at least one second clock signal
To the first adjacent structure cell.If judged result is no, each structure cell may be selected from the 4th adjacent structure cell
At least one the 3rd clock signal as each structure cell work time pulse signal, each structure cell can by this at least one the 3rd
Clock signal is sent to the first adjacent structure cell along a first direction, and each structure cell can by this at least one the 3rd
Clock signal is sent to the second adjacent structure cell along second direction.
In one embodiment of this invention, when each structure cell judges to receive at least 1 from clock pulse supply device
During one clock signal, each structure cell can be produced according to this at least one first clock signal and correspond at least one second
Second synchronizing signal of clock signal, each structure cell can be produced according to this at least one first clock signal and corresponded to
At least the 3rd synchronizing signal of one the 3rd clock signal, each structure cell can be by the second synchronizing signal along first party
To being sent to the first adjacent structure cell, and along second direction can be sent to the 3rd synchronizing signal by each structure cell
Second adjacent structure cell.Each structure cell may be selected input of this at least one first clock signal as each structure cell
Clock signal, each structure cell may be selected the input of the second synchronizing signal or the 3rd synchronizing signal as each structure cell
Synchronizing signal, and the work time pulse signal of each structure cell is produced according to this.The cycle of the second synchronizing signal and the 3rd
The cycle of synchronizing signal more than this at least one first clock signal cycle, and the second synchronizing signal cycle
With the integral multiple in be this at least cycle of one first clock signal in the cycle of the 3rd synchronizing signal.
In one embodiment of this invention, when each structure cell judges not receive this at least from clock pulse supply device
During one first clock signal, each structure cell can determine whether to receive at least one second from the adjacent structure cell of third phase
Clock signal and the second synchronizing signal.If the determination result is YES, each structure cell may be selected at least one second clock pulse
Signal and the second synchronizing signal are using the input clock signal as each structure cell and input sync signal and evidence
To produce the work time pulse signal of each structure cell, and will at least one second clock signal and the second synchronizing signal edge
First direction and be sent to the first adjacent structure cell.If judged result is no, each structure cell may be selected from the
At least one the 3rd clock signal of four adjacent structure cells and the 3rd synchronizing signal are using as the defeated of each structure cell
Enter clock signal and input sync signal and produce the work time pulse signal of each structure cell according to this, each structure cell can be by
At least one the 3rd clock signal is sent to the first adjacent structure cell along a first direction with the 3rd synchronizing signal,
And at least one the 3rd clock signal and the 3rd synchronizing signal can be sent to second by each structure cell along second direction
Adjacent structure cell.
In one embodiment of this invention, above-mentioned each structure cell can be synchronous with input according to input clock signal
Signal is to produce work time pulse signal, so that each structure cell can react on work time pulse signal and be input into synchronously
Different time sections or different time points in the cycle of signal are operated.
In one embodiment of this invention, when each structure cell judges to receive at least 1 from clock pulse supply device
During one clock signal, each structure cell may be selected this at least one first clock signal as each structure cell work when
Arteries and veins signal, and each structure cell can be using this at least one first clock signal is as at least one second clock signal and passes
Deliver to all adjacent structure cells.
In one embodiment of this invention, when each structure cell judges not receive this at least from clock pulse supply device
During one first clock signal, each structure cell may be selected from the one of which in the adjacent structure cell in part at least
One second clock signal as each structure cell work time pulse signal, and each structure cell can by it is selected at least
One second clock signal is sent to remaining adjacent structure cell.
In one embodiment of this invention, above-mentioned each at least interface structure cell is connect from clock pulse supply device
The frequency or phase of at least one first clock signal for receiving are incomplete same.
In one embodiment of this invention, above-mentioned each at least interface structure cell is connect from clock pulse supply device
At least one first clock signal for receiving is a differential-pair signal.
Based on above-mentioned, the clock pulse supply device of the embodiment of the present invention can be by least in many structure cell chips
Individual interface structure cell provides the running of each structure cell in many structure cell chips required work with signal transmssion line group
Make clock signal, wherein being usable (can operate) after many structure cell chips connect required power supply and signal.
When many structure cell chips are not yet cut again, data can be carried out in the multiple structure cells in many structure cell chips
Decentralized processing.And the signal of the different structure cells in many structure cell chips can be by the signal transmssion line between structure cell
Group is transmitted.In addition, the also visual practical application of user, required operational capability or cost are examined
Measure and many structure cell chips are flexibly cut in units of structure cell, to be cut into many sub- chips,
Portion's molecular chip after wherein cutting still can be used (can still operate) after connecting required power supply and signal.And,
Clock pulse transmission means between each structure cell can by change in each structure cell clock pulse selecting sequence set in advance come
It is adjusted.Therefore, clock pulse supply system elasticity in design can be increased.In addition, each structure cell
Work time pulse signal can be adjusted according to the operating requirements of itself or physical characteristic, so that each structure cell can
Operated in different time sections or different time points.Thus, it is possible to decrease clock pulse supply system
Instantaneous power is consumed, and produced switching is made an uproar when can also reduce the work time pulse signal transition simultaneously of each structure cell
Sound, so as to lift the monolithic stability degree of clock pulse supply system.
It is that features described above of the invention and advantage can be become apparent, special embodiment below, and coordinate
Accompanying drawing is described in detail below.
Brief description of the drawings
Following accompanying drawing is a part for specification of the invention, shows example embodiment of the invention,
Accompanying drawing illustrates principle of the invention together with the description of specification.
Fig. 1 is the schematic diagram according to the clock pulse supply system shown by one embodiment of the invention；
Fig. 2 is the schematic diagram according to the clock pulse supply system shown by another embodiment of the present invention；
Fig. 3 is according to the clock pulse transfer process figure between each structure cell shown by one embodiment of the invention；
Fig. 4 is according to the clock pulse waveform diagram shown by one embodiment of the invention；
Fig. 5 A are to operate the sequential under burst mode to show according to the structure cell shown by one embodiment of the invention
It is intended to；
Fig. 5 B are the sequential according to the structure cell operation shown by another embodiment of the present invention in a continuous mode
Schematic diagram；
Fig. 6 is to transmit schematic diagram according to the clock pulse between each structure cell shown by another embodiment of the present invention；
Fig. 7 is shown according to the clock pulse transmission inside the clock pulse supply system shown by another embodiment of the present invention
It is intended to.
Description of reference numerals：
100、100’、200、300：Clock pulse supply system；
110、210、310：Many structure cell chips；
111~114,211~219,311~319：Structure cell；
120、220、320：Clock pulse supply device；
M、K：Numerical value；
OCI, OCI1~OCI4：Signal transmssion line group；
OCI_HCK、OCI_CK：Second clock signal；
OCI_HSYNC：Second synchronizing signal；
OCI_VCK：3rd clock signal；
OCI_VSYNC：3rd synchronizing signal；
OPCK：Work time pulse signal；
PAD、PAD1、PAD2：Weld pad；
PAD_CKI1, PAD_CKI2, PAD_CKI31~PAD_CKI33：First clock signal；
SUB：Semiconductor base；
SYNC：Input sync signal；
S320、S330、S340、S350、S360：Step；
T：Cycle, unit period；
NT：Cycle.
Specific embodiment
With detailed reference to one exemplary embodiment of the invention, the one exemplary embodiment is illustrated in the accompanying drawings
Example.In addition, all possible parts, use the element/component of identical label in schema and implementation method
Represent same or like part.
Fig. 1 is refer to, Fig. 1 is the signal according to the clock pulse supply system shown by one embodiment of the invention
Figure.Clock pulse supply system 100 may include many structure cell chips 110 and clock pulse supply device 120.Polycrystalline
Born of the same parents' chip 110 may include semiconductor base SUB, multiple structure cells 111~114 and multiple signal transmssion lines
OCI1~OCI4 is organized, but the present invention is not limited thereto.Structure cell 111~114 can configure and be arranged in and partly leads
Have at least one to be separated by space between structure cell on body substrate SUB and adjacent.In addition, each signal transmssion line
Group OCI1~OCI4 can be configured in being separated by spatially between adjacent structure cell, and can be used as between adjacent cell
Signal transmission action (such as clock pulse transmission action or data transfer activity) medium.It is understood that
Many structure cell chips 110 are usable (can operate) after required power supply and signal is connected.
For example, signal transmssion line group OCI1 is configurable on structure cell 111 and structure cell 112 adjacent thereto
Between be separated by spatially.Signal transmssion line group OCI1 can couple structure cell 111,112 and as structure cell 111,
The medium of signal transmission action (such as clock pulse transmission action or data transfer activity) between 112.When many structure cells
When chip 110 is not yet cut again, data can be (such as brilliant in the multiple structure cells in many structure cell chips 110
Decentralized processing is carried out in born of the same parents 111~114).In addition, being separated by space and can provide as cutting between adjacent cell
Cut and turn into the space of cutting.In other words, when required structure cell quantity can with it is less when, can be with
It is separated by space to part by the action cut to be cut with the signal transmssion line group of cut-off parts (for example
Signal transmssion line group OCI2, OCI4) so that many structure cell chips 110 are cut into many sub- chips, and
And, each sub- chip after cutting still can be used (can still operate) after required power supply and signal is connected.
Each signal transmssion line group OCI1~OCI4 can include a plurality of wire, and these wires can be using covering
One or more layers the patterned metal layer of semiconductor base SUB is formed.In addition, each structure cell 111~114
Can also have multiple weld pad PAD, these weld pads PAD to be configurable on the top layer of structure cell 111~114.
There can be at least one interface structure cell (such as structure cell 111) in structure cell 111~114.Clock pulse supply dress
Put 120 and may be coupled to this interface structure cell (structure cell 111), and can be by this interface structure cell (structure cell 111) and crystalline substance
Signal transmssion line group OCI1~OCI4 between born of the same parents 111~114 is provided needed for the running of structure cell 111~114
Work time pulse signal.
Subsidiary one carries, the quantity and array of the structure cell 111~114 of many structure cell chips 110 shown in Fig. 1
Arrangement mode is merely an example, and is not used to the limitation present invention.In fact, proposed by the invention
The quantity of the structure cell of many structure cell chips can be by designer according to practical application or design requirement with arrangement mode
And be adjusted.
In an one exemplary embodiment of the invention, clock pulse supply device 120 can by packaging and routing come with
Weld pad PAD (such as weld pad PAD1) on interface structure cell (structure cell 111) produces electric connection, but the present invention
It is not limited thereto.In another one exemplary embodiment of the invention, clock pulse supply device 120 can also lead to
The chip interconnection technique and the weld pad PAD on interface structure cell (structure cell 111) for crossing flip (flip chip) (are for example welded
Pad PAD1) produce electric connection.The present invention is not intended to limit clock pulse supply device 120 and interface structure cell (structure cell
111) the electric connection mode of the weld pad PAD on.
In the one exemplary embodiment shown in Fig. 1 of the present invention, structure cell 111 can be by one of weld pad
PAD1 is coupled to clock pulse supply device 120 to receive the first clock signal PAD_CKI1, wherein, the
One clock signal PAD_CKI1 can be for example the data signal of full swing (full swing), but the present invention is simultaneously
It is not limited.
Below referring to Fig. 1 and Fig. 2, Fig. 2 be according to shown by another embodiment of the present invention when
The schematic diagram of arteries and veins supply system.Clock pulse supply system 100 ' shown in Fig. 2 equally may include many structure cell chips
110 and clock pulse supply device 120.Many structure cell chips 110 may include semiconductor base SUB, Duo Gejing
Born of the same parents 111~114 and multiple signal transmssion line group OCI1~OCI4.However, compared to Fig. 1, Fig. 2's
Structure cell 111 can be coupled to clock pulse supply device 120 to receive respectively by two weld pads PAD1, PAD2
First clock signal PAD_CKI1, PAD_CKI2, wherein, the first clock signal PAD_CKI1,
PAD_CKI2 can be for example the differential-pair signal (differential pair of signals) of the small amplitude of oscillation.Such one
Come, under the premise of frequency for not influenceing first clock signal PAD_CKI1, PAD_CKI2, when
Arteries and veins supply system 100 ' can reach power saving and drop using the clock pulse supply device 120 of relatively low driving force
The effect of low hardware cost.In addition, the clock pulse supply system 100 shown in Fig. 1 and the clock pulse shown in Fig. 2
The function mode of supply system 100 ' is similar, therefore following only for the clock pulse supply system shown in Fig. 1
100 running is described in detail, and clock pulse supply system 100 ' shown in Fig. 2 can the rest may be inferred it.
Referring concurrently to Fig. 1 and Fig. 3, Fig. 3 it is again please below according to each shown by one embodiment of the invention
Clock pulse transfer process figure between structure cell.On startup after arteries and veins supply system 100, in step s 320,
Each structure cell can determine whether to receive the first clock signal from clock pulse supply device.By taking Fig. 1 as an example, structure cell
111~114 can judge whether to receive the first clock signal from clock pulse supply device 120 respectively
PAD_CKI1, wherein, structure cell 111 can determine whether out can from clock pulse supply device 120 receive first when
Arteries and veins signal PAD_CKI1, and structure cell 112~114 can determine whether out not connect from clock pulse supply device 120
Receive the first clock signal PAD_CKI1.
If judged result in step s 320 is yes, step S330 is performed.With the structure cell 111 of Fig. 1
As a example by, structure cell 111 may be selected work time pulses of the first clock signal PAD_CKI1 as structure cell 111
Signal；Structure cell 111 can be using the first clock signal PAD_CKI1 as the second clock signal OCI_HCK
And (such as the right of structure cell 111) is sent to the first adjacent structure cell (such as structure cell 112) along a first direction,
And structure cell 111 can be using the first clock signal PAD_CKI1 as the 3rd clock signal OCI_VCK and edge
Second direction (such as top of structure cell 111) and be sent to the second adjacent structure cell (such as structure cell 113).
If judged result in step s 320 is no, step S340 is performed.With the structure cell 112 of Fig. 1,
As a example by 113, structure cell 112,113 can then judge whether to receive the second clock pulse from the adjacent structure cell of third phase
Signal OCI_HCK, wherein the adjacent structure cell of above-mentioned third phase can be for example positioned at the left side of structure cell 112,113
Adjacent structure cell, but the present invention is not limited thereto.For example, the third phase of structure cell 112 is adjacent
Structure cell can be for example structure cell 111, and the adjacent structure cell of the third phase of structure cell 113 and not exist.Due to structure cell
Second clock signal OCI_HCK can be sent to structure cell 112, therefore structure cell by 111 in step S330
112 can determine whether out that the second clock signal OCI_HCK can be received from structure cell 111 in step 340.Remove
Outside this, due to structure cell 113 left side structure cell and do not exist, therefore structure cell 113 is in step 340 then
Can determine whether out not receive the second clock signal OCI_HCK.
If the judged result in step S340 is yes, step S350 is performed.With the structure cell 112 of Fig. 1
As a example by, structure cell 112 may be selected the second clock signal from the adjacent structure cell (i.e. structure cell 111) of third phase
OCI_HCK as structure cell 112 work time pulse signal, and structure cell 112 can be by the second clock signal
(such as right) is sent to first adjacent structure cell (such as right side of structure cell 112 to OCI_HCK along a first direction
The structure cell of side, not shown).
If the judged result in step S340 is no, step S360 is performed.With the structure cell 113 of Fig. 1
As a example by, structure cell 113 may be selected the 3rd clock signal from the 4th adjacent structure cell as structure cell 113
Work time pulse signal, wherein above-mentioned 4th adjacent structure cell can be for example positioned at the adjacent of the lower section of structure cell 113
Structure cell, but the present invention is not limited thereto.For example, the 4th adjacent structure cell of structure cell 113 can
E.g. structure cell 111.Because structure cell 111 can be in step S330 by the 3rd clock signal OCI_VCK
Structure cell 113 is sent to, therefore structure cell 113 may be selected the 3rd clock signal OCI_VCK from structure cell 111
As the work time pulse signal of structure cell 113.Structure cell 113 can make the 3rd clock signal OCI_VCK
(such as right of structure cell 113) is sent to first for the second clock signal OCI_HCK and along a first direction
Adjacent structure cell (structure cell 114), and structure cell 113 can be by the 3rd clock signal OCI_VCK along second party
The second adjacent structure cell is sent to (such as top) (for example the structure cell of the top of structure cell 113, not shown).
Similarly, structure cell 114 can judge that the second clock pulse can be received from structure cell 113 in step 340
Signal OCI_HCK, therefore structure cell 114 can in step 350 select the second clock pulse from structure cell 113
Signal OCI_HCK as structure cell 114 work time pulse signal, and structure cell 114 can be by the second clock pulse
(such as right) is sent to the first adjacent structure cell (such as structure cell to signal OCI_HCK along a first direction
The structure cell on 114 right sides, not shown).
Consequently, it is possible to the structure cell 111~114 shown in Fig. 1 can respectively according to the clock pulse transmission side shown in Fig. 3
Formula and obtain itself running needed for work time pulse signal.Subsidiary one carries, and above-mentioned shows of the invention
In exemplary embodiment, structure cell 111 is interface structure cell, first direction is right, second direction is top,
First adjacent cell of each structure cell is located at the right side of each structure cell, the second adjacent cell of each structure cell is located at each crystalline substance
The top of born of the same parents, the third phase vincial faces born of the same parents of each structure cell are located at left side, the 4th phase vincial faces of each structure cell of each structure cell
The lower section that born of the same parents are located at each structure cell is all merely an example, and is not used to the limitation present invention.
It is noted that when each structure cell 111~114 shown in Fig. 1 reacts on the work time pulse of itself
Signal and when same time section or same time point are operated together, be likely to result in clock pulse supply system
100 because instantaneous power consumption it is excessive reduce clock pulse supply system 100 power supply networking transient stability.
In addition, if the work time pulse signal of each structure cell 111~114 is when transition is carried out at same time point,
Switching noise (switching noise) produced by it is likely to be coupled to letter by semiconductor base SUB
Number transmission line group OCI1~OCI4, so as to reduce the signal transmission product of signal transmssion line group OCI1~OCI4
Matter, particularly the work time pulse signal in each structure cell 111~114 are under the situation of high-frequency signal.
Therefore, in an one exemplary embodiment of the invention, each structure cell 111~114 can according to itself
Operating requirements or physical characteristic (such as temperature, but not limited to this) and adjust its work time pulse signal so that
Each structure cell 111~114 can be operated in different time sections or different time points.Consequently, it is possible to can drop
The instantaneous power consumption of low clock pulse supply system 100, can also reduce the work time pulse of each structure cell 111~114
The signal switching noise produced when transition is carried out at same time point.
It is below according to an implementation of the invention referring to Fig. 1 and Fig. 4, Fig. 4 for further
Clock pulse waveform diagram shown by example.By taking the structure cell 111 of Fig. 1 as an example, when structure cell 111, judge can
When receiving the first clock signal PAD_CKI1 from clock pulse supply device 120 (namely structure cell 111 is interface
Structure cell), structure cell 111 can be produced according to the first clock signal PAD_CKI1 and correspond to the second clock signal
The second synchronizing signal OCI_HSYNC of OCI_HCK.Additionally, structure cell 111 can also be according to the first clock pulse
Signal PAD_CKI1 produces the 3rd synchronizing signal corresponding to the 3rd clock signal OCI_VCK
OCI_VSYNC.That is, the second synchronizing signal OCI_HSYNC and the 3rd synchronizing signal
OCI_VSYNC can be produced by interface structure cell (i.e. structure cell 111).
The transmission means of the clock signal being same as described by above-mentioned Fig. 3, structure cell 111 equally can be by second
(such as right) is sent to the first adjacent structure cell (structure cell to synchronizing signal OCI_HSYNC along a first direction
, and structure cell 111 equally (can for example go up the 3rd synchronizing signal OCI_VSYNC along second direction 112)
Side) it is sent to the second adjacent structure cell (structure cell 113).Therefore, synchronizing signal (such as between each structure cell
Two synchronizing signal OCI_HSYNC or the 3rd synchronizing signal OCI_VSYNC) transmission means refer to
The related description of Fig. 1 and Fig. 3 is stated to analogize to obtain it, be will not be repeated here.
As shown in figure 4, the cycle NT and the 3rd synchronizing signal of the second synchronizing signal OCI_HSYNC
The cycle NT of OCI_VSYNC more than the first clock signal PAD_CKI1 cycle T (or unit week
Phase T), and the second synchronizing signal OCI_HSYNC cycle NT and the 3rd synchronizing signal OCI_VSYNC
Cycle NT be the first clock signal PAD_CKI1 cycle T integral multiple (multiple is N), wherein
Multiple N can be for example 256, but not limited to this.Herein it is noted that multiple N can be to be stored in
Parameter in structure cell 111, and can be set according to practical application or design requirement.
In addition, structure cell 111 may be selected the first clock signal PAD_CKI1 as structure cell 111
Input clock signal.Structure cell 111 may be selected the second synchronizing signal OCI_HSYNC or the 3rd synchronizing signal
OCI_VSYNC as structure cell 111 input sync signal, and according to this produce structure cell 111 work
Clock signal.Structure cell 112,114 may be selected the second clock signal OCI_HCK as structure cell 112,
114 input clock signal.Structure cell 112,114 may be selected the second synchronizing signal OCI_HSYNC to make
It is the input sync signal of structure cell 112,114, and produces the work time pulse letter of structure cell 112,114 according to this
Number.Similarly, structure cell 113 may be selected the 3rd clock signal OCI_VCK as the defeated of structure cell 113
Enter clock signal.Structure cell 113 may be selected the 3rd synchronizing signal OCI_VSYNC as structure cell 113
Input sync signal, and the work time pulse signal of structure cell 113 is produced according to this.
In one embodiment of this invention, do not consider reduce structure cell 111~114 operating voltage and reduce
On the premise of the frequency of its work time pulse signal, structure cell 111~114 can be allowed to operate in burst mode (burst
mode).As shown in Figure 5A, Fig. 5 A are operated in clump according to the structure cell shown by one embodiment of the invention
Time diagram under hair pattern.Structure cell 111~114 can be according to produced work time pulse signal OPCK
And after input sync signal SYNC is triggered and postpones M unit period T (i.e. M × T), start
K unit period T of continuous operations (i.e. K × T).Numerical value M, K of each structure cell 111~114 can be storage
Parameter in each structure cell 111~114, and be positive integer.The numerical value M of each structure cell 111~114 can foundation
Practical application or design requirement and be set as different numerical value, and the numerical value K of each structure cell 111~114 also may be used
It is set as different numerical value according to practical application or design requirement, so that each structure cell 111~114 can be defeated
Enter the different time section among the cycle NT of synchronizing signal SYNC to be operated.Consequently, it is possible to can
The instantaneous power consumption of clock pulse supply system 100 is reduced, and when can reduce the work of each structure cell 111~114
Produced switching noise during arteries and veins signal OPCK transitions.
For example, it is assumed herein that the cycle NT of input sync signal SYNC is 256 unit periods
T.In order to allow each structure cell 111~114 can be in cycle NT (i.e. 256 lists of input sync signal SYNC
Bit period T) among different time section operated, structure cell 111 can be allowed in input sync signal SYNC
Trigger and postpone after 2 unit period T, start 10 unit period T of continuous operations；Can allow structure cell
112 after input sync signal SYNC is triggered and postpones 21 unit period T, starts continuous operations
20 unit period T；Structure cell 113 can be allowed to be triggered in input sync signal SYNC and postpone 50 lists
After bit period T, start 60 unit period T of continuous operations；And structure cell 114 can be allowed synchronous in input
After signal SYNC is triggered and postponed 120 unit period T, start 100 unit weeks of continuous operations
Phase T.
In another embodiment of the invention, structure cell 111~114 can also be allowed in the continuous of lower operating voltage
Operated under pattern (continue mode).It is another according to the present invention for below refer to Fig. 5 B, Fig. 5 B
Structure cell shown by embodiment operates time diagram in a continuous mode.Specifically, the present embodiment
The frequency of the work time pulse signal OPCK of structure cell 111~114 and the work of the structure cell 111~114 that staggers can be reduced
Make the phase of clock signal OPCK and reduced to reach clock pulse supply system 100 instantaneous power consumption and
Reduce the work(of switching noise produced during the work time pulse signal OPCK transitions of each structure cell 111~114
Effect.
As shown in Figure 5 B, structure cell 111~114 can according to produced work time pulse signal OPCK
Input sync signal SYNC is triggered and is postponed to be started working after M unit period T (i.e. M × T),
And worked once every K unit period T (i.e. K × T) after start-up operation, wherein, structure cell
The responsibility cycle (duty cycle) of 111~114 work time pulse signal OPCK can be for 50% (namely (K × T)
÷ 2), but the present invention is not limited thereto.Numerical value M, K of each structure cell 111~114 can be to be stored in respectively
Parameter in structure cell 111~114, and be positive integer.The numerical value M of each structure cell 111~114 can be according to reality
Using or design requirement and be set as different numerical value, and the numerical value K of each structure cell 111~114 also can foundation
Practical application or design requirement and be set as different numerical value so that each structure cell 111~114 can be same in input
Different time points among the cycle NT of step signal SYNC are operated, to reduce clock pulse supply system
100 instantaneous power consumption, and the work time pulse signal OPCK transitions of each structure cell 111~114 can be reduced
When produced switching noise.
For example, it is also assumed that the cycle NT of input sync signal SYNC is 256 unit periods
T.In order to allow each structure cell 111~114 can be in cycle NT (i.e. 256 lists of input sync signal SYNC
Bit period T) among different time points operated, structure cell 111 can be allowed in input sync signal SYNC
Trigger and postpone to be come into operation after 2 unit period T, and every 20 units after coming into operation
Cycle T is operated once；Structure cell 112 can be allowed to be triggered in input sync signal SYNC and postpone 4 units
Come into operation after cycle T, and operated once every 20 unit period T after coming into operation；
Structure cell 113 can be allowed to start fortune after input sync signal SYNC is triggered and postpones 6 unit period T
Make, and operated once every 20 unit period T after coming into operation；And structure cell 114 can be allowed defeated
Enter synchronizing signal SYNC to trigger and postpone to be come into operation after 8 unit period T, and coming into operation
Afterwards every 20 unit period T runnings once.
Fig. 6 is below refer to, Fig. 6 is according between each structure cell shown by another embodiment of the present invention
Clock pulse transmits schematic diagram.Similar to the framework of the clock pulse supply system 100 shown in Fig. 1, shown in Fig. 6
Clock pulse supply system 200 equally may include many structure cell chips 210 and clock pulse supply device 220.Polycrystalline
Born of the same parents' chip 210 equally may include that semiconductor base SUB, multiple structure cells 211~219 and multiple signals are passed
Defeated line group OCI.Therefore, the framework of the clock pulse supply system 200 shown in Fig. 6 refers to above-mentioned Fig. 1's
Related description, below repeats no more.However, the clock pulse between each structure cell 211~219 shown in Fig. 6 is passed
Defeated mode is different from Fig. 1 and Fig. 3, wherein, the direction of arrow shown in Fig. 6 is clock pulse supply system 200
In clock pulse transmission direction.
As shown in fig. 6, structure cell 211~219 can judge whether to be received from clock pulse supply device 220 respectively
First clock signal PAD_CKI1, wherein, structure cell 215 (i.e. interface structure cell) can determine whether out to be supplied from clock pulse
Device 220 is answered to receive the first clock signal PAD_CKI1, and structure cell 211~214,216~219 can
Judge not receive the first clock signal PAD_CKI1 from clock pulse supply device 220.
Because structure cell 215 can receive the first clock signal PAD_CKI1 from clock pulse supply device 220,
Therefore structure cell 215 may be selected work time pulse signals of the first clock signal PAD_CKI1 as structure cell 215.
Additionally, structure cell 215 can using the first clock signal PAD_CKI1 as the second clock signal OCI_CK simultaneously
It is sent to all adjacent structure cells (such as structure cell 212,214,216,218).
And structure cell 211~214,216~219 may be selected from the one of which in the adjacent structure cell in part
Second clock signal OCI_CK as structure cell 211~214,216~219 work time pulse signal, it is and brilliant
It is adjacent that selected second clock signal OCI_CK can be sent to remaining by born of the same parents 211~214,216~219
Structure cell.
For example, structure cell 212 may be selected from one of them adjacent structure cell (i.e. structure cell 215) second
Clock signal OCI_CK, and the second clock signal OCI_CK from structure cell 215 is sent to remaining
Adjacent structure cell (i.e. structure cell 211,213 and the structure cell (not shown) positioned at the lower section of structure cell 212).Structure cell
214 may be selected the second clock signal OCI_CK from one of them adjacent structure cell (i.e. structure cell 215),
And the second clock signal OCI_CK from structure cell 215 is sent to remaining adjacent structure cell (i.e. structure cell
211st, 217 and the structure cell (not shown) positioned at the left of structure cell 214).Specifically, since structure cell 211
The second clock signal OCI_CK can be received from two adjacent structure cells (i.e. structure cell 212,214), therefore
Structure cell 211 can be selected from one of them adjacent structure cell according to clock pulse selecting sequence set in advance
Second clock signal OCI_CK (for example may be selected the second clock signal OCI_CK from structure cell 212),
And selected second clock signal OCI_CK is sent to remaining adjacent structure cell (i.e. positioned at structure cell 211
Left and the structure cell (not shown) of lower section).And the clock pulse transmission means of structure cell 213,216~219 is referred to
State it is bright analogize to obtain it, therefore repeat no more.It follows that many structure cell chips 210 can be with interface structure cell (i.e.
Structure cell 215) centered on point, and by signal transmssion line group OCI and adjacent structure cell by the second clock signal
OCI_CK is sent to remaining structure cell 211~214,216~219 of many structure cell chips 210 in order.
Herein specifically, between each structure cell described in above-mentioned Fig. 3 and Fig. 6 embodiments
Clock pulse transmission means is merely example, and is not used to the limitation present invention.Between each structure cell of the invention when
Arteries and veins transmission means can be adjusted by changing in each structure cell clock pulse selecting sequence set in advance.
Fig. 7 is below refer to, Fig. 7 is according to the clock pulse supply system shown by another embodiment of the present invention
Internal clock pulse transmission schematic diagram.Similar to the framework of the clock pulse supply system 200 shown in Fig. 6, Fig. 7
Shown clock pulse supply system 300 equally may include many structure cell chips 310 and clock pulse supply device 320.
Many structure cell chips 310 equally may include semiconductor base SUB, multiple structure cells 311~319 and multiple letters
Number transmission line group OCI.
However, compared in the structure cell 211~219 shown in Fig. 6 only have an interface structure cell (such as structure cell
215), can have in the structure cell 311~319 shown in Fig. 7 multiple interface structure cells (for example structure cell 311,315,
319).Clock pulse supply device 320 may be coupled to this little interface structure cell (structure cell 311,315,319), and can
By this multiple signal transmissions of a little interface structure cells (structure cell 311,315,319) and structure cell 311~319 between
Line group OCI come provide structure cell 311~319 running needed for work time pulse signal.
Particularly, structure cell 311,315,319 respectively from clock pulse supply device 320 receive first when
The frequency or phase of arteries and veins signal PAD_CKI31, PAD_CKI32, PAD_CKI33 can with identical,
Can also be incomplete same, depending on practical application or design requirement.In addition, each crystalline substance shown in Fig. 7
Clock pulse transmission means between born of the same parents 311~319 refers to the related description of Fig. 1~Fig. 6, below repeats no more.
One is attached herein is mentioned that the quantity and allocation position of the interface structure cell in embodiment illustrated in fig. 7 are only one
Individual example, and it is not used to the limitation present invention.In other words, designer can need according to practical application or design
Ask to adjust the quantity and allocation position of the interface structure cell in many structure cell chips 310.
In sum, the clock pulse supply device of the embodiment of the present invention can be by least in many structure cell chips
Individual interface structure cell provides the running of each structure cell in many structure cell chips required work with signal transmssion line group
Make clock signal, wherein being usable (can operate) after many structure cell chips connect required power supply and signal.
When many structure cell chips are not yet cut again, data can be carried out in the multiple structure cells in many structure cell chips
Decentralized processing.And the signal of the different structure cells in many structure cell chips can be by the signal transmssion line between structure cell
Group is transmitted.In addition, the also visual practical application of user, required operational capability or cost are examined
Measure and many structure cell chips are flexibly cut in units of structure cell, to be cut into many sub- chips,
Portion's molecular chip after wherein cutting still can be used (can still operate) after connecting required power supply and signal.And,
Clock pulse transmission means between each structure cell can by change in each structure cell clock pulse selecting sequence set in advance come
It is adjusted.Therefore, clock pulse supply system elasticity in design can be increased.In addition, each structure cell
Work time pulse signal can be adjusted according to the operating requirements of itself or physical characteristic, so that each structure cell can
Operated in different time sections or different time points.Thus, it is possible to decrease clock pulse supply system
Instantaneous power is consumed, and produced switching is made an uproar when can also reduce the work time pulse signal transition simultaneously of each structure cell
Sound, so as to lift the monolithic stability degree of clock pulse supply system.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than right
Its limitation；Although being described in detail to the present invention with reference to foregoing embodiments, this area it is common
Technical staff should be understood：It can still modify to the technical scheme described in foregoing embodiments,
Or equivalent is carried out to which part or all technical characteristic；And these modifications or replacement, and
The scope of the essence disengaging various embodiments of the present invention technical scheme of appropriate technical solution is not made.
Claims (11)
1. a kind of clock pulse supply system, it is characterised in that including：
Many structure cell chips, including：
Semiconductor base；
Multiple structure cells, are arranged on the semiconductor base, and each structure cell has between adjacent structure cell
At least one is separated by space；And
Multiple signal transmssion line groups, each signal transmssion line is assembled put and be separated by described between adjacent cell
Spatially, and be used to carry out the signal transmission between adjacent cell action,
Wherein described polycrystalline born of the same parents chip be it is usable, and many structure cell chips by part those be separated by
Space is cut with those signal transmssion line groups of cut-off parts, causes many structure cell chips to be divided into
Many sub- chips, wherein the part a little chip after cutting still can be used；And
Clock pulse supply device, couples at least one of those structure cells interface structure cell,
Wherein, the clock pulse supply device is by least one interface structure cell and those signal transmssion lines
Group provides each structure cell running required work time pulse signal.
2. clock pulse supply system according to claim 1, it is characterised in that have on each structure cell
There are at least one of multiple weld pads, those weld pads on each at least one interface structure cell to be coupled to institute
Clock pulse supply device is stated to receive at least one first clock signal.
3. clock pulse supply system according to claim 2, it is characterised in that
When each structure cell judges to receive at least one first clock signal from the clock pulse supply device
When, at least one first clock signal described in each structure cell selection as each structure cell the work
Clock signal, at least one first clock signal is used as at least one second clock signal described in each structure cell general
And the first adjacent structure cell is sent to along a first direction, and when at least one first described in each structure cell general
Arteries and veins signal is sent to the second adjacent structure cell as at least one the 3rd clock signal and along second direction.
4. clock pulse supply system according to claim 3, it is characterised in that
When each structure cell judges not receive at least one first clock pulse letter from the clock pulse supply device
Number when, each structure cell judges whether to receive at least one second clock pulse letter from the adjacent structure cell of third phase
Number,
If the determination result is YES, at least one second clock signal described in each structure cell selection is as each institute
State the work time pulse signal of structure cell, and each structure cell will described at least one second clock signal along
The first direction is sent to the described first adjacent structure cell；
If judged result is no, each structure cell selection is from described in the 4th adjacent structure cell at least 1 the
Three clock signals as each structure cell the work time pulse signal, each structure cell will described at least one
3rd clock signal is sent to the described first adjacent structure cell, and each structure cell along the first direction
At least one the 3rd clock signal is sent to the described second adjacent structure cell along the second direction.
5. clock pulse supply system according to claim 3, it is characterised in that
When each structure cell judges to receive at least one first clock signal from the clock pulse supply device
When, each structure cell according at least one first clock signal produce correspond to described at least one second when
Second synchronizing signal of arteries and veins signal, each structure cell at least one first clock signal according to produces correspondence
In the 3rd synchronizing signal of at least one the 3rd clock signal, each structure cell is synchronously believed described second
Number it is sent to the described first adjacent structure cell along the first direction, and each structure cell is by the described 3rd
Synchronizing signal is sent to the described second adjacent structure cell along the second direction,
Wherein, at least one first clock signal described in each structure cell selection is as the defeated of each structure cell
Enter clock signal, each structure cell select second synchronizing signal or the 3rd synchronizing signal as
The input sync signal of each structure cell, and the work time pulse signal of each structure cell is produced according to this,
Wherein, the cycle of the cycle of second synchronizing signal and the 3rd synchronizing signal more than it is described extremely
The cycle of few one first clock signal, and the cycle of second synchronizing signal and the 3rd synchronizing signal
Cycle be at least cycle of one first clock signal integral multiple.
6. clock pulse supply system according to claim 5, it is characterised in that when each structure cell is sentenced
Disconnected when not receiving at least first clock signal from the clock pulse supply device, each structure cell is sentenced
It is disconnected whether to receive at least one second clock signal letter synchronous with described second from the adjacent structure cell of third phase
Number,
If the determination result is YES, at least one second clock signal and described second described in each structure cell selection
Synchronizing signal is so that the input clock signal as each structure cell is with input sync signal and produces according to this
The work time pulse signal of each structure cell, and at least one second clock signal and described second by described in
Synchronizing signal is sent to the described first adjacent structure cell along the first direction；
If judged result is no, each structure cell selection is from described in the 4th adjacent structure cell at least 1 the
Three clock signals are with the 3rd synchronizing signal using the input clock signal as each structure cell
Produce with the input sync signal and according to this work time pulse signal of each structure cell, each crystalline substance
With the 3rd synchronizing signal be sent at least one the 3rd clock signal along the first direction by born of the same parents
Described first adjacent structure cell, and at least one the 3rd clock signal and the described 3rd described in each structure cell general
Synchronizing signal is sent to the described second adjacent structure cell along the second direction.
7. clock pulse supply system according to claim 6, it is characterised in that each structure cell according to
It is described to be input into clock signal with the input sync signal to produce the work time pulse signal, so that each institute
State structure cell and react on the work time pulse signal and during different within the cycle of the input sync signal
Between section or different time points operated.
8. clock pulse supply system according to claim 2, it is characterised in that when each structure cell is sentenced
It is disconnected from the clock pulse supply device receive at least first clock signal when, each structure cell selection
At least one first clock signal as each structure cell the work time pulse signal, it is and each described
Structure cell is using at least one first clock signal is as at least one second clock signal and is sent to all adjacent
Structure cell.
9. clock pulse supply system according to claim 8, it is characterised in that when each structure cell is sentenced
It is disconnected when not receiving at least first clock signal from the clock pulse supply device, each structure cell choosing
Select from least one second clock signal described in the one of which in the adjacent structure cell in part as each institute
State the work time pulse signal of structure cell, and each structure cell will selected at least one second clock pulse
Signal is sent to remaining adjacent structure cell.
10. clock pulse supply system according to claim 2, it is characterised in that each described at least connects
The frequency or phase of at least one first clock signal described in received by mouth structure cell from the clock pulse supply device
Position is incomplete same.
11. clock pulse supply systems according to claim 2, it is characterised in that each described at least one connects
At least one first clock signal described in received by mouth structure cell from the clock pulse supply device is that differential pair is believed
Number.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510794497.3A CN106712746A (en) | 2015-11-18 | 2015-11-18 | Clock rate supply system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510794497.3A CN106712746A (en) | 2015-11-18 | 2015-11-18 | Clock rate supply system |
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|---|---|---|---|---|
| CN1403887A (en) * | 2001-08-28 | 2003-03-19 | 富士通株式会社 | Semiconductor integrated circuit with function of begining and stopping supplying clock signal |
| US20100194434A1 (en) * | 2009-01-30 | 2010-08-05 | East-West Innovation Corporation | Systems and methods of integrated circuit clocking |
| CN102136246A (en) * | 2010-12-23 | 2011-07-27 | 友达光电股份有限公司 | Clock signal supply method and circuit of shift buffer |
| CN103036561A (en) * | 2011-09-28 | 2013-04-10 | 华晶科技股份有限公司 | Clock pulse supply device and method thereof |
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2015
- 2015-11-18 CN CN201510794497.3A patent/CN106712746A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1403887A (en) * | 2001-08-28 | 2003-03-19 | 富士通株式会社 | Semiconductor integrated circuit with function of begining and stopping supplying clock signal |
| US20100194434A1 (en) * | 2009-01-30 | 2010-08-05 | East-West Innovation Corporation | Systems and methods of integrated circuit clocking |
| CN102136246A (en) * | 2010-12-23 | 2011-07-27 | 友达光电股份有限公司 | Clock signal supply method and circuit of shift buffer |
| CN103036561A (en) * | 2011-09-28 | 2013-04-10 | 华晶科技股份有限公司 | Clock pulse supply device and method thereof |
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Application publication date: 20170524 |