CN106711245B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN106711245B CN106711245B CN201510437373.XA CN201510437373A CN106711245B CN 106711245 B CN106711245 B CN 106711245B CN 201510437373 A CN201510437373 A CN 201510437373A CN 106711245 B CN106711245 B CN 106711245B
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Abstract
The forming method of a kind of semiconductor structure and forming method thereof, wherein semiconductor structure includes：Substrate is provided；Semiconductor film is formed in the substrate surface；Graphene film is formed in the semiconductor film top surface；Black phosphorus film is formed in the graphene film top surface；Patterned mask layer is formed in the black phosphorus film top surface；Using the patterned mask layer as mask, graphical black phosphorus film, graphene film and the semiconductor film, some discrete semiconductor layers, the graphene layer positioned at semiconductor layer surface and the black phosphorus layer positioned at graphene layer top surface are formed in the substrate surface.The present invention provides a kind of structural behaviour superior semiconductor structure, improves the performance for the semiconductor structure to be formed.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
At present, the photonic propulsion based on silicon materials has turned into one of important research field in integrated optics.Based on silicon materials
The photonic device such as development such as optic communication passive device, adjuster, detector, image intensifer and Guangyuan it is more ripe.Due to
Silicon materials have an inherent shortcomings such as low electro-optic coefficient, lower light emission efficiency, non-broad band optical material and high propagation loss, and with
The continuous reduction of integrated circuit fields device size, silicon materials move closer to its manufacturing limit.Therefore optic communication and micro-nano light
Devices field development is learned there is an urgent need to a kind of mixing material can simultaneously with silicon materials characteristic and broad band light sub-feature, is
This semiconductor industry one after another propose surmount silicon technology (Beyond Silicon), wherein the graphene with larger potentiality to be exploited by
To extensive concern.
Graphene (Graphene) is a kind of two crystal of the carbon atom composition in monolayer honeycomb crystal lattice.Experiment card
Bright, graphene not only has very outstanding mechanical property and heat endurance, also with outstanding electric property, such as sub-micron
The ballistic transport characteristic of level, high carrier mobility, tunable band gap, quantum hall effect at room temperature etc., also, graphite
Alkene can realize the functions such as the transmitting of multifunctional signal, transmission, modulation, detection due to property itself in its material internal.
The superior electric property of graphene makes the graphene-based transistor of development and integrated circuit into possible, and is possible to take
It is referred to as the leading semiconductor material of a new generation for silicon, graphene can with silicon waveguide (silicon waveguide) integrated technology
Applied to novel photoelectric and device for non-linear optical, semiconductor industry shows great interest to this.Graphene and silicon waveguide collection
Into device, graphene (GSi, Graphene on Silicon) device alternatively referred to as on silicon, the graphene device tool on silicon
There is the graphene waveguide (GSi waveguide) on silicon.The graphene device how formed on the silicon, it is semiconductor applications mesh
One of preceding research emphasis.
However, the performance of the graphene device on the silicon that prior art is formed still has much room for improvement.
The content of the invention
It is of the invention to solve the problems, such as to be to provide a kind of semiconductor structure and forming method thereof, improve the property of semiconductor structure
Energy.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided；Institute
State substrate surface and form semiconductor film；Graphene film is formed in the semiconductor film top surface；At the top of the graphene film
Surface forms black phosphorus film；Patterned mask layer is formed in the black phosphorus film top surface；Using the patterned mask layer as
Mask, graphical black phosphorus film, graphene film and the semiconductor film, some discrete semiconductors are formed in the substrate surface
Layer, the graphene layer positioned at semiconductor layer surface and the black phosphorus layer positioned at graphene layer top surface.
Optionally, forming the method for the graphene film includes：Carbonaceous material film is formed on the semiconductor film surface；It is right
The carbonaceous material film and semiconductor film carry out the first annealing, and graphene is formed in the semiconductor film top surface
Film；After the described first annealing, the carbonaceous material film is removed.
Optionally, the material of the carbonaceous material film is poly- methyl-prop hexenoic acid methyl esters, makrolon, polyamide, poly- first
Aldehyde or polytetrafluoroethylene (PTFE).
Optionally, first annealing is laser annealing, Millisecond annealing or rapid thermal annealing.
Optionally, the annealing temperature of the laser annealing is 1400 degrees Celsius to 1500 degrees Celsius.
Optionally, first annealing includes temperature-rise period, insulating process and the temperature-fall period carried out successively.
Optionally, in the temperature-rise period and insulating process, carbon atom decomposites from the carbonaceous material film；
In the insulating process, the semiconductor film top surface is in molten condition, the semiconductor film top in molten condition
The carbon atom decomposited described in portion's Surface absorption；In the temperature-fall period, the carbon atom is analysed from semiconductor film top surface
Go out, the carbon atom of precipitation condenses in semiconductor film top surface to be nucleated, and graphene film is formed in the semiconductor film top surface.
Optionally, the thickness of the graphene layer is 1 angstrom to 100 angstroms；The thickness of the black phosphorus layer is 1 angstrom to 100 angstroms.
Optionally, forming the processing step of the black phosphorus film includes：Red phosphorus film is deposited in the graphene film top surface；
The second annealing is carried out to the red phosphorus film, the red phosphorus film is converted into black phosphorus film.
Optionally, the red phosphorus film is formed using chemical vapor deposition method.
Optionally, second annealing includes the laser anneal process and temperature-fall period carried out successively.
Optionally, second annealing includes circulating the laser anneal process and temperature-fall period carried out successively several times.
Optionally, the annealing temperature of the laser anneal process is 800 degrees Celsius to 1500 degrees Celsius, the temperature-fall period
Rate of temperature fall for 50 degrees Celsius per hour to 200 degrees Celsius per hour.
Optionally, before the patterned mask layer is formed, in addition to step：Place is performed etching to the black phosphorus film
Reason, adjust the atomic layer number of plies of the black phosphorus film.
Optionally, the technological parameter of the etching processing is：Chamber pressure is 5 millitorrs to 200 millitorrs, O2Flow is
5sccm to 200sccm, Ar flow are 50sccm to 500sccm, and source power is 50 watts to 500 watts, and bias power is 0 watt to 200
Watt.
Optionally, using dry etch process graphically black phosphorus film, graphene film and the semiconductor film, etching cavity
Pressure is 5 millitorrs to 200 millitorrs, O2Flow is 5sccm to 200sccm, CF4Flow is 50sccm to 200sccm, SF6Flow is
0sccm to 200sccm, NF3Flow is 0sccm to 200sccm, and HBr flows are 0sccm to 200sccm, source power be 50 watts extremely
500 watts, bias power is 0 watt to 200 watts.
The present invention also provides a kind of semiconductor structure, including：Substrate；Some discrete positioned at the substrate surface is partly led
Body layer；Graphene layer positioned at the semiconductor layer surface；Positioned at the black phosphorus layer of the graphene layer top surface.
Optionally, the thickness of the semiconductor layer is 100 angstroms to 50 nanometers；The thickness of the graphene layer is 1 angstrom to 100
Angstrom；The thickness of the black phosphorus layer is 1 angstrom to 100 angstroms.
Optionally, the substrate includes substrate and the insulating barrier positioned at substrate surface.
Compared with prior art, technical scheme has advantages below：
In the technical scheme of the forming method of semiconductor structure provided by the invention, there is provided substrate；In the substrate surface
Form semiconductor film；Graphene film is formed in the semiconductor film top surface；Formed in the graphene film top surface black
Phosphorus film；Patterned mask layer is formed in the black phosphorus film top surface；Using the patterned mask layer as mask, graphically
Black phosphorus film, graphene film and the semiconductor film, some discrete semiconductor layers are formed, positioned at partly leading in the substrate surface
The graphene layer of body layer top surface and the black phosphorus layer positioned at graphene layer top surface.The present invention is by graphene and black phosphorus knot
Close, form a kind of new semiconductor structure, the advantage of grapheme material can be played, and can has band gap using black phosphorus material
Characteristic so that the superior performance of the semiconductor structure of formation.
Further, the first annealing of the invention is laser annealing, and the annealing temperature of laser annealing is 1400 Celsius
Degree is to 1500 degrees Celsius so that in insulating process, carbon atom has higher solubility in semiconductor film top surface, therefore
In temperature-fall period, the carbon content separated out from semiconductor film top surface is also more, advantageously forms the graphite of high quality
Alkene film.
Further, the present invention also performs etching processing to the black phosphorus film of formation, so as to adjust the atom of black phosphorus film layer by layer
Number, and then cause the band gap of the black phosphorus film after etching processing to meet to require.
The present invention also provides a kind of structural behaviour superior semiconductor structure, and the semiconductor structure makes full use of graphene
The advantage of material and black phosphorus material, so as to improve the performance of semiconductor structure.
Brief description of the drawings
Fig. 1 to Fig. 2 is the structural representation for the semiconductor structure for including the graphene waveguide on silicon；
Fig. 3 to Figure 10 is the cross-sectional view that the semiconductor structure that one embodiment of the invention provides forms process.
Embodiment
From background technology, the performance of the semiconductor structure for the graphene waveguide included on silicon that prior art is formed
Have much room for improvement.
With reference to figure 1 and Fig. 2, wherein, Fig. 1 is that the stereochemical structure for the semiconductor structure for including the graphene waveguide on silicon is shown
It is intended to, Fig. 2 is the cross-sectional view that Fig. 1 is cut along line of cut AA1, including：Substrate 100, positioned at the exhausted of the surface of substrate 100
Edge layer 101, some discrete silicon layers 102, the graphene layer positioned at the top surface of silicon layer 102 positioned at the surface of insulating barrier 101
103。
It has been investigated that the material of graphene layer 103 is graphene, although grapheme material has many advantages, such as,
Material of the grapheme material close to zero band gap (band gap), it is meant that graphene layer 103 remains certain conduction
Property, it is difficult to complete the conversion between conductor and insulator, it is difficult to realize the logic Push And Release of digital circuit, therefore semiconductor structure
The problem of being faced with all the time in opening and electric leakage, the operating efficiency of semiconductor structure is low.
Further study show that black phosphorus (BP, black phosphorus) and a kind of two-dimentional (monatomic thickness) crystal, it
With wide gap tunable, the black phosphorus material with different band gap can be obtained according to the change of the atomic layer number of plies of black phosphorus, therefore
Black phosphorus can be used for detecting whole visible ray to the spectrum of infrared light region.
Therefore, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided；In the substrate surface
Form semiconductor film；Graphene film is formed in the semiconductor film top surface；Formed in the graphene film top surface black
Phosphorus film；Patterned mask layer is formed in the black phosphorus film top surface；Using the patterned mask layer as mask, graphically
Black phosphorus film, graphene film and the semiconductor film, some discrete semiconductor layers are formed, positioned at partly leading in the substrate surface
The graphene layer of body layer top surface and the black phosphorus layer positioned at graphene layer top surface.The present invention is by graphene and black phosphorus knot
Close, form a kind of new semiconductor structure, the advantage of grapheme material can be played, and can has band gap using black phosphorus material
Characteristic so that the superior performance of the semiconductor structure of formation.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 3 to Figure 10 is the cross-sectional view that the semiconductor structure that one embodiment of the invention provides forms process.
With reference to figure 3, there is provided substrate；Semiconductor film 203 is formed in the substrate surface.
In the present embodiment, the substrate includes substrate 201 and the insulating barrier 202 positioned at the surface of substrate 201.
The material of the substrate 201 is silicon, germanium, SiGe, carborundum, GaAs or gallium indium；The substrate 201 is also
It can be the silicon-Germanium substrate on the silicon substrate or insulator on insulator.Can also be formed with partly leading in the substrate 201
Body device, for example, PMOS transistor, nmos pass transistor, CMOS transistor, resistor, capacitor or inductor.
In the present embodiment, the substrate 201 is silicon substrate.
The material of the insulating barrier 202 is silica, silicon nitride, carbon dope silicon nitride or silicon oxynitride.Using chemical gas
Mutually deposition, physical vapour deposition (PVD) or atom layer deposition process form the insulating barrier 202.The insulating barrier 202 acts on
In：It is far small formed with insulating barrier 202, the refractive index of the material of insulating barrier 202 between substrate 201 and the semiconductor layer being subsequently formed
In the refractive index of the material of substrate 201, therefore the light wave and substrate that insulating barrier 202 will can transmit in the semiconductor layer that be subsequently formed
201 are isolated entirely from, so as to eliminate the harmful effect that substrate 201 absorbs light wave, it is believed that insulating barrier 202 instead of substrate
201 optical effect so that whether adulterating for substrate 201 is not limited by the waveguide being subsequently formed, therefore can be to substrate 201
Processing is doped to improve the electric property of semiconductor structure.
In the present embodiment, the material of the insulating barrier 202 is silica.
The semiconductor film 203 provides Process ba- sis to be subsequently formed semiconductor layer, subsequently carries out figure to semiconductor film 203
Shape, some discrete semiconductor layers are formed on the surface of insulating barrier 202.The material of the semiconductor film 203 is silicon, germanium or germanium
Silicon；The semiconductor film 203 is formed using chemical vapor deposition, physical vapour deposition (PVD) or atom layer deposition process.
In the present embodiment, the material of the semiconductor film 203 is silicon, is formed and described partly led using chemical vapor deposition method
Body film 203, the thickness of the semiconductor film 203 is 100 angstroms to 50 nanometers.
In other embodiments, the material of semiconductor film can also be germanium, SiGe or carborundum.
With reference to figure 4, carbonaceous material film 204 is formed on the surface of semiconductor film 203.
The carbonaceous material film 204 provides carbon atom to be subsequently formed graphene film.
In the present embodiment, the material of the carbonaceous material film 204 is polymethyl methacrylate (PMMA, Polymethyl
Methacrylate), the carbonaceous material film 204 is formed using spin coating process.
In other embodiments, the material of the carbonaceous material film can also be makrolon, polyamide, polyformaldehyde or poly-
Tetrafluoroethene.In other embodiments, the carbonaceous material film can also be formed using chemical vapor deposition method.
With reference to figure 5, the first annealing is carried out to the carbonaceous material film 204 (with reference to figure 4) and semiconductor film 203,
Graphene film 205 is formed in the top surface of semiconductor film 203.
First annealing includes temperature-rise period, insulating process and the temperature-fall period carried out successively.
First, temperature-rise period is carried out to carbonaceous material film 204 and semiconductor film 203, in temperature-rise period, carbon atom from
Decomposited in the carbonaceous material film 204.
After temperature is increased to annealing temperature, then carbonaceous material film 204 and semiconductor film 203 be incubated
Journey, in insulating process, carbon atom will decomposite from the carbonaceous material film 204, and in insulating process, semiconductor
The top surface of film 203 will be in molten condition, and the top surface of semiconductor film 203 in molten condition absorbs the decomposition
The carbon atom gone out, carbon atom have the first solubility in the top surface of semiconductor film 203.
After the top surface of semiconductor film 203 absorbs the carbon atom of certain content, lead to carbonaceous material film 204 and partly
Body film 203 is carried out in temperature-fall period, and carbon atom has the second solubility, second dissolving in the top surface of semiconductor film 203
Degree is much smaller than the first solubility, therefore carbon atom separates out from the top surface of semiconductor film 203, and the carbon atom of the precipitation is partly being led
The top surface of body film 203 cohesion nucleation, so as to form graphene film 205 in the top surface of semiconductor film 203.
The amount of carbon atom that the top surface of semiconductor film 203 absorbs determines the graphene film to be formed to a certain extent
205 number of plies, therefore when the number of plies of the graphene film 205 of required formation is more, the soaking time of annealing is longer, makes
It is more to obtain the amount of carbon atom that the top surface of semiconductor film 203 absorbs.
First annealing is laser annealing, Millisecond annealing or rapid thermal annealing.
In the present embodiment, first annealing is laser annealing, and the annealing temperature of laser annealing is 1400 degrees Celsius
To 1500 degrees Celsius.In a specific embodiment, the eutectic point of carbon atom and silicon atom (eutectic point) is
1404 degrees Celsius, under 1404 degrees Celsius, solubility of the carbon atom in silicon is 0.75% (atomic percent).In other implementations
In example, the first annealing can also be Millisecond annealing, and the annealing temperature of Millisecond annealing is 1500 degrees Celsius to 1600 degrees Celsius.
In the present embodiment, the thickness of the graphene film 205 is 1 angstrom to 100 angstroms.
After the graphene film 205 is formed, the carbonaceous material film 204 is removed.In the present embodiment, carved using wet method
Etching technique removes the carbonaceous material film 204, and the etch liquids of the wet-etching technology are acetone soln, will carry out first and moves back
Carbonaceous material film 204 after fire processing is placed in acetone soln and soak 0.5 hour to 6 hours, removal carbonaceous material film 204 it
The backward surface of graphene film 205 sprinkling deionized water is cleaned.In a specific embodiment, acetone in the acetone soln
Mass concentration be 10% to 20%, soak time be 0.5 hour to 1 hour, the concentration of the acetone soln it is smaller and soak
Time is shorter, can avoid that graphene film 205 is caused to corrode.
With reference to figure 6, in the top surface of graphene film 205 deposition red phosphorus film 206.
The material of the red phosphorus film 206 is red phosphorus (red phosphorus), and technique base is provided to be subsequently formed black phosphorus film
Plinth, subsequently the red phosphorus film 206 is made annealing treatment the red phosphorus film 206 is converted into black phosphorus film.
The red phosphorus film 206 is formed using chemical vapor deposition, physical vapour deposition (PVD) or atom layer deposition process.
In a specific embodiment, the red phosphorus film 206 is formed using chemical vapor deposition method.
The mass of red phosphorus film 206 formed using above-mentioned chemical vapor deposition method is higher and uniform with good thickness
Property, provide good Process ba- sis to be subsequently formed the black phosphorus film of high quality.
If the thickness of the red phosphorus film 206 is excessively thin, in the matter of the red phosphorus film 206 of the top surface of graphene film 205 deposition
Measure the quality and thickness evenness for the black phosphorus film that poor and thickness evenness is poor, is subsequently formed on the basis of red phosphorus film 206
Also will be relatively poor；If the thickness of the red phosphorus film 206 is blocked up, the technique that red phosphorus film 206 is subsequently converted into black phosphorus film is difficult
Degree is big, and the red phosphorus film 206 for easily causing the top surface near zone of graphene film 205 is difficult to convert into black phosphorus film.
Amid all these factors consider, in the present embodiment, the thickness of the red phosphorus film 206 is 50 angstroms to 500 angstroms.
With reference to figure 7, the second annealing is carried out to the red phosphorus film 206 (with reference to figure 6), the red phosphorus film 206 is converted
For black phosphorus film 207.
Second annealing includes the laser anneal process and temperature-fall period carried out successively, makes in the material of red phosphorus film 206
Portion's structure changes, and the material of red phosphorus film 206 is converted into black phosphorus, forms the black phosphorus film 207.
In order to improve the mass of black phosphorus film 207 of formation, in the present embodiment, second annealing includes circulating several times successively
The laser anneal process and temperature-fall period of progress, it is described refer to several times more than 1 it is any naturally for several times, until red phosphorus
Film 206 is fully converted to black phosphorus film 207.Described is several times 2-40 times, and for example, 5 times, 8 times, 12 times or 20 are inferior.
The annealing temperature of laser annealing in second annealing is unsuitable too high, otherwise easily to established graphene film
205 have undesirable effect；The annealing temperature of laser annealing in second annealing is also unsuitable too low, and annealing temperature is too low
When red phosphorus film 206 be converted into black phosphorus film 207 ability it is weak.
In a specific embodiment, the annealing temperature of the laser anneal process is 800 degrees Celsius to 1500 degrees Celsius,
The rate of temperature fall of the temperature-fall period be 50 degrees Celsius per hour to 200 degrees Celsius per hour.
With reference to figure 8, processing is performed etching to the black phosphorus film 207, adjusts the atomic layer number of plies of the black phosphorus film 207.
The band gap of the material of black phosphorus film 207 is relevant with the atomic layer number of plies.Due to (the reference of red phosphorus film 206 being previously formed
Thickness Fig. 6) is thicker, and the thickness of the corresponding black phosphorus film 207 for be formed is also thicker, therefore the atomic layer number of plies of black phosphorus film 207
It is more.
Therefore, performing etching processing to black phosphorus film 207, the atomic layer number of plies of the black phosphorus film 207 is reduced, so that black
The band gap of the material of phosphorus film 207 meets to require.
In the present embodiment, the technique at the etching is：Chamber pressure is 5 millitorrs to 200 millitorrs, O2Flow is 5sccm
To 200sccm, Ar flows are 50sccm to 500sccm, and source power is 50 watts to 500 watts, and bias power is 0 watt to 200 watts.
After etching processing, the thickness of the black phosphorus film 207 is 1 angstrom to 100 angstroms.
With reference to figure 9, patterned mask layer 208 is formed on the surface of black phosphorus film 207.
The patterned mask layer 208 defines the positions and dimensions for the semiconductor layer being subsequently formed.
The material of the patterned mask layer 208 is different from the material of semiconductor film 203；It is also, described patterned
The material of mask layer 208 is different from the material of insulating barrier 202, so that same etching technics is to patterned mask layer 208
There is higher etching selection ratio with insulating barrier 202.This is due to：
It can subsequently be etched after semiconductor layer is formed and remove patterned mask layer, and due between adjacent semiconductor layers
The surface of insulating barrier 202 be exposed, therefore the surface of the insulating barrier 202 is exposed on etching and removes patterned mask layer
Etching environment in, in order that the etching technics to the etch rate very little of insulating barrier 202, it is desirable to etching technics is to figure
The mask layer 208 and insulating barrier 202 of change have higher etching selection ratio, therefore the material of the patterned mask layer 208
It is different from the material of insulating barrier 202.
In one embodiment, the material of the patterned mask layer 208 is photoresist, by coat photoresist film,
Exposure technology and developing process form the patterned mask layer 208.
In another embodiment, the material of the patterned mask layer 208 is titanium nitride, tantalum nitride, silica, nitridation
Silicon or silicon oxynitride.
With reference to figure 10, with the patterned mask layer 208 (with reference to figure 9) for mask, the graphical black phosphorus film 207
(with reference to figure 9), graphene film 205 (with reference to figure 9) and semiconductor film 203 (with reference to figure 9), are formed some in the substrate surface
Discrete semiconductor layer 213, the graphene layer 215 positioned at the top surface of semiconductor layer 213 and pushed up positioned at graphene layer 215
The black phosphorus layer 217 on portion surface.
In the present embodiment, using dry etch process, the black phosphorus film 207, graphene film 205 and semiconductor film are etched
203, until exposing the surface of insulating barrier 202, some discrete semiconductor layers 213 are formed on the surface of insulating barrier 202.
In a specific embodiment, the technological parameter of the dry etch process is：Etching cavity pressure be 5 millitorrs extremely
200 millitorrs, O2Flow is 5sccm to 200sccm, CF4Flow is 50sccm to 200sccm, SF6Flow be 0sccm extremely
200sccm, NF3Flow is 0sccm to 200sccm, and HBr flows are 0sccm to 200sccm, and source power is 50 watts to 500 watts,
Bias power is 0 watt to 200 watts.
The semiconductor layer 213 is waveguide (waveguide), due to the freedom in semiconductor layer 213 and in insulating barrier 202
Carrier concentration is different, and semiconductor layer 213 is also different from the Refractive Index of Material of insulating barrier 202, therefore parallel to insulating barrier 202
The light wave that top surface is propagated is constrained in semiconductor layer 213, is consequently formed waveguide.
In the present embodiment, the material of the semiconductor layer 213 is silicon, and the waveguide being correspondingly formed is silicon waveguide (silicon
Waveguide), the thickness of the semiconductor layer 213 is 100 angstroms to 50 nanometers.
The material of the graphene layer 215 is graphene, and the material of the black phosphorus layer 217 is black phosphorus.
The semiconductor structure that the present embodiment is formed can be applied in optical device, for example, being applied to that light can be opened and closed
Optical modulator.When applying different voltages to graphene layer 215, the energy of electronics can change in graphene layer 215.When to
When graphene layer 215 applies the negative voltage of abundance, electronics is sucked out and causes graphene layer 215 from absorbing photon, therefore
When photon is by graphene layer 215, graphene layer 215 is fully transparent, and this time is " on ".When to graphene layer
215 when applying certain positive voltage, graphene layer 215 and transparent, but electronics is closely bundled together, and makes graphene layer
215 can not absorb photon, so as to effective " closing " light.
Also, because the top surface of graphene layer 215 is formed with black phosphorus layer 217, the material of the black phosphorus layer 217 is band gap
Material, and by changing the atomic layer number of plies of black phosphorus layer 217, the black phosphorus layer 217 for possessing different band gap can be obtained, make black phosphorus layer
217 can absorb the wavelength of visible-range and infrared light scope.
Simultaneously as in the present embodiment, black phosphorus film 207, graphene film 205 are etched using dry etch process and partly led
Body film 203, it is correspondingly formed black phosphorus layer 217, graphene layer 215 and semiconductor layer 213 so that black phosphorus layer 217, the graphite of formation
Alkene layer 215 and the side wall of semiconductor layer 213 flush, and the graphene layer 215 is uniformly covered in the top table of semiconductor layer 213
Face, avoid forming graphene in the sidewall surfaces of semiconductor layer 213；The black phosphorus layer 217 is uniformly covered in graphene layer 215 and pushed up
Portion surface, avoid forming black phosphorus in semiconductor layer 213 and the sidewall surfaces of graphene layer 215.Therefore, the half of the present embodiment formation
Conductor structure it is functional, effectively avoid extra optical absorption loss and light scattering loss.
If graphene layer does not cover the whole top surface of semiconductor layer, or the graphene positioned at semiconductor layer surface
Layer thickness homogeneity is poor, and either semiconductor layer sidewall surfaces are of poor quality formed with graphene or graphene layer, or graphite
Alkene layer side wall is formed with black phosphorus, the damage that will cause semiconductor structure to produce extra absorpting and scattering, and then influences shape
Into semiconductor structure performance.
After the semiconductor layer 213, graphene layer 215 and black phosphorus layer 217 is formed, described patterned cover is removed
Film layer 208.
Accordingly, the present invention also provides a kind of semiconductor structure, with reference to figure 10, including：
Substrate；
Positioned at some discrete semiconductor layers 213 of the substrate surface；
Positioned at the graphene layer 215 of the top surface of semiconductor layer 213；
Positioned at the black phosphorus layer 217 of the top surface of graphene layer 215.
The semiconductor structure provided will be described in detail below.
The substrate includes substrate 201 and the insulating barrier 202 positioned at the surface of substrate 201.The material of the substrate 201 is
Silicon, germanium, SiGe, carborundum, GaAs or gallium indium；The substrate 201 can also be silicon substrate or insulation on insulator
Silicon-Germanium substrate on body.In the present embodiment, the substrate 201 is silicon substrate.
The material of the insulating barrier 202 is silica, silicon nitride or silicon oxynitride.The refraction of the material of insulating barrier 202
Rate is less than the refractive index of the material of substrate 201, therefore insulating barrier 202 can be by the light wave transmitted in semiconductor layer 213 and substrate 201
Completely isolated opening, so as to eliminate the harmful effect that substrate 201 absorbs light wave.In the present embodiment, the material of the insulating barrier 202
For silica.
It is waveguide that semiconductor layer 213 is searched by Soviet Union, and semiconductor layer 213 is interior different from the free carrier concentration in insulating barrier 202,
Semiconductor layer 213 is also different from the Refractive Index of Material of insulating barrier 202, therefore is being propagated parallel to the top surface of insulating barrier 202
Light wave is bound in semiconductor layer 213, is consequently formed waveguide.
In the present embodiment, the material of the semiconductor layer 213 is silicon, and semiconductor layer 213 is silicon waveguide, the semiconductor layer
213 thickness is 100 angstroms to 50 nanometers.
The material of the graphene layer 215 is graphene, and the thickness of graphene layer 215 is 1 angstrom to 100 angstroms；The black phosphorus
The material of layer 217 is black phosphorus, and the thickness of black phosphorus layer 217 is 1 angstrom to 100 angstroms.
The semiconductor structure that the present embodiment provides can be applied in optical device, for example, being applied to that light can be opened and closed
Optical modulator.When applying different voltages to graphene layer 215, the energy of electronics can change in graphene layer 215.When to
When graphene layer 215 applies the negative voltage of abundance, electronics is sucked out and causes graphene layer 215 from absorbing photon, therefore
When photon is by graphene layer 215, graphene layer 215 is fully transparent, and this time is " on ".When to graphene layer
215 when applying certain positive voltage, graphene layer 215 and transparent, but electronics is closely bundled together, and makes graphene layer
215 can not absorb photon, so as to effective " closing " light.
Also, because the top surface of graphene layer 215 is formed with black phosphorus layer 217, the material of the black phosphorus layer 217 is band gap
Material, and by changing the atomic layer number of plies of black phosphorus layer 217, the black phosphorus layer 217 for possessing different band gap can be obtained, make black phosphorus layer
217 can absorb the wavelength of visible-range and infrared light scope.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (19)
- A kind of 1. forming method of semiconductor structure, it is characterised in that including：Substrate is provided；Semiconductor film is formed in the substrate surface；Graphene film is formed in the semiconductor film top surface；Black phosphorus film is formed in the graphene film top surface；Patterned mask layer is formed in the black phosphorus film top surface；Using the patterned mask layer as mask, graphical black phosphorus film, graphene film and the semiconductor film, in the base Basal surface forms some discrete semiconductor layers, the graphene layer positioned at semiconductor layer surface and positioned at graphene layer top The black phosphorus layer on portion surface.
- 2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the method for forming the graphene film Including：Carbonaceous material film is formed on the semiconductor film surface；First is carried out to the carbonaceous material film and semiconductor film to move back Fire processing, graphene film is formed in the semiconductor film top surface；After the described first annealing, remove described carbon containing Material membrane.
- 3. the forming method of semiconductor structure as claimed in claim 2, it is characterised in that the material of the carbonaceous material film is Poly- methyl-prop hexenoic acid methyl esters, makrolon, polyamide, polyformaldehyde or polytetrafluoroethylene (PTFE).
- 4. the forming method of semiconductor structure as claimed in claim 2, it is characterised in that first annealing is laser Annealing, Millisecond annealing or rapid thermal annealing.
- 5. the forming method of semiconductor structure as claimed in claim 4, it is characterised in that the annealing temperature of the laser annealing For 1400 degrees Celsius to 1500 degrees Celsius.
- 6. the forming method of semiconductor structure as claimed in claim 2, it is characterised in that it is described first annealing include according to Temperature-rise period, insulating process and the temperature-fall period of secondary progress.
- 7. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that in the temperature-rise period and insulation During, carbon atom decomposites from the carbonaceous material film；In the insulating process, at the semiconductor film top surface In molten condition, the semiconductor film top surface in molten condition absorb described in the carbon atom that decomposites；In the drop During temperature, the carbon atom separates out from semiconductor film top surface, and the carbon atom of precipitation condenses in semiconductor film top surface Nucleation, graphene film is formed in the semiconductor film top surface.
- 8. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the thickness of the graphene layer is 1 Angstrom to 100 angstroms；The thickness of the black phosphorus layer is 1 angstrom to 100 angstroms.
- 9. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that form the technique step of the black phosphorus film Suddenly include：Red phosphorus film is deposited in the graphene film top surface；The second annealing is carried out to the red phosphorus film, will be described red Phosphorus film is converted into black phosphorus film.
- 10. the forming method of semiconductor structure as claimed in claim 9, it is characterised in that using chemical vapor deposition method Form the red phosphorus film.
- 11. the forming method of semiconductor structure as claimed in claim 9, it is characterised in that second annealing is included successively The laser anneal process and temperature-fall period of progress.
- 12. the forming method of semiconductor structure as claimed in claim 11, it is characterised in that second annealing includes some It is secondary to circulate the laser anneal process and temperature-fall period carried out successively.
- 13. the forming method of the semiconductor structure as described in claim 11 or 12, it is characterised in that the laser anneal process Annealing temperature be 800 degrees Celsius to 1500 degrees Celsius, the rate of temperature fall of the temperature-fall period is for 50 degrees Celsius per hour to 200 Degree Celsius per hour.
- 14. the forming method of the semiconductor structure as described in claim 1 or 9, it is characterised in that described patterned being formed Before mask layer, in addition to step：Processing is performed etching to the black phosphorus film, adjusts the atomic layer number of plies of the black phosphorus film.
- 15. the forming method of semiconductor structure as claimed in claim 14, it is characterised in that the technique ginseng of the etching processing Number is：Chamber pressure is 5 millitorrs to 200 millitorrs, O2Flow is 5sccm to 200sccm,Ar flows are 50sccm to 500sccm, and source power is 50 watts to 500 watts, and bias power is 0 watt to 200 watts.
- 16. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that using dry etch process figure Change black phosphorus film, graphene film and the semiconductor film, etching cavity pressure is 5 millitorrs to 200 millitorrs, O2Flow is 5sccm To 200sccm, CF4Flow is 50sccm to 200sccm,SF6Flow is 0sccm to 200sccm, NF3Flow is 0sccm to 200sccm, and HBr flows are 0sccm to 200sccm, source Power is 50 watts to 500 watts, and bias power is 0 watt to 200 watts.
- A kind of 17. semiconductor structure, it is characterised in that including：Substrate；Positioned at some discrete semiconductor layers of the substrate surface；Graphene layer positioned at the semiconductor layer surface；Positioned at the black phosphorus layer of the graphene layer top surface.
- 18. semiconductor structure as claimed in claim 17, it is characterised in that the thickness of the semiconductor layer is 100 angstroms to 50 Nanometer；The thickness of the graphene layer is 1 angstrom to 100 angstroms；The thickness of the black phosphorus layer is 1 angstrom to 100 angstroms.
- 19. semiconductor structure as claimed in claim 17, it is characterised in that the substrate includes substrate and positioned at substrate table The insulating barrier in face.
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